Revision 92f9a4f1
b/hw/apb_pci.c | ||
---|---|---|
304 | 304 |
return rc; |
305 | 305 |
} |
306 | 306 |
|
307 |
pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN); |
|
308 |
pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA); |
|
309 |
|
|
310 | 307 |
/* |
311 | 308 |
* command register: |
312 | 309 |
* According to PCI bridge spec, after reset |
... | ... | |
321 | 318 |
pci_set_word(dev->config + PCI_STATUS, |
322 | 319 |
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
323 | 320 |
PCI_STATUS_DEVSEL_MEDIUM); |
324 |
pci_set_byte(dev->config + PCI_REVISION_ID, 0x11); |
|
325 | 321 |
return 0; |
326 | 322 |
} |
327 | 323 |
|
... | ... | |
436 | 432 |
|
437 | 433 |
static int pbm_pci_host_init(PCIDevice *d) |
438 | 434 |
{ |
439 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN); |
|
440 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE); |
|
441 | 435 |
pci_set_word(d->config + PCI_COMMAND, |
442 | 436 |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
443 | 437 |
pci_set_word(d->config + PCI_STATUS, |
444 | 438 |
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
445 | 439 |
PCI_STATUS_DEVSEL_MEDIUM); |
446 |
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
|
447 | 440 |
return 0; |
448 | 441 |
} |
449 | 442 |
|
... | ... | |
451 | 444 |
.qdev.name = "pbm", |
452 | 445 |
.qdev.size = sizeof(PCIDevice), |
453 | 446 |
.init = pbm_pci_host_init, |
447 |
.vendor_id = PCI_VENDOR_ID_SUN, |
|
448 |
.device_id = PCI_DEVICE_ID_SUN_SABRE, |
|
449 |
.class_id = PCI_CLASS_BRIDGE_HOST, |
|
454 | 450 |
.is_bridge = 1, |
455 | 451 |
}; |
456 | 452 |
|
... | ... | |
468 | 464 |
.qdev.reset = pci_bridge_reset, |
469 | 465 |
.init = apb_pci_bridge_initfn, |
470 | 466 |
.exit = pci_bridge_exitfn, |
467 |
.vendor_id = PCI_VENDOR_ID_SUN, |
|
468 |
.device_id = PCI_DEVICE_ID_SUN_SIMBA, |
|
469 |
.revision = 0x11, |
|
471 | 470 |
.config_write = pci_bridge_write_config, |
472 | 471 |
.is_bridge = 1, |
473 | 472 |
}; |
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