Revision 930f3fe1
| b/hw/apb_pci.c | ||
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| 39 | 39 |
#define APB_DPRINTF(fmt, ...) |
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#endif |
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/* |
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* Chipset docs: |
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* PBM: "UltraSPARC IIi User's Manual", |
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* http://www.sun.com/processors/manuals/805-0087.pdf |
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* |
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* APB: "Advanced PCI Bridge (APB) User's Manual", |
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* http://www.sun.com/processors/manuals/805-1251.pdf |
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*/ |
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typedef target_phys_addr_t pci_addr_t; |
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#include "pci_host.h" |
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| b/hw/m48t59.c | ||
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| 41 | 41 |
* alarm and a watchdog timer and related control registers. In the |
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* PPC platform there is also a nvram lock function. |
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*/ |
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/* |
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* Chipset docs: |
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf |
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf |
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf |
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*/ |
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struct m48t59_t {
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/* Model parameters */ |
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uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
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