Revision 932e71cd target-mips/translate_init.c
b/target-mips/translate_init.c | ||
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495 | 495 |
env->fpus[i].fcr0 = def->CP1_fcr0; |
496 | 496 |
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497 | 497 |
memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
498 |
if (env->user_mode_only) {
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499 |
if (env->CP0_Config1 & (1 << CP0C1_FP))
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500 |
env->hflags |= MIPS_HFLAG_FPU;
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498 |
#if defined(CONFIG_USER_ONLY)
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if (env->CP0_Config1 & (1 << CP0C1_FP)) |
|
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env->hflags |= MIPS_HFLAG_FPU; |
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501 | 501 |
#ifdef TARGET_MIPS64 |
502 |
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
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503 |
env->hflags |= MIPS_HFLAG_F64; |
|
502 |
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
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env->hflags |= MIPS_HFLAG_F64; |
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504 |
#endif |
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504 | 505 |
#endif |
505 |
} |
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506 | 506 |
} |
507 | 507 |
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508 | 508 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
... | ... | |
520 | 520 |
// (0x04 << CP0MVPC0_PTC); |
521 | 521 |
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
522 | 522 |
(0x04 << CP0MVPC0_PTC); |
523 |
#if !defined(CONFIG_USER_ONLY) |
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523 | 524 |
/* Usermode has no TLB support */ |
524 |
if (!env->user_mode_only)
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525 |
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
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env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
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526 |
#endif
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526 | 527 |
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527 | 528 |
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
528 | 529 |
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
... | ... | |
572 | 573 |
env->insn_flags = def->insn_flags; |
573 | 574 |
|
574 | 575 |
#ifndef CONFIG_USER_ONLY |
575 |
if (!env->user_mode_only) |
|
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mmu_init(env, def); |
|
576 |
mmu_init(env, def); |
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577 | 577 |
#endif |
578 | 578 |
fpu_init(env, def); |
579 | 579 |
mvp_init(env, def); |
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