Revision 93b12ccc

b/target-mips/op.c
3 3
 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
b/target-mips/op_mem.c
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    glue(stq, MEMSUFFIX)(T0, DT0);
221 221
    RETURN();
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}
223
void glue(op_lwxc1, MEMSUFFIX) (void)
224
{
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    WT0 = glue(ldl, MEMSUFFIX)(T0 + T1);
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    RETURN();
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}
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void glue(op_swxc1, MEMSUFFIX) (void)
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{
230
    glue(stl, MEMSUFFIX)(T0 + T1, WT0);
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    RETURN();
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}
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void glue(op_ldxc1, MEMSUFFIX) (void)
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{
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    DT0 = glue(ldq, MEMSUFFIX)(T0 + T1);
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    RETURN();
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}
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void glue(op_sdxc1, MEMSUFFIX) (void)
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{
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    glue(stq, MEMSUFFIX)(T0 + T1, DT0);
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    RETURN();
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}
243 223
void glue(op_luxc1, MEMSUFFIX) (void)
244 224
{
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    /* XXX: is defined as unaligned */
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    DT0 = glue(ldq, MEMSUFFIX)(T0 + T1);
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    DT0 = glue(ldq, MEMSUFFIX)(T0 & ~0x7);
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    RETURN();
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}
249 228
void glue(op_suxc1, MEMSUFFIX) (void)
250 229
{
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    /* XXX: is defined as unaligned */
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    glue(stq, MEMSUFFIX)(T0 + T1, DT0);
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    glue(stq, MEMSUFFIX)(T0 & ~0x7, DT0);
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    RETURN();
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}
b/target-mips/translate.c
711 711
OP_ST_TABLE(wc1);
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OP_LD_TABLE(dc1);
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OP_ST_TABLE(dc1);
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OP_LD_TABLE(wxc1);
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OP_ST_TABLE(wxc1);
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OP_LD_TABLE(dxc1);
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OP_ST_TABLE(dxc1);
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OP_LD_TABLE(uxc1);
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OP_ST_TABLE(uxc1);
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......
1092 1088
        return;
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    }
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    GEN_STORE_TN_REG(rt, T0);
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    MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
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    MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
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}
1097 1093

  
1098 1094
/* Arithmetic */
......
5242 5238

  
5243 5239
/* Coprocessor 3 (FPU) */
5244 5240
static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
5245
                           int base, int index)
5241
                           int fs, int base, int index)
5246 5242
{
5247 5243
    const char *opn = "extended float load/store";
5244
    int store = 0;
5248 5245

  
5249 5246
    /* All of those work only on 64bit FPUs. */
5250 5247
    gen_op_cp1_64bitmode();
5251
    GEN_LOAD_REG_TN(T0, base);
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    GEN_LOAD_REG_TN(T1, index);
5248
    if (base == 0) {
5249
        if (index == 0)
5250
            gen_op_reset_T0();
5251
        else
5252
            GEN_LOAD_REG_TN(T0, index);
5253
    } else if (index == 0) {
5254
        GEN_LOAD_REG_TN(T0, base);
5255
    } else {
5256
        GEN_LOAD_REG_TN(T0, base);
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        GEN_LOAD_REG_TN(T1, index);
5258
        gen_op_addr_add();
5259
    }
5253 5260
    /* Don't do NOP if destination is zero: we must perform the actual
5254 5261
     * memory access
5255 5262
     */
5256 5263
    switch (opc) {
5257 5264
    case OPC_LWXC1:
5258
        op_ldst(lwxc1);
5265
        op_ldst(lwc1);
5259 5266
        GEN_STORE_FTN_FREG(fd, WT0);
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        opn = "lwxc1";
5261 5268
        break;
5262 5269
    case OPC_LDXC1:
5263
        op_ldst(ldxc1);
5270
        op_ldst(ldc1);
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        GEN_STORE_FTN_FREG(fd, DT0);
5265 5272
        opn = "ldxc1";
5266 5273
        break;
......
5270 5277
        opn = "luxc1";
5271 5278
        break;
5272 5279
    case OPC_SWXC1:
5273
        GEN_LOAD_FREG_FTN(WT0, fd);
5274
        op_ldst(swxc1);
5280
        GEN_LOAD_FREG_FTN(WT0, fs);
5281
        op_ldst(swc1);
5275 5282
        opn = "swxc1";
5283
        store = 1;
5276 5284
        break;
5277 5285
    case OPC_SDXC1:
5278
        GEN_LOAD_FREG_FTN(DT0, fd);
5279
        op_ldst(sdxc1);
5286
        GEN_LOAD_FREG_FTN(DT0, fs);
5287
        op_ldst(sdc1);
5280 5288
        opn = "sdxc1";
5289
        store = 1;
5281 5290
        break;
5282 5291
    case OPC_SUXC1:
5283
        GEN_LOAD_FREG_FTN(DT0, fd);
5292
        GEN_LOAD_FREG_FTN(DT0, fs);
5284 5293
        op_ldst(suxc1);
5285 5294
        opn = "suxc1";
5295
        store = 1;
5286 5296
        break;
5287 5297
    default:
5288 5298
        MIPS_INVAL(opn);
5289 5299
        generate_exception(ctx, EXCP_RI);
5290 5300
        return;
5291 5301
    }
5292
    MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[fd],regnames[index], regnames[base]);
5302
    MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
5303
               regnames[index], regnames[base]);
5293 5304
}
5294 5305

  
5295 5306
static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
......
5882 5893
            case OPC_SWXC1:
5883 5894
            case OPC_SDXC1:
5884 5895
            case OPC_SUXC1:
5885
                gen_flt3_ldst(ctx, op1, sa, rs, rt);
5896
                gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
5886 5897
                break;
5887 5898
            case OPC_PREFX:
5888 5899
                /* treat as noop */

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