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/*
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* qemu user main
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <errno.h> |
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#include <unistd.h> |
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#include <sys/mman.h> |
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#include "qemu.h" |
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#include "qemu-common.h" |
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#include "cache-utils.h" |
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/* For tb_lock */
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#include "exec-all.h" |
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#define DEBUG_LOGFILE "/tmp/qemu.log" |
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static const char *interp_prefix = CONFIG_QEMU_PREFIX; |
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const char *qemu_uname_release = CONFIG_UNAME_RELEASE; |
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#if defined(__i386__) && !defined(CONFIG_STATIC)
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/* Force usage of an ELF interpreter even if it is an ELF shared
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object ! */
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const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2"; |
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#endif
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|
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/* for recent libc, we add these dummy symbols which are not declared
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when generating a linked object (bug in ld ?) */
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#if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC) |
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asm(".globl __preinit_array_start\n" |
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".globl __preinit_array_end\n"
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".globl __init_array_start\n"
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".globl __init_array_end\n"
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".globl __fini_array_start\n"
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".globl __fini_array_end\n"
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".section \".rodata\"\n"
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"__preinit_array_start:\n"
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"__preinit_array_end:\n"
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"__init_array_start:\n"
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"__init_array_end:\n"
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"__fini_array_start:\n"
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"__fini_array_end:\n"
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".long 0\n"
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".previous\n");
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#endif
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/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
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we allocate a bigger stack. Need a better solution, for example
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by remapping the process stack directly at the right place */
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unsigned long x86_stack_size = 512 * 1024; |
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void gemu_log(const char *fmt, ...) |
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{ |
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va_list ap; |
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va_start(ap, fmt); |
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vfprintf(stderr, fmt, ap); |
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va_end(ap); |
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} |
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|
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void cpu_outb(CPUState *env, int addr, int val) |
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{ |
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fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
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} |
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|
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void cpu_outw(CPUState *env, int addr, int val) |
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{ |
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fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
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} |
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|
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void cpu_outl(CPUState *env, int addr, int val) |
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{ |
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fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
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} |
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|
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int cpu_inb(CPUState *env, int addr) |
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{ |
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fprintf(stderr, "inb: port=0x%04x\n", addr);
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return 0; |
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} |
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int cpu_inw(CPUState *env, int addr) |
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{ |
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fprintf(stderr, "inw: port=0x%04x\n", addr);
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return 0; |
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} |
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int cpu_inl(CPUState *env, int addr) |
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{ |
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fprintf(stderr, "inl: port=0x%04x\n", addr);
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return 0; |
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} |
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#if defined(TARGET_I386)
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int cpu_get_pic_interrupt(CPUState *env)
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{ |
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return -1; |
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} |
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#endif
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/* timers for rdtsc */
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#if 0
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static uint64_t emu_time;
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int64_t cpu_get_real_ticks(void)
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{
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return emu_time++;
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}
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#endif
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#if defined(USE_NPTL)
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/***********************************************************/
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/* Helper routines for implementing atomic operations. */
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/* To implement exclusive operations we force all cpus to syncronise.
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We don't require a full sync, only that no cpus are executing guest code.
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The alternative is to map target atomic ops onto host equivalents,
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which requires quite a lot of per host/target work. */
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static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
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static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
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static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
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static int pending_cpus; |
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/* Make sure everything is in a consistent state for calling fork(). */
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void fork_start(void) |
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{ |
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mmap_fork_start(); |
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pthread_mutex_lock(&tb_lock); |
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pthread_mutex_lock(&exclusive_lock); |
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} |
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void fork_end(int child) |
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{ |
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if (child) {
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/* Child processes created by fork() only have a single thread.
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Discard information about the parent threads. */
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first_cpu = thread_env; |
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thread_env->next_cpu = NULL;
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pending_cpus = 0;
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pthread_mutex_init(&exclusive_lock, NULL);
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pthread_cond_init(&exclusive_cond, NULL);
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pthread_cond_init(&exclusive_resume, NULL);
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pthread_mutex_init(&tb_lock, NULL);
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gdbserver_fork(thread_env); |
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} else {
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pthread_mutex_unlock(&exclusive_lock); |
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pthread_mutex_unlock(&tb_lock); |
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} |
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mmap_fork_end(child); |
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} |
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/* Wait for pending exclusive operations to complete. The exclusive lock
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must be held. */
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static inline void exclusive_idle(void) |
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{ |
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while (pending_cpus) {
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pthread_cond_wait(&exclusive_resume, &exclusive_lock); |
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} |
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} |
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/* Start an exclusive operation.
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Must only be called from outside cpu_arm_exec. */
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static inline void start_exclusive(void) |
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{ |
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CPUState *other; |
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pthread_mutex_lock(&exclusive_lock); |
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exclusive_idle(); |
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pending_cpus = 1;
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/* Make all other cpus stop executing. */
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for (other = first_cpu; other; other = other->next_cpu) {
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if (other->running) {
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pending_cpus++; |
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cpu_interrupt(other, CPU_INTERRUPT_EXIT); |
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} |
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} |
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if (pending_cpus > 1) { |
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pthread_cond_wait(&exclusive_cond, &exclusive_lock); |
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} |
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} |
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/* Finish an exclusive operation. */
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static inline void end_exclusive(void) |
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{ |
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pending_cpus = 0;
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pthread_cond_broadcast(&exclusive_resume); |
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pthread_mutex_unlock(&exclusive_lock); |
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} |
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/* Wait for exclusive ops to finish, and begin cpu execution. */
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static inline void cpu_exec_start(CPUState *env) |
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{ |
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pthread_mutex_lock(&exclusive_lock); |
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exclusive_idle(); |
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env->running = 1;
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pthread_mutex_unlock(&exclusive_lock); |
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} |
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/* Mark cpu as not executing, and release pending exclusive ops. */
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static inline void cpu_exec_end(CPUState *env) |
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{ |
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pthread_mutex_lock(&exclusive_lock); |
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env->running = 0;
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if (pending_cpus > 1) { |
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pending_cpus--; |
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if (pending_cpus == 1) { |
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pthread_cond_signal(&exclusive_cond); |
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} |
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} |
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exclusive_idle(); |
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pthread_mutex_unlock(&exclusive_lock); |
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} |
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#else /* if !USE_NPTL */ |
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/* These are no-ops because we are not threadsafe. */
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static inline void cpu_exec_start(CPUState *env) |
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{ |
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} |
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static inline void cpu_exec_end(CPUState *env) |
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{ |
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} |
244 |
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static inline void start_exclusive(void) |
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{ |
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} |
248 |
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static inline void end_exclusive(void) |
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{ |
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} |
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void fork_start(void) |
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{ |
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} |
256 |
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void fork_end(int child) |
258 |
{ |
259 |
if (child) {
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gdbserver_fork(thread_env); |
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} |
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} |
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#endif
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#ifdef TARGET_I386
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/***********************************************************/
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/* CPUX86 core interface */
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void cpu_smm_update(CPUState *env)
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{ |
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} |
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{ |
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return cpu_get_real_ticks();
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} |
278 |
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static void write_dt(void *ptr, unsigned long addr, unsigned long limit, |
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int flags)
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{ |
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unsigned int e1, e2; |
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uint32_t *p; |
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e1 = (addr << 16) | (limit & 0xffff); |
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e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); |
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e2 |= flags; |
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p = ptr; |
288 |
p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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} |
291 |
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static uint64_t *idt_table;
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#ifdef TARGET_X86_64
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static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, |
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uint64_t addr, unsigned int sel) |
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{ |
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uint32_t *p, e1, e2; |
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e1 = (addr & 0xffff) | (sel << 16); |
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e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); |
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p = ptr; |
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p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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p[2] = tswap32(addr >> 32); |
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p[3] = 0; |
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} |
306 |
/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl) |
308 |
{ |
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0); |
310 |
} |
311 |
#else
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static void set_gate(void *ptr, unsigned int type, unsigned int dpl, |
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uint32_t addr, unsigned int sel) |
314 |
{ |
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uint32_t *p, e1, e2; |
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e1 = (addr & 0xffff) | (sel << 16); |
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e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); |
318 |
p = ptr; |
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p[0] = tswap32(e1);
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p[1] = tswap32(e2);
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} |
322 |
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl) |
325 |
{ |
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set_gate(idt_table + n, 0, dpl, 0, 0); |
327 |
} |
328 |
#endif
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329 |
|
330 |
void cpu_loop(CPUX86State *env)
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{ |
332 |
int trapnr;
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abi_ulong pc; |
334 |
target_siginfo_t info; |
335 |
|
336 |
for(;;) {
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trapnr = cpu_x86_exec(env); |
338 |
switch(trapnr) {
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case 0x80: |
340 |
/* linux syscall from int $0x80 */
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341 |
env->regs[R_EAX] = do_syscall(env, |
342 |
env->regs[R_EAX], |
343 |
env->regs[R_EBX], |
344 |
env->regs[R_ECX], |
345 |
env->regs[R_EDX], |
346 |
env->regs[R_ESI], |
347 |
env->regs[R_EDI], |
348 |
env->regs[R_EBP]); |
349 |
break;
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350 |
#ifndef TARGET_ABI32
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351 |
case EXCP_SYSCALL:
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352 |
/* linux syscall from syscall intruction */
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353 |
env->regs[R_EAX] = do_syscall(env, |
354 |
env->regs[R_EAX], |
355 |
env->regs[R_EDI], |
356 |
env->regs[R_ESI], |
357 |
env->regs[R_EDX], |
358 |
env->regs[10],
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env->regs[8],
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360 |
env->regs[9]);
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361 |
env->eip = env->exception_next_eip; |
362 |
break;
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363 |
#endif
|
364 |
case EXCP0B_NOSEG:
|
365 |
case EXCP0C_STACK:
|
366 |
info.si_signo = SIGBUS; |
367 |
info.si_errno = 0;
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368 |
info.si_code = TARGET_SI_KERNEL; |
369 |
info._sifields._sigfault._addr = 0;
|
370 |
queue_signal(env, info.si_signo, &info); |
371 |
break;
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372 |
case EXCP0D_GPF:
|
373 |
/* XXX: potential problem if ABI32 */
|
374 |
#ifndef TARGET_X86_64
|
375 |
if (env->eflags & VM_MASK) {
|
376 |
handle_vm86_fault(env); |
377 |
} else
|
378 |
#endif
|
379 |
{ |
380 |
info.si_signo = SIGSEGV; |
381 |
info.si_errno = 0;
|
382 |
info.si_code = TARGET_SI_KERNEL; |
383 |
info._sifields._sigfault._addr = 0;
|
384 |
queue_signal(env, info.si_signo, &info); |
385 |
} |
386 |
break;
|
387 |
case EXCP0E_PAGE:
|
388 |
info.si_signo = SIGSEGV; |
389 |
info.si_errno = 0;
|
390 |
if (!(env->error_code & 1)) |
391 |
info.si_code = TARGET_SEGV_MAPERR; |
392 |
else
|
393 |
info.si_code = TARGET_SEGV_ACCERR; |
394 |
info._sifields._sigfault._addr = env->cr[2];
|
395 |
queue_signal(env, info.si_signo, &info); |
396 |
break;
|
397 |
case EXCP00_DIVZ:
|
398 |
#ifndef TARGET_X86_64
|
399 |
if (env->eflags & VM_MASK) {
|
400 |
handle_vm86_trap(env, trapnr); |
401 |
} else
|
402 |
#endif
|
403 |
{ |
404 |
/* division by zero */
|
405 |
info.si_signo = SIGFPE; |
406 |
info.si_errno = 0;
|
407 |
info.si_code = TARGET_FPE_INTDIV; |
408 |
info._sifields._sigfault._addr = env->eip; |
409 |
queue_signal(env, info.si_signo, &info); |
410 |
} |
411 |
break;
|
412 |
case EXCP01_DB:
|
413 |
case EXCP03_INT3:
|
414 |
#ifndef TARGET_X86_64
|
415 |
if (env->eflags & VM_MASK) {
|
416 |
handle_vm86_trap(env, trapnr); |
417 |
} else
|
418 |
#endif
|
419 |
{ |
420 |
info.si_signo = SIGTRAP; |
421 |
info.si_errno = 0;
|
422 |
if (trapnr == EXCP01_DB) {
|
423 |
info.si_code = TARGET_TRAP_BRKPT; |
424 |
info._sifields._sigfault._addr = env->eip; |
425 |
} else {
|
426 |
info.si_code = TARGET_SI_KERNEL; |
427 |
info._sifields._sigfault._addr = 0;
|
428 |
} |
429 |
queue_signal(env, info.si_signo, &info); |
430 |
} |
431 |
break;
|
432 |
case EXCP04_INTO:
|
433 |
case EXCP05_BOUND:
|
434 |
#ifndef TARGET_X86_64
|
435 |
if (env->eflags & VM_MASK) {
|
436 |
handle_vm86_trap(env, trapnr); |
437 |
} else
|
438 |
#endif
|
439 |
{ |
440 |
info.si_signo = SIGSEGV; |
441 |
info.si_errno = 0;
|
442 |
info.si_code = TARGET_SI_KERNEL; |
443 |
info._sifields._sigfault._addr = 0;
|
444 |
queue_signal(env, info.si_signo, &info); |
445 |
} |
446 |
break;
|
447 |
case EXCP06_ILLOP:
|
448 |
info.si_signo = SIGILL; |
449 |
info.si_errno = 0;
|
450 |
info.si_code = TARGET_ILL_ILLOPN; |
451 |
info._sifields._sigfault._addr = env->eip; |
452 |
queue_signal(env, info.si_signo, &info); |
453 |
break;
|
454 |
case EXCP_INTERRUPT:
|
455 |
/* just indicate that signals should be handled asap */
|
456 |
break;
|
457 |
case EXCP_DEBUG:
|
458 |
{ |
459 |
int sig;
|
460 |
|
461 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
462 |
if (sig)
|
463 |
{ |
464 |
info.si_signo = sig; |
465 |
info.si_errno = 0;
|
466 |
info.si_code = TARGET_TRAP_BRKPT; |
467 |
queue_signal(env, info.si_signo, &info); |
468 |
} |
469 |
} |
470 |
break;
|
471 |
default:
|
472 |
pc = env->segs[R_CS].base + env->eip; |
473 |
fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
|
474 |
(long)pc, trapnr);
|
475 |
abort(); |
476 |
} |
477 |
process_pending_signals(env); |
478 |
} |
479 |
} |
480 |
#endif
|
481 |
|
482 |
#ifdef TARGET_ARM
|
483 |
|
484 |
static void arm_cache_flush(abi_ulong start, abi_ulong last) |
485 |
{ |
486 |
abi_ulong addr, last1; |
487 |
|
488 |
if (last < start)
|
489 |
return;
|
490 |
addr = start; |
491 |
for(;;) {
|
492 |
last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
|
493 |
if (last1 > last)
|
494 |
last1 = last; |
495 |
tb_invalidate_page_range(addr, last1 + 1);
|
496 |
if (last1 == last)
|
497 |
break;
|
498 |
addr = last1 + 1;
|
499 |
} |
500 |
} |
501 |
|
502 |
/* Handle a jump to the kernel code page. */
|
503 |
static int |
504 |
do_kernel_trap(CPUARMState *env) |
505 |
{ |
506 |
uint32_t addr; |
507 |
uint32_t cpsr; |
508 |
uint32_t val; |
509 |
|
510 |
switch (env->regs[15]) { |
511 |
case 0xffff0fa0: /* __kernel_memory_barrier */ |
512 |
/* ??? No-op. Will need to do better for SMP. */
|
513 |
break;
|
514 |
case 0xffff0fc0: /* __kernel_cmpxchg */ |
515 |
/* XXX: This only works between threads, not between processes.
|
516 |
It's probably possible to implement this with native host
|
517 |
operations. However things like ldrex/strex are much harder so
|
518 |
there's not much point trying. */
|
519 |
start_exclusive(); |
520 |
cpsr = cpsr_read(env); |
521 |
addr = env->regs[2];
|
522 |
/* FIXME: This should SEGV if the access fails. */
|
523 |
if (get_user_u32(val, addr))
|
524 |
val = ~env->regs[0];
|
525 |
if (val == env->regs[0]) { |
526 |
val = env->regs[1];
|
527 |
/* FIXME: Check for segfaults. */
|
528 |
put_user_u32(val, addr); |
529 |
env->regs[0] = 0; |
530 |
cpsr |= CPSR_C; |
531 |
} else {
|
532 |
env->regs[0] = -1; |
533 |
cpsr &= ~CPSR_C; |
534 |
} |
535 |
cpsr_write(env, cpsr, CPSR_C); |
536 |
end_exclusive(); |
537 |
break;
|
538 |
case 0xffff0fe0: /* __kernel_get_tls */ |
539 |
env->regs[0] = env->cp15.c13_tls2;
|
540 |
break;
|
541 |
default:
|
542 |
return 1; |
543 |
} |
544 |
/* Jump back to the caller. */
|
545 |
addr = env->regs[14];
|
546 |
if (addr & 1) { |
547 |
env->thumb = 1;
|
548 |
addr &= ~1;
|
549 |
} |
550 |
env->regs[15] = addr;
|
551 |
|
552 |
return 0; |
553 |
} |
554 |
|
555 |
void cpu_loop(CPUARMState *env)
|
556 |
{ |
557 |
int trapnr;
|
558 |
unsigned int n, insn; |
559 |
target_siginfo_t info; |
560 |
uint32_t addr; |
561 |
|
562 |
for(;;) {
|
563 |
cpu_exec_start(env); |
564 |
trapnr = cpu_arm_exec(env); |
565 |
cpu_exec_end(env); |
566 |
switch(trapnr) {
|
567 |
case EXCP_UDEF:
|
568 |
{ |
569 |
TaskState *ts = env->opaque; |
570 |
uint32_t opcode; |
571 |
int rc;
|
572 |
|
573 |
/* we handle the FPU emulation here, as Linux */
|
574 |
/* we get the opcode */
|
575 |
/* FIXME - what to do if get_user() fails? */
|
576 |
get_user_u32(opcode, env->regs[15]);
|
577 |
|
578 |
rc = EmulateAll(opcode, &ts->fpa, env); |
579 |
if (rc == 0) { /* illegal instruction */ |
580 |
info.si_signo = SIGILL; |
581 |
info.si_errno = 0;
|
582 |
info.si_code = TARGET_ILL_ILLOPN; |
583 |
info._sifields._sigfault._addr = env->regs[15];
|
584 |
queue_signal(env, info.si_signo, &info); |
585 |
} else if (rc < 0) { /* FP exception */ |
586 |
int arm_fpe=0; |
587 |
|
588 |
/* translate softfloat flags to FPSR flags */
|
589 |
if (-rc & float_flag_invalid)
|
590 |
arm_fpe |= BIT_IOC; |
591 |
if (-rc & float_flag_divbyzero)
|
592 |
arm_fpe |= BIT_DZC; |
593 |
if (-rc & float_flag_overflow)
|
594 |
arm_fpe |= BIT_OFC; |
595 |
if (-rc & float_flag_underflow)
|
596 |
arm_fpe |= BIT_UFC; |
597 |
if (-rc & float_flag_inexact)
|
598 |
arm_fpe |= BIT_IXC; |
599 |
|
600 |
FPSR fpsr = ts->fpa.fpsr; |
601 |
//printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
|
602 |
|
603 |
if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ |
604 |
info.si_signo = SIGFPE; |
605 |
info.si_errno = 0;
|
606 |
|
607 |
/* ordered by priority, least first */
|
608 |
if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
|
609 |
if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
|
610 |
if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
|
611 |
if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
|
612 |
if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
|
613 |
|
614 |
info._sifields._sigfault._addr = env->regs[15];
|
615 |
queue_signal(env, info.si_signo, &info); |
616 |
} else {
|
617 |
env->regs[15] += 4; |
618 |
} |
619 |
|
620 |
/* accumulate unenabled exceptions */
|
621 |
if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
|
622 |
fpsr |= BIT_IXC; |
623 |
if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
|
624 |
fpsr |= BIT_UFC; |
625 |
if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
|
626 |
fpsr |= BIT_OFC; |
627 |
if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
|
628 |
fpsr |= BIT_DZC; |
629 |
if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
|
630 |
fpsr |= BIT_IOC; |
631 |
ts->fpa.fpsr=fpsr; |
632 |
} else { /* everything OK */ |
633 |
/* increment PC */
|
634 |
env->regs[15] += 4; |
635 |
} |
636 |
} |
637 |
break;
|
638 |
case EXCP_SWI:
|
639 |
case EXCP_BKPT:
|
640 |
{ |
641 |
env->eabi = 1;
|
642 |
/* system call */
|
643 |
if (trapnr == EXCP_BKPT) {
|
644 |
if (env->thumb) {
|
645 |
/* FIXME - what to do if get_user() fails? */
|
646 |
get_user_u16(insn, env->regs[15]);
|
647 |
n = insn & 0xff;
|
648 |
env->regs[15] += 2; |
649 |
} else {
|
650 |
/* FIXME - what to do if get_user() fails? */
|
651 |
get_user_u32(insn, env->regs[15]);
|
652 |
n = (insn & 0xf) | ((insn >> 4) & 0xff0); |
653 |
env->regs[15] += 4; |
654 |
} |
655 |
} else {
|
656 |
if (env->thumb) {
|
657 |
/* FIXME - what to do if get_user() fails? */
|
658 |
get_user_u16(insn, env->regs[15] - 2); |
659 |
n = insn & 0xff;
|
660 |
} else {
|
661 |
/* FIXME - what to do if get_user() fails? */
|
662 |
get_user_u32(insn, env->regs[15] - 4); |
663 |
n = insn & 0xffffff;
|
664 |
} |
665 |
} |
666 |
|
667 |
if (n == ARM_NR_cacheflush) {
|
668 |
arm_cache_flush(env->regs[0], env->regs[1]); |
669 |
} else if (n == ARM_NR_semihosting |
670 |
|| n == ARM_NR_thumb_semihosting) { |
671 |
env->regs[0] = do_arm_semihosting (env);
|
672 |
} else if (n == 0 || n >= ARM_SYSCALL_BASE |
673 |
|| (env->thumb && n == ARM_THUMB_SYSCALL)) { |
674 |
/* linux syscall */
|
675 |
if (env->thumb || n == 0) { |
676 |
n = env->regs[7];
|
677 |
} else {
|
678 |
n -= ARM_SYSCALL_BASE; |
679 |
env->eabi = 0;
|
680 |
} |
681 |
if ( n > ARM_NR_BASE) {
|
682 |
switch (n) {
|
683 |
case ARM_NR_cacheflush:
|
684 |
arm_cache_flush(env->regs[0], env->regs[1]); |
685 |
break;
|
686 |
case ARM_NR_set_tls:
|
687 |
cpu_set_tls(env, env->regs[0]);
|
688 |
env->regs[0] = 0; |
689 |
break;
|
690 |
default:
|
691 |
gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
|
692 |
n); |
693 |
env->regs[0] = -TARGET_ENOSYS;
|
694 |
break;
|
695 |
} |
696 |
} else {
|
697 |
env->regs[0] = do_syscall(env,
|
698 |
n, |
699 |
env->regs[0],
|
700 |
env->regs[1],
|
701 |
env->regs[2],
|
702 |
env->regs[3],
|
703 |
env->regs[4],
|
704 |
env->regs[5]);
|
705 |
} |
706 |
} else {
|
707 |
goto error;
|
708 |
} |
709 |
} |
710 |
break;
|
711 |
case EXCP_INTERRUPT:
|
712 |
/* just indicate that signals should be handled asap */
|
713 |
break;
|
714 |
case EXCP_PREFETCH_ABORT:
|
715 |
addr = env->cp15.c6_insn; |
716 |
goto do_segv;
|
717 |
case EXCP_DATA_ABORT:
|
718 |
addr = env->cp15.c6_data; |
719 |
goto do_segv;
|
720 |
do_segv:
|
721 |
{ |
722 |
info.si_signo = SIGSEGV; |
723 |
info.si_errno = 0;
|
724 |
/* XXX: check env->error_code */
|
725 |
info.si_code = TARGET_SEGV_MAPERR; |
726 |
info._sifields._sigfault._addr = addr; |
727 |
queue_signal(env, info.si_signo, &info); |
728 |
} |
729 |
break;
|
730 |
case EXCP_DEBUG:
|
731 |
{ |
732 |
int sig;
|
733 |
|
734 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
735 |
if (sig)
|
736 |
{ |
737 |
info.si_signo = sig; |
738 |
info.si_errno = 0;
|
739 |
info.si_code = TARGET_TRAP_BRKPT; |
740 |
queue_signal(env, info.si_signo, &info); |
741 |
} |
742 |
} |
743 |
break;
|
744 |
case EXCP_KERNEL_TRAP:
|
745 |
if (do_kernel_trap(env))
|
746 |
goto error;
|
747 |
break;
|
748 |
default:
|
749 |
error:
|
750 |
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
|
751 |
trapnr); |
752 |
cpu_dump_state(env, stderr, fprintf, 0);
|
753 |
abort(); |
754 |
} |
755 |
process_pending_signals(env); |
756 |
} |
757 |
} |
758 |
|
759 |
#endif
|
760 |
|
761 |
#ifdef TARGET_SPARC
|
762 |
#define SPARC64_STACK_BIAS 2047 |
763 |
|
764 |
//#define DEBUG_WIN
|
765 |
|
766 |
/* WARNING: dealing with register windows _is_ complicated. More info
|
767 |
can be found at http://www.sics.se/~psm/sparcstack.html */
|
768 |
static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) |
769 |
{ |
770 |
index = (index + cwp * 16) % (16 * env->nwindows); |
771 |
/* wrap handling : if cwp is on the last window, then we use the
|
772 |
registers 'after' the end */
|
773 |
if (index < 8 && env->cwp == env->nwindows - 1) |
774 |
index += 16 * env->nwindows;
|
775 |
return index;
|
776 |
} |
777 |
|
778 |
/* save the register window 'cwp1' */
|
779 |
static inline void save_window_offset(CPUSPARCState *env, int cwp1) |
780 |
{ |
781 |
unsigned int i; |
782 |
abi_ulong sp_ptr; |
783 |
|
784 |
sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
|
785 |
#ifdef TARGET_SPARC64
|
786 |
if (sp_ptr & 3) |
787 |
sp_ptr += SPARC64_STACK_BIAS; |
788 |
#endif
|
789 |
#if defined(DEBUG_WIN)
|
790 |
printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", |
791 |
sp_ptr, cwp1); |
792 |
#endif
|
793 |
for(i = 0; i < 16; i++) { |
794 |
/* FIXME - what to do if put_user() fails? */
|
795 |
put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
|
796 |
sp_ptr += sizeof(abi_ulong);
|
797 |
} |
798 |
} |
799 |
|
800 |
static void save_window(CPUSPARCState *env) |
801 |
{ |
802 |
#ifndef TARGET_SPARC64
|
803 |
unsigned int new_wim; |
804 |
new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & |
805 |
((1LL << env->nwindows) - 1); |
806 |
save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
|
807 |
env->wim = new_wim; |
808 |
#else
|
809 |
save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
|
810 |
env->cansave++; |
811 |
env->canrestore--; |
812 |
#endif
|
813 |
} |
814 |
|
815 |
static void restore_window(CPUSPARCState *env) |
816 |
{ |
817 |
#ifndef TARGET_SPARC64
|
818 |
unsigned int new_wim; |
819 |
#endif
|
820 |
unsigned int i, cwp1; |
821 |
abi_ulong sp_ptr; |
822 |
|
823 |
#ifndef TARGET_SPARC64
|
824 |
new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & |
825 |
((1LL << env->nwindows) - 1); |
826 |
#endif
|
827 |
|
828 |
/* restore the invalid window */
|
829 |
cwp1 = cpu_cwp_inc(env, env->cwp + 1);
|
830 |
sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
|
831 |
#ifdef TARGET_SPARC64
|
832 |
if (sp_ptr & 3) |
833 |
sp_ptr += SPARC64_STACK_BIAS; |
834 |
#endif
|
835 |
#if defined(DEBUG_WIN)
|
836 |
printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", |
837 |
sp_ptr, cwp1); |
838 |
#endif
|
839 |
for(i = 0; i < 16; i++) { |
840 |
/* FIXME - what to do if get_user() fails? */
|
841 |
get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
|
842 |
sp_ptr += sizeof(abi_ulong);
|
843 |
} |
844 |
#ifdef TARGET_SPARC64
|
845 |
env->canrestore++; |
846 |
if (env->cleanwin < env->nwindows - 1) |
847 |
env->cleanwin++; |
848 |
env->cansave--; |
849 |
#else
|
850 |
env->wim = new_wim; |
851 |
#endif
|
852 |
} |
853 |
|
854 |
static void flush_windows(CPUSPARCState *env) |
855 |
{ |
856 |
int offset, cwp1;
|
857 |
|
858 |
offset = 1;
|
859 |
for(;;) {
|
860 |
/* if restore would invoke restore_window(), then we can stop */
|
861 |
cwp1 = cpu_cwp_inc(env, env->cwp + offset); |
862 |
#ifndef TARGET_SPARC64
|
863 |
if (env->wim & (1 << cwp1)) |
864 |
break;
|
865 |
#else
|
866 |
if (env->canrestore == 0) |
867 |
break;
|
868 |
env->cansave++; |
869 |
env->canrestore--; |
870 |
#endif
|
871 |
save_window_offset(env, cwp1); |
872 |
offset++; |
873 |
} |
874 |
cwp1 = cpu_cwp_inc(env, env->cwp + 1);
|
875 |
#ifndef TARGET_SPARC64
|
876 |
/* set wim so that restore will reload the registers */
|
877 |
env->wim = 1 << cwp1;
|
878 |
#endif
|
879 |
#if defined(DEBUG_WIN)
|
880 |
printf("flush_windows: nb=%d\n", offset - 1); |
881 |
#endif
|
882 |
} |
883 |
|
884 |
void cpu_loop (CPUSPARCState *env)
|
885 |
{ |
886 |
int trapnr, ret;
|
887 |
target_siginfo_t info; |
888 |
|
889 |
while (1) { |
890 |
trapnr = cpu_sparc_exec (env); |
891 |
|
892 |
switch (trapnr) {
|
893 |
#ifndef TARGET_SPARC64
|
894 |
case 0x88: |
895 |
case 0x90: |
896 |
#else
|
897 |
case 0x110: |
898 |
case 0x16d: |
899 |
#endif
|
900 |
ret = do_syscall (env, env->gregs[1],
|
901 |
env->regwptr[0], env->regwptr[1], |
902 |
env->regwptr[2], env->regwptr[3], |
903 |
env->regwptr[4], env->regwptr[5]); |
904 |
if ((unsigned int)ret >= (unsigned int)(-515)) { |
905 |
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
906 |
env->xcc |= PSR_CARRY; |
907 |
#else
|
908 |
env->psr |= PSR_CARRY; |
909 |
#endif
|
910 |
ret = -ret; |
911 |
} else {
|
912 |
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
913 |
env->xcc &= ~PSR_CARRY; |
914 |
#else
|
915 |
env->psr &= ~PSR_CARRY; |
916 |
#endif
|
917 |
} |
918 |
env->regwptr[0] = ret;
|
919 |
/* next instruction */
|
920 |
env->pc = env->npc; |
921 |
env->npc = env->npc + 4;
|
922 |
break;
|
923 |
case 0x83: /* flush windows */ |
924 |
#ifdef TARGET_ABI32
|
925 |
case 0x103: |
926 |
#endif
|
927 |
flush_windows(env); |
928 |
/* next instruction */
|
929 |
env->pc = env->npc; |
930 |
env->npc = env->npc + 4;
|
931 |
break;
|
932 |
#ifndef TARGET_SPARC64
|
933 |
case TT_WIN_OVF: /* window overflow */ |
934 |
save_window(env); |
935 |
break;
|
936 |
case TT_WIN_UNF: /* window underflow */ |
937 |
restore_window(env); |
938 |
break;
|
939 |
case TT_TFAULT:
|
940 |
case TT_DFAULT:
|
941 |
{ |
942 |
info.si_signo = SIGSEGV; |
943 |
info.si_errno = 0;
|
944 |
/* XXX: check env->error_code */
|
945 |
info.si_code = TARGET_SEGV_MAPERR; |
946 |
info._sifields._sigfault._addr = env->mmuregs[4];
|
947 |
queue_signal(env, info.si_signo, &info); |
948 |
} |
949 |
break;
|
950 |
#else
|
951 |
case TT_SPILL: /* window overflow */ |
952 |
save_window(env); |
953 |
break;
|
954 |
case TT_FILL: /* window underflow */ |
955 |
restore_window(env); |
956 |
break;
|
957 |
case TT_TFAULT:
|
958 |
case TT_DFAULT:
|
959 |
{ |
960 |
info.si_signo = SIGSEGV; |
961 |
info.si_errno = 0;
|
962 |
/* XXX: check env->error_code */
|
963 |
info.si_code = TARGET_SEGV_MAPERR; |
964 |
if (trapnr == TT_DFAULT)
|
965 |
info._sifields._sigfault._addr = env->dmmuregs[4];
|
966 |
else
|
967 |
info._sifields._sigfault._addr = env->tsptr->tpc; |
968 |
queue_signal(env, info.si_signo, &info); |
969 |
} |
970 |
break;
|
971 |
#ifndef TARGET_ABI32
|
972 |
case 0x16e: |
973 |
flush_windows(env); |
974 |
sparc64_get_context(env); |
975 |
break;
|
976 |
case 0x16f: |
977 |
flush_windows(env); |
978 |
sparc64_set_context(env); |
979 |
break;
|
980 |
#endif
|
981 |
#endif
|
982 |
case EXCP_INTERRUPT:
|
983 |
/* just indicate that signals should be handled asap */
|
984 |
break;
|
985 |
case EXCP_DEBUG:
|
986 |
{ |
987 |
int sig;
|
988 |
|
989 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
990 |
if (sig)
|
991 |
{ |
992 |
info.si_signo = sig; |
993 |
info.si_errno = 0;
|
994 |
info.si_code = TARGET_TRAP_BRKPT; |
995 |
queue_signal(env, info.si_signo, &info); |
996 |
} |
997 |
} |
998 |
break;
|
999 |
default:
|
1000 |
printf ("Unhandled trap: 0x%x\n", trapnr);
|
1001 |
cpu_dump_state(env, stderr, fprintf, 0);
|
1002 |
exit (1);
|
1003 |
} |
1004 |
process_pending_signals (env); |
1005 |
} |
1006 |
} |
1007 |
|
1008 |
#endif
|
1009 |
|
1010 |
#ifdef TARGET_PPC
|
1011 |
static inline uint64_t cpu_ppc_get_tb (CPUState *env) |
1012 |
{ |
1013 |
/* TO FIX */
|
1014 |
return 0; |
1015 |
} |
1016 |
|
1017 |
uint32_t cpu_ppc_load_tbl (CPUState *env) |
1018 |
{ |
1019 |
return cpu_ppc_get_tb(env) & 0xFFFFFFFF; |
1020 |
} |
1021 |
|
1022 |
uint32_t cpu_ppc_load_tbu (CPUState *env) |
1023 |
{ |
1024 |
return cpu_ppc_get_tb(env) >> 32; |
1025 |
} |
1026 |
|
1027 |
uint32_t cpu_ppc_load_atbl (CPUState *env) |
1028 |
{ |
1029 |
return cpu_ppc_get_tb(env) & 0xFFFFFFFF; |
1030 |
} |
1031 |
|
1032 |
uint32_t cpu_ppc_load_atbu (CPUState *env) |
1033 |
{ |
1034 |
return cpu_ppc_get_tb(env) >> 32; |
1035 |
} |
1036 |
|
1037 |
uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
1038 |
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
|
1039 |
|
1040 |
uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
1041 |
{ |
1042 |
return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
1043 |
} |
1044 |
|
1045 |
/* XXX: to be fixed */
|
1046 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
1047 |
{ |
1048 |
return -1; |
1049 |
} |
1050 |
|
1051 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
1052 |
{ |
1053 |
return -1; |
1054 |
} |
1055 |
|
1056 |
#define EXCP_DUMP(env, fmt, args...) \
|
1057 |
do { \
|
1058 |
fprintf(stderr, fmt , ##args); \ |
1059 |
cpu_dump_state(env, stderr, fprintf, 0); \
|
1060 |
qemu_log(fmt, ##args); \ |
1061 |
log_cpu_state(env, 0); \
|
1062 |
} while (0) |
1063 |
|
1064 |
void cpu_loop(CPUPPCState *env)
|
1065 |
{ |
1066 |
target_siginfo_t info; |
1067 |
int trapnr;
|
1068 |
uint32_t ret; |
1069 |
|
1070 |
for(;;) {
|
1071 |
trapnr = cpu_ppc_exec(env); |
1072 |
switch(trapnr) {
|
1073 |
case POWERPC_EXCP_NONE:
|
1074 |
/* Just go on */
|
1075 |
break;
|
1076 |
case POWERPC_EXCP_CRITICAL: /* Critical input */ |
1077 |
cpu_abort(env, "Critical interrupt while in user mode. "
|
1078 |
"Aborting\n");
|
1079 |
break;
|
1080 |
case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
1081 |
cpu_abort(env, "Machine check exception while in user mode. "
|
1082 |
"Aborting\n");
|
1083 |
break;
|
1084 |
case POWERPC_EXCP_DSI: /* Data storage exception */ |
1085 |
EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n", |
1086 |
env->spr[SPR_DAR]); |
1087 |
/* XXX: check this. Seems bugged */
|
1088 |
switch (env->error_code & 0xFF000000) { |
1089 |
case 0x40000000: |
1090 |
info.si_signo = TARGET_SIGSEGV; |
1091 |
info.si_errno = 0;
|
1092 |
info.si_code = TARGET_SEGV_MAPERR; |
1093 |
break;
|
1094 |
case 0x04000000: |
1095 |
info.si_signo = TARGET_SIGILL; |
1096 |
info.si_errno = 0;
|
1097 |
info.si_code = TARGET_ILL_ILLADR; |
1098 |
break;
|
1099 |
case 0x08000000: |
1100 |
info.si_signo = TARGET_SIGSEGV; |
1101 |
info.si_errno = 0;
|
1102 |
info.si_code = TARGET_SEGV_ACCERR; |
1103 |
break;
|
1104 |
default:
|
1105 |
/* Let's send a regular segfault... */
|
1106 |
EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
|
1107 |
env->error_code); |
1108 |
info.si_signo = TARGET_SIGSEGV; |
1109 |
info.si_errno = 0;
|
1110 |
info.si_code = TARGET_SEGV_MAPERR; |
1111 |
break;
|
1112 |
} |
1113 |
info._sifields._sigfault._addr = env->nip; |
1114 |
queue_signal(env, info.si_signo, &info); |
1115 |
break;
|
1116 |
case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
1117 |
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n", |
1118 |
env->spr[SPR_SRR0]); |
1119 |
/* XXX: check this */
|
1120 |
switch (env->error_code & 0xFF000000) { |
1121 |
case 0x40000000: |
1122 |
info.si_signo = TARGET_SIGSEGV; |
1123 |
info.si_errno = 0;
|
1124 |
info.si_code = TARGET_SEGV_MAPERR; |
1125 |
break;
|
1126 |
case 0x10000000: |
1127 |
case 0x08000000: |
1128 |
info.si_signo = TARGET_SIGSEGV; |
1129 |
info.si_errno = 0;
|
1130 |
info.si_code = TARGET_SEGV_ACCERR; |
1131 |
break;
|
1132 |
default:
|
1133 |
/* Let's send a regular segfault... */
|
1134 |
EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
|
1135 |
env->error_code); |
1136 |
info.si_signo = TARGET_SIGSEGV; |
1137 |
info.si_errno = 0;
|
1138 |
info.si_code = TARGET_SEGV_MAPERR; |
1139 |
break;
|
1140 |
} |
1141 |
info._sifields._sigfault._addr = env->nip - 4;
|
1142 |
queue_signal(env, info.si_signo, &info); |
1143 |
break;
|
1144 |
case POWERPC_EXCP_EXTERNAL: /* External input */ |
1145 |
cpu_abort(env, "External interrupt while in user mode. "
|
1146 |
"Aborting\n");
|
1147 |
break;
|
1148 |
case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
1149 |
EXCP_DUMP(env, "Unaligned memory access\n");
|
1150 |
/* XXX: check this */
|
1151 |
info.si_signo = TARGET_SIGBUS; |
1152 |
info.si_errno = 0;
|
1153 |
info.si_code = TARGET_BUS_ADRALN; |
1154 |
info._sifields._sigfault._addr = env->nip - 4;
|
1155 |
queue_signal(env, info.si_signo, &info); |
1156 |
break;
|
1157 |
case POWERPC_EXCP_PROGRAM: /* Program exception */ |
1158 |
/* XXX: check this */
|
1159 |
switch (env->error_code & ~0xF) { |
1160 |
case POWERPC_EXCP_FP:
|
1161 |
EXCP_DUMP(env, "Floating point program exception\n");
|
1162 |
info.si_signo = TARGET_SIGFPE; |
1163 |
info.si_errno = 0;
|
1164 |
switch (env->error_code & 0xF) { |
1165 |
case POWERPC_EXCP_FP_OX:
|
1166 |
info.si_code = TARGET_FPE_FLTOVF; |
1167 |
break;
|
1168 |
case POWERPC_EXCP_FP_UX:
|
1169 |
info.si_code = TARGET_FPE_FLTUND; |
1170 |
break;
|
1171 |
case POWERPC_EXCP_FP_ZX:
|
1172 |
case POWERPC_EXCP_FP_VXZDZ:
|
1173 |
info.si_code = TARGET_FPE_FLTDIV; |
1174 |
break;
|
1175 |
case POWERPC_EXCP_FP_XX:
|
1176 |
info.si_code = TARGET_FPE_FLTRES; |
1177 |
break;
|
1178 |
case POWERPC_EXCP_FP_VXSOFT:
|
1179 |
info.si_code = TARGET_FPE_FLTINV; |
1180 |
break;
|
1181 |
case POWERPC_EXCP_FP_VXSNAN:
|
1182 |
case POWERPC_EXCP_FP_VXISI:
|
1183 |
case POWERPC_EXCP_FP_VXIDI:
|
1184 |
case POWERPC_EXCP_FP_VXIMZ:
|
1185 |
case POWERPC_EXCP_FP_VXVC:
|
1186 |
case POWERPC_EXCP_FP_VXSQRT:
|
1187 |
case POWERPC_EXCP_FP_VXCVI:
|
1188 |
info.si_code = TARGET_FPE_FLTSUB; |
1189 |
break;
|
1190 |
default:
|
1191 |
EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
|
1192 |
env->error_code); |
1193 |
break;
|
1194 |
} |
1195 |
break;
|
1196 |
case POWERPC_EXCP_INVAL:
|
1197 |
EXCP_DUMP(env, "Invalid instruction\n");
|
1198 |
info.si_signo = TARGET_SIGILL; |
1199 |
info.si_errno = 0;
|
1200 |
switch (env->error_code & 0xF) { |
1201 |
case POWERPC_EXCP_INVAL_INVAL:
|
1202 |
info.si_code = TARGET_ILL_ILLOPC; |
1203 |
break;
|
1204 |
case POWERPC_EXCP_INVAL_LSWX:
|
1205 |
info.si_code = TARGET_ILL_ILLOPN; |
1206 |
break;
|
1207 |
case POWERPC_EXCP_INVAL_SPR:
|
1208 |
info.si_code = TARGET_ILL_PRVREG; |
1209 |
break;
|
1210 |
case POWERPC_EXCP_INVAL_FP:
|
1211 |
info.si_code = TARGET_ILL_COPROC; |
1212 |
break;
|
1213 |
default:
|
1214 |
EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
|
1215 |
env->error_code & 0xF);
|
1216 |
info.si_code = TARGET_ILL_ILLADR; |
1217 |
break;
|
1218 |
} |
1219 |
break;
|
1220 |
case POWERPC_EXCP_PRIV:
|
1221 |
EXCP_DUMP(env, "Privilege violation\n");
|
1222 |
info.si_signo = TARGET_SIGILL; |
1223 |
info.si_errno = 0;
|
1224 |
switch (env->error_code & 0xF) { |
1225 |
case POWERPC_EXCP_PRIV_OPC:
|
1226 |
info.si_code = TARGET_ILL_PRVOPC; |
1227 |
break;
|
1228 |
case POWERPC_EXCP_PRIV_REG:
|
1229 |
info.si_code = TARGET_ILL_PRVREG; |
1230 |
break;
|
1231 |
default:
|
1232 |
EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
|
1233 |
env->error_code & 0xF);
|
1234 |
info.si_code = TARGET_ILL_PRVOPC; |
1235 |
break;
|
1236 |
} |
1237 |
break;
|
1238 |
case POWERPC_EXCP_TRAP:
|
1239 |
cpu_abort(env, "Tried to call a TRAP\n");
|
1240 |
break;
|
1241 |
default:
|
1242 |
/* Should not happen ! */
|
1243 |
cpu_abort(env, "Unknown program exception (%02x)\n",
|
1244 |
env->error_code); |
1245 |
break;
|
1246 |
} |
1247 |
info._sifields._sigfault._addr = env->nip - 4;
|
1248 |
queue_signal(env, info.si_signo, &info); |
1249 |
break;
|
1250 |
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
1251 |
EXCP_DUMP(env, "No floating point allowed\n");
|
1252 |
info.si_signo = TARGET_SIGILL; |
1253 |
info.si_errno = 0;
|
1254 |
info.si_code = TARGET_ILL_COPROC; |
1255 |
info._sifields._sigfault._addr = env->nip - 4;
|
1256 |
queue_signal(env, info.si_signo, &info); |
1257 |
break;
|
1258 |
case POWERPC_EXCP_SYSCALL: /* System call exception */ |
1259 |
cpu_abort(env, "Syscall exception while in user mode. "
|
1260 |
"Aborting\n");
|
1261 |
break;
|
1262 |
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
1263 |
EXCP_DUMP(env, "No APU instruction allowed\n");
|
1264 |
info.si_signo = TARGET_SIGILL; |
1265 |
info.si_errno = 0;
|
1266 |
info.si_code = TARGET_ILL_COPROC; |
1267 |
info._sifields._sigfault._addr = env->nip - 4;
|
1268 |
queue_signal(env, info.si_signo, &info); |
1269 |
break;
|
1270 |
case POWERPC_EXCP_DECR: /* Decrementer exception */ |
1271 |
cpu_abort(env, "Decrementer interrupt while in user mode. "
|
1272 |
"Aborting\n");
|
1273 |
break;
|
1274 |
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
1275 |
cpu_abort(env, "Fix interval timer interrupt while in user mode. "
|
1276 |
"Aborting\n");
|
1277 |
break;
|
1278 |
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
1279 |
cpu_abort(env, "Watchdog timer interrupt while in user mode. "
|
1280 |
"Aborting\n");
|
1281 |
break;
|
1282 |
case POWERPC_EXCP_DTLB: /* Data TLB error */ |
1283 |
cpu_abort(env, "Data TLB exception while in user mode. "
|
1284 |
"Aborting\n");
|
1285 |
break;
|
1286 |
case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
1287 |
cpu_abort(env, "Instruction TLB exception while in user mode. "
|
1288 |
"Aborting\n");
|
1289 |
break;
|
1290 |
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ |
1291 |
EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
|
1292 |
info.si_signo = TARGET_SIGILL; |
1293 |
info.si_errno = 0;
|
1294 |
info.si_code = TARGET_ILL_COPROC; |
1295 |
info._sifields._sigfault._addr = env->nip - 4;
|
1296 |
queue_signal(env, info.si_signo, &info); |
1297 |
break;
|
1298 |
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ |
1299 |
cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
|
1300 |
break;
|
1301 |
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ |
1302 |
cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
|
1303 |
break;
|
1304 |
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ |
1305 |
cpu_abort(env, "Performance monitor exception not handled\n");
|
1306 |
break;
|
1307 |
case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
1308 |
cpu_abort(env, "Doorbell interrupt while in user mode. "
|
1309 |
"Aborting\n");
|
1310 |
break;
|
1311 |
case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
1312 |
cpu_abort(env, "Doorbell critical interrupt while in user mode. "
|
1313 |
"Aborting\n");
|
1314 |
break;
|
1315 |
case POWERPC_EXCP_RESET: /* System reset exception */ |
1316 |
cpu_abort(env, "Reset interrupt while in user mode. "
|
1317 |
"Aborting\n");
|
1318 |
break;
|
1319 |
case POWERPC_EXCP_DSEG: /* Data segment exception */ |
1320 |
cpu_abort(env, "Data segment exception while in user mode. "
|
1321 |
"Aborting\n");
|
1322 |
break;
|
1323 |
case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
1324 |
cpu_abort(env, "Instruction segment exception "
|
1325 |
"while in user mode. Aborting\n");
|
1326 |
break;
|
1327 |
/* PowerPC 64 with hypervisor mode support */
|
1328 |
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
1329 |
cpu_abort(env, "Hypervisor decrementer interrupt "
|
1330 |
"while in user mode. Aborting\n");
|
1331 |
break;
|
1332 |
case POWERPC_EXCP_TRACE: /* Trace exception */ |
1333 |
/* Nothing to do:
|
1334 |
* we use this exception to emulate step-by-step execution mode.
|
1335 |
*/
|
1336 |
break;
|
1337 |
/* PowerPC 64 with hypervisor mode support */
|
1338 |
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
1339 |
cpu_abort(env, "Hypervisor data storage exception "
|
1340 |
"while in user mode. Aborting\n");
|
1341 |
break;
|
1342 |
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ |
1343 |
cpu_abort(env, "Hypervisor instruction storage exception "
|
1344 |
"while in user mode. Aborting\n");
|
1345 |
break;
|
1346 |
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
1347 |
cpu_abort(env, "Hypervisor data segment exception "
|
1348 |
"while in user mode. Aborting\n");
|
1349 |
break;
|
1350 |
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ |
1351 |
cpu_abort(env, "Hypervisor instruction segment exception "
|
1352 |
"while in user mode. Aborting\n");
|
1353 |
break;
|
1354 |
case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1355 |
EXCP_DUMP(env, "No Altivec instructions allowed\n");
|
1356 |
info.si_signo = TARGET_SIGILL; |
1357 |
info.si_errno = 0;
|
1358 |
info.si_code = TARGET_ILL_COPROC; |
1359 |
info._sifields._sigfault._addr = env->nip - 4;
|
1360 |
queue_signal(env, info.si_signo, &info); |
1361 |
break;
|
1362 |
case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ |
1363 |
cpu_abort(env, "Programable interval timer interrupt "
|
1364 |
"while in user mode. Aborting\n");
|
1365 |
break;
|
1366 |
case POWERPC_EXCP_IO: /* IO error exception */ |
1367 |
cpu_abort(env, "IO error exception while in user mode. "
|
1368 |
"Aborting\n");
|
1369 |
break;
|
1370 |
case POWERPC_EXCP_RUNM: /* Run mode exception */ |
1371 |
cpu_abort(env, "Run mode exception while in user mode. "
|
1372 |
"Aborting\n");
|
1373 |
break;
|
1374 |
case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
1375 |
cpu_abort(env, "Emulation trap exception not handled\n");
|
1376 |
break;
|
1377 |
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
1378 |
cpu_abort(env, "Instruction fetch TLB exception "
|
1379 |
"while in user-mode. Aborting");
|
1380 |
break;
|
1381 |
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
1382 |
cpu_abort(env, "Data load TLB exception while in user-mode. "
|
1383 |
"Aborting");
|
1384 |
break;
|
1385 |
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
1386 |
cpu_abort(env, "Data store TLB exception while in user-mode. "
|
1387 |
"Aborting");
|
1388 |
break;
|
1389 |
case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
1390 |
cpu_abort(env, "Floating-point assist exception not handled\n");
|
1391 |
break;
|
1392 |
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
1393 |
cpu_abort(env, "Instruction address breakpoint exception "
|
1394 |
"not handled\n");
|
1395 |
break;
|
1396 |
case POWERPC_EXCP_SMI: /* System management interrupt */ |
1397 |
cpu_abort(env, "System management interrupt while in user mode. "
|
1398 |
"Aborting\n");
|
1399 |
break;
|
1400 |
case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
1401 |
cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
|
1402 |
"Aborting\n");
|
1403 |
break;
|
1404 |
case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ |
1405 |
cpu_abort(env, "Performance monitor exception not handled\n");
|
1406 |
break;
|
1407 |
case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
1408 |
cpu_abort(env, "Vector assist exception not handled\n");
|
1409 |
break;
|
1410 |
case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
1411 |
cpu_abort(env, "Soft patch exception not handled\n");
|
1412 |
break;
|
1413 |
case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
1414 |
cpu_abort(env, "Maintenance exception while in user mode. "
|
1415 |
"Aborting\n");
|
1416 |
break;
|
1417 |
case POWERPC_EXCP_STOP: /* stop translation */ |
1418 |
/* We did invalidate the instruction cache. Go on */
|
1419 |
break;
|
1420 |
case POWERPC_EXCP_BRANCH: /* branch instruction: */ |
1421 |
/* We just stopped because of a branch. Go on */
|
1422 |
break;
|
1423 |
case POWERPC_EXCP_SYSCALL_USER:
|
1424 |
/* system call in user-mode emulation */
|
1425 |
/* WARNING:
|
1426 |
* PPC ABI uses overflow flag in cr0 to signal an error
|
1427 |
* in syscalls.
|
1428 |
*/
|
1429 |
#if 0
|
1430 |
printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
|
1431 |
env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
|
1432 |
#endif
|
1433 |
env->crf[0] &= ~0x1; |
1434 |
ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], |
1435 |
env->gpr[5], env->gpr[6], env->gpr[7], |
1436 |
env->gpr[8]);
|
1437 |
if (ret > (uint32_t)(-515)) { |
1438 |
env->crf[0] |= 0x1; |
1439 |
ret = -ret; |
1440 |
} |
1441 |
env->gpr[3] = ret;
|
1442 |
#if 0
|
1443 |
printf("syscall returned 0x%08x (%d)\n", ret, ret);
|
1444 |
#endif
|
1445 |
break;
|
1446 |
case EXCP_DEBUG:
|
1447 |
{ |
1448 |
int sig;
|
1449 |
|
1450 |
sig = gdb_handlesig(env, TARGET_SIGTRAP); |
1451 |
if (sig) {
|
1452 |
info.si_signo = sig; |
1453 |
info.si_errno = 0;
|
1454 |
info.si_code = TARGET_TRAP_BRKPT; |
1455 |
queue_signal(env, info.si_signo, &info); |
1456 |
} |
1457 |
} |
1458 |
break;
|
1459 |
case EXCP_INTERRUPT:
|
1460 |
/* just indicate that signals should be handled asap */
|
1461 |
break;
|
1462 |
default:
|
1463 |
cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
|
1464 |
break;
|
1465 |
} |
1466 |
process_pending_signals(env); |
1467 |
} |
1468 |
} |
1469 |
#endif
|
1470 |
|
1471 |
#ifdef TARGET_MIPS
|
1472 |
|
1473 |
#define MIPS_SYS(name, args) args,
|
1474 |
|
1475 |
static const uint8_t mips_syscall_args[] = { |
1476 |
MIPS_SYS(sys_syscall , 0) /* 4000 */ |
1477 |
MIPS_SYS(sys_exit , 1)
|
1478 |
MIPS_SYS(sys_fork , 0)
|
1479 |
MIPS_SYS(sys_read , 3)
|
1480 |
MIPS_SYS(sys_write , 3)
|
1481 |
MIPS_SYS(sys_open , 3) /* 4005 */ |
1482 |
MIPS_SYS(sys_close , 1)
|
1483 |
MIPS_SYS(sys_waitpid , 3)
|
1484 |
MIPS_SYS(sys_creat , 2)
|
1485 |
MIPS_SYS(sys_link , 2)
|
1486 |
MIPS_SYS(sys_unlink , 1) /* 4010 */ |
1487 |
MIPS_SYS(sys_execve , 0)
|
1488 |
MIPS_SYS(sys_chdir , 1)
|
1489 |
MIPS_SYS(sys_time , 1)
|
1490 |
MIPS_SYS(sys_mknod , 3)
|
1491 |
MIPS_SYS(sys_chmod , 2) /* 4015 */ |
1492 |
MIPS_SYS(sys_lchown , 3)
|
1493 |
MIPS_SYS(sys_ni_syscall , 0)
|
1494 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ |
1495 |
MIPS_SYS(sys_lseek , 3)
|
1496 |
MIPS_SYS(sys_getpid , 0) /* 4020 */ |
1497 |
MIPS_SYS(sys_mount , 5)
|
1498 |
MIPS_SYS(sys_oldumount , 1)
|
1499 |
MIPS_SYS(sys_setuid , 1)
|
1500 |
MIPS_SYS(sys_getuid , 0)
|
1501 |
MIPS_SYS(sys_stime , 1) /* 4025 */ |
1502 |
MIPS_SYS(sys_ptrace , 4)
|
1503 |
MIPS_SYS(sys_alarm , 1)
|
1504 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ |
1505 |
MIPS_SYS(sys_pause , 0)
|
1506 |
MIPS_SYS(sys_utime , 2) /* 4030 */ |
1507 |
MIPS_SYS(sys_ni_syscall , 0)
|
1508 |
MIPS_SYS(sys_ni_syscall , 0)
|
1509 |
MIPS_SYS(sys_access , 2)
|
1510 |
MIPS_SYS(sys_nice , 1)
|
1511 |
MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ |
1512 |
MIPS_SYS(sys_sync , 0)
|
1513 |
MIPS_SYS(sys_kill , 2)
|
1514 |
MIPS_SYS(sys_rename , 2)
|
1515 |
MIPS_SYS(sys_mkdir , 2)
|
1516 |
MIPS_SYS(sys_rmdir , 1) /* 4040 */ |
1517 |
MIPS_SYS(sys_dup , 1)
|
1518 |
MIPS_SYS(sys_pipe , 0)
|
1519 |
MIPS_SYS(sys_times , 1)
|
1520 |
MIPS_SYS(sys_ni_syscall , 0)
|
1521 |
MIPS_SYS(sys_brk , 1) /* 4045 */ |
1522 |
MIPS_SYS(sys_setgid , 1)
|
1523 |
MIPS_SYS(sys_getgid , 0)
|
1524 |
MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ |
1525 |
MIPS_SYS(sys_geteuid , 0)
|
1526 |
MIPS_SYS(sys_getegid , 0) /* 4050 */ |
1527 |
MIPS_SYS(sys_acct , 0)
|
1528 |
MIPS_SYS(sys_umount , 2)
|
1529 |
MIPS_SYS(sys_ni_syscall , 0)
|
1530 |
MIPS_SYS(sys_ioctl , 3)
|
1531 |
MIPS_SYS(sys_fcntl , 3) /* 4055 */ |
1532 |
MIPS_SYS(sys_ni_syscall , 2)
|
1533 |
MIPS_SYS(sys_setpgid , 2)
|
1534 |
MIPS_SYS(sys_ni_syscall , 0)
|
1535 |
MIPS_SYS(sys_olduname , 1)
|
1536 |
MIPS_SYS(sys_umask , 1) /* 4060 */ |
1537 |
MIPS_SYS(sys_chroot , 1)
|
1538 |
MIPS_SYS(sys_ustat , 2)
|
1539 |
MIPS_SYS(sys_dup2 , 2)
|
1540 |
MIPS_SYS(sys_getppid , 0)
|
1541 |
MIPS_SYS(sys_getpgrp , 0) /* 4065 */ |
1542 |
MIPS_SYS(sys_setsid , 0)
|
1543 |
MIPS_SYS(sys_sigaction , 3)
|
1544 |
MIPS_SYS(sys_sgetmask , 0)
|
1545 |
MIPS_SYS(sys_ssetmask , 1)
|
1546 |
MIPS_SYS(sys_setreuid , 2) /* 4070 */ |
1547 |
MIPS_SYS(sys_setregid , 2)
|
1548 |
MIPS_SYS(sys_sigsuspend , 0)
|
1549 |
MIPS_SYS(sys_sigpending , 1)
|
1550 |
MIPS_SYS(sys_sethostname , 2)
|
1551 |
MIPS_SYS(sys_setrlimit , 2) /* 4075 */ |
1552 |
MIPS_SYS(sys_getrlimit , 2)
|
1553 |
MIPS_SYS(sys_getrusage , 2)
|
1554 |
MIPS_SYS(sys_gettimeofday, 2)
|
1555 |
MIPS_SYS(sys_settimeofday, 2)
|
1556 |
MIPS_SYS(sys_getgroups , 2) /* 4080 */ |
1557 |
MIPS_SYS(sys_setgroups , 2)
|
1558 |
MIPS_SYS(sys_ni_syscall , 0) /* old_select */ |
1559 |
MIPS_SYS(sys_symlink , 2)
|
1560 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ |
1561 |
MIPS_SYS(sys_readlink , 3) /* 4085 */ |
1562 |
MIPS_SYS(sys_uselib , 1)
|
1563 |
MIPS_SYS(sys_swapon , 2)
|
1564 |
MIPS_SYS(sys_reboot , 3)
|
1565 |
MIPS_SYS(old_readdir , 3)
|
1566 |
MIPS_SYS(old_mmap , 6) /* 4090 */ |
1567 |
MIPS_SYS(sys_munmap , 2)
|
1568 |
MIPS_SYS(sys_truncate , 2)
|
1569 |
MIPS_SYS(sys_ftruncate , 2)
|
1570 |
MIPS_SYS(sys_fchmod , 2)
|
1571 |
MIPS_SYS(sys_fchown , 3) /* 4095 */ |
1572 |
MIPS_SYS(sys_getpriority , 2)
|
1573 |
MIPS_SYS(sys_setpriority , 3)
|
1574 |
MIPS_SYS(sys_ni_syscall , 0)
|
1575 |
MIPS_SYS(sys_statfs , 2)
|
1576 |
MIPS_SYS(sys_fstatfs , 2) /* 4100 */ |
1577 |
MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ |
1578 |
MIPS_SYS(sys_socketcall , 2)
|
1579 |
MIPS_SYS(sys_syslog , 3)
|
1580 |
MIPS_SYS(sys_setitimer , 3)
|
1581 |
MIPS_SYS(sys_getitimer , 2) /* 4105 */ |
1582 |
MIPS_SYS(sys_newstat , 2)
|
1583 |
MIPS_SYS(sys_newlstat , 2)
|
1584 |
MIPS_SYS(sys_newfstat , 2)
|
1585 |
MIPS_SYS(sys_uname , 1)
|
1586 |
MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ |
1587 |
MIPS_SYS(sys_vhangup , 0)
|
1588 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ |
1589 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ |
1590 |
MIPS_SYS(sys_wait4 , 4)
|
1591 |
MIPS_SYS(sys_swapoff , 1) /* 4115 */ |
1592 |
MIPS_SYS(sys_sysinfo , 1)
|
1593 |
MIPS_SYS(sys_ipc , 6)
|
1594 |
MIPS_SYS(sys_fsync , 1)
|
1595 |
MIPS_SYS(sys_sigreturn , 0)
|
1596 |
MIPS_SYS(sys_clone , 0) /* 4120 */ |
1597 |
MIPS_SYS(sys_setdomainname, 2)
|
1598 |
MIPS_SYS(sys_newuname , 1)
|
1599 |
MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ |
1600 |
MIPS_SYS(sys_adjtimex , 1)
|
1601 |
MIPS_SYS(sys_mprotect , 3) /* 4125 */ |
1602 |
MIPS_SYS(sys_sigprocmask , 3)
|
1603 |
MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ |
1604 |
MIPS_SYS(sys_init_module , 5)
|
1605 |
MIPS_SYS(sys_delete_module, 1)
|
1606 |
MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ |
1607 |
MIPS_SYS(sys_quotactl , 0)
|
1608 |
MIPS_SYS(sys_getpgid , 1)
|
1609 |
MIPS_SYS(sys_fchdir , 1)
|
1610 |
MIPS_SYS(sys_bdflush , 2)
|
1611 |
MIPS_SYS(sys_sysfs , 3) /* 4135 */ |
1612 |
MIPS_SYS(sys_personality , 1)
|
1613 |
MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ |
1614 |
MIPS_SYS(sys_setfsuid , 1)
|
1615 |
MIPS_SYS(sys_setfsgid , 1)
|
1616 |
MIPS_SYS(sys_llseek , 5) /* 4140 */ |
1617 |
MIPS_SYS(sys_getdents , 3)
|
1618 |
MIPS_SYS(sys_select , 5)
|
1619 |
MIPS_SYS(sys_flock , 2)
|
1620 |
MIPS_SYS(sys_msync , 3)
|
1621 |
MIPS_SYS(sys_readv , 3) /* 4145 */ |
1622 |
MIPS_SYS(sys_writev , 3)
|
1623 |
MIPS_SYS(sys_cacheflush , 3)
|
1624 |
MIPS_SYS(sys_cachectl , 3)
|
1625 |
MIPS_SYS(sys_sysmips , 4)
|
1626 |
MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ |
1627 |
MIPS_SYS(sys_getsid , 1)
|
1628 |
MIPS_SYS(sys_fdatasync , 0)
|
1629 |
MIPS_SYS(sys_sysctl , 1)
|
1630 |
MIPS_SYS(sys_mlock , 2)
|
1631 |
MIPS_SYS(sys_munlock , 2) /* 4155 */ |
1632 |
MIPS_SYS(sys_mlockall , 1)
|
1633 |
MIPS_SYS(sys_munlockall , 0)
|
1634 |
MIPS_SYS(sys_sched_setparam, 2)
|
1635 |
MIPS_SYS(sys_sched_getparam, 2)
|
1636 |
MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ |
1637 |
MIPS_SYS(sys_sched_getscheduler, 1)
|
1638 |
MIPS_SYS(sys_sched_yield , 0)
|
1639 |
MIPS_SYS(sys_sched_get_priority_max, 1)
|
1640 |
MIPS_SYS(sys_sched_get_priority_min, 1)
|
1641 |
MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ |
1642 |
MIPS_SYS(sys_nanosleep, 2)
|
1643 |
MIPS_SYS(sys_mremap , 4)
|
1644 |
MIPS_SYS(sys_accept , 3)
|
1645 |
MIPS_SYS(sys_bind , 3)
|
1646 |
MIPS_SYS(sys_connect , 3) /* 4170 */ |
1647 |
MIPS_SYS(sys_getpeername , 3)
|
1648 |
MIPS_SYS(sys_getsockname , 3)
|
1649 |
MIPS_SYS(sys_getsockopt , 5)
|
1650 |
MIPS_SYS(sys_listen , 2)
|
1651 |
MIPS_SYS(sys_recv , 4) /* 4175 */ |
1652 |
MIPS_SYS(sys_recvfrom , 6)
|
1653 |
MIPS_SYS(sys_recvmsg , 3)
|
1654 |
MIPS_SYS(sys_send , 4)
|
1655 |
MIPS_SYS(sys_sendmsg , 3)
|
1656 |
MIPS_SYS(sys_sendto , 6) /* 4180 */ |
1657 |
MIPS_SYS(sys_setsockopt , 5)
|
1658 |
MIPS_SYS(sys_shutdown , 2)
|
1659 |
MIPS_SYS(sys_socket , 3)
|
1660 |
MIPS_SYS(sys_socketpair , 4)
|
1661 |
MIPS_SYS(sys_setresuid , 3) /* 4185 */ |
1662 |
MIPS_SYS(sys_getresuid , 3)
|
1663 |
MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ |
1664 |
MIPS_SYS(sys_poll , 3)
|
1665 |
MIPS_SYS(sys_nfsservctl , 3)
|
1666 |
MIPS_SYS(sys_setresgid , 3) /* 4190 */ |
1667 |
MIPS_SYS(sys_getresgid , 3)
|
1668 |
MIPS_SYS(sys_prctl , 5)
|
1669 |
MIPS_SYS(sys_rt_sigreturn, 0)
|
1670 |
MIPS_SYS(sys_rt_sigaction, 4)
|
1671 |
MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ |
1672 |
MIPS_SYS(sys_rt_sigpending, 2)
|
1673 |
MIPS_SYS(sys_rt_sigtimedwait, 4)
|
1674 |
MIPS_SYS(sys_rt_sigqueueinfo, 3)
|
1675 |
MIPS_SYS(sys_rt_sigsuspend, 0)
|
1676 |
MIPS_SYS(sys_pread64 , 6) /* 4200 */ |
1677 |
MIPS_SYS(sys_pwrite64 , 6)
|
1678 |
MIPS_SYS(sys_chown , 3)
|
1679 |
MIPS_SYS(sys_getcwd , 2)
|
1680 |
MIPS_SYS(sys_capget , 2)
|
1681 |
MIPS_SYS(sys_capset , 2) /* 4205 */ |
1682 |
MIPS_SYS(sys_sigaltstack , 0)
|
1683 |
MIPS_SYS(sys_sendfile , 4)
|
1684 |
MIPS_SYS(sys_ni_syscall , 0)
|
1685 |
MIPS_SYS(sys_ni_syscall , 0)
|
1686 |
MIPS_SYS(sys_mmap2 , 6) /* 4210 */ |
1687 |
MIPS_SYS(sys_truncate64 , 4)
|
1688 |
MIPS_SYS(sys_ftruncate64 , 4)
|
1689 |
MIPS_SYS(sys_stat64 , 2)
|
1690 |
MIPS_SYS(sys_lstat64 , 2)
|
1691 |
MIPS_SYS(sys_fstat64 , 2) /* 4215 */ |
1692 |
MIPS_SYS(sys_pivot_root , 2)
|
1693 |
MIPS_SYS(sys_mincore , 3)
|
1694 |
MIPS_SYS(sys_madvise , 3)
|
1695 |
MIPS_SYS(sys_getdents64 , 3)
|
1696 |
MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ |
1697 |
MIPS_SYS(sys_ni_syscall , 0)
|
1698 |
MIPS_SYS(sys_gettid , 0)
|
1699 |
MIPS_SYS(sys_readahead , 5)
|
1700 |
MIPS_SYS(sys_setxattr , 5)
|
1701 |
MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ |
1702 |
MIPS_SYS(sys_fsetxattr , 5)
|
1703 |
MIPS_SYS(sys_getxattr , 4)
|
1704 |
MIPS_SYS(sys_lgetxattr , 4)
|
1705 |
MIPS_SYS(sys_fgetxattr , 4)
|
1706 |
MIPS_SYS(sys_listxattr , 3) /* 4230 */ |
1707 |
MIPS_SYS(sys_llistxattr , 3)
|
1708 |
MIPS_SYS(sys_flistxattr , 3)
|
1709 |
MIPS_SYS(sys_removexattr , 2)
|
1710 |
MIPS_SYS(sys_lremovexattr, 2)
|
1711 |
MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ |
1712 |
MIPS_SYS(sys_tkill , 2)
|
1713 |
MIPS_SYS(sys_sendfile64 , 5)
|
1714 |
MIPS_SYS(sys_futex , 2)
|
1715 |
MIPS_SYS(sys_sched_setaffinity, 3)
|
1716 |
MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ |
1717 |
MIPS_SYS(sys_io_setup , 2)
|
1718 |
MIPS_SYS(sys_io_destroy , 1)
|
1719 |
MIPS_SYS(sys_io_getevents, 5)
|
1720 |
MIPS_SYS(sys_io_submit , 3)
|
1721 |
MIPS_SYS(sys_io_cancel , 3) /* 4245 */ |
1722 |
MIPS_SYS(sys_exit_group , 1)
|
1723 |
MIPS_SYS(sys_lookup_dcookie, 3)
|
1724 |
MIPS_SYS(sys_epoll_create, 1)
|
1725 |
MIPS_SYS(sys_epoll_ctl , 4)
|
1726 |
MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ |
1727 |
MIPS_SYS(sys_remap_file_pages, 5)
|
1728 |
MIPS_SYS(sys_set_tid_address, 1)
|
1729 |
MIPS_SYS(sys_restart_syscall, 0)
|
1730 |
MIPS_SYS(sys_fadvise64_64, 7)
|
1731 |
MIPS_SYS(sys_statfs64 , 3) /* 4255 */ |
1732 |
MIPS_SYS(sys_fstatfs64 , 2)
|
1733 |
MIPS_SYS(sys_timer_create, 3)
|
1734 |
MIPS_SYS(sys_timer_settime, 4)
|
1735 |
MIPS_SYS(sys_timer_gettime, 2)
|
1736 |
MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ |
1737 |
MIPS_SYS(sys_timer_delete, 1)
|
1738 |
MIPS_SYS(sys_clock_settime, 2)
|
1739 |
MIPS_SYS(sys_clock_gettime, 2)
|
1740 |
MIPS_SYS(sys_clock_getres, 2)
|
1741 |
MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ |
1742 |
MIPS_SYS(sys_tgkill , 3)
|
1743 |
MIPS_SYS(sys_utimes , 2)
|
1744 |
MIPS_SYS(sys_mbind , 4)
|
1745 |
MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ |
1746 |
MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ |
1747 |
MIPS_SYS(sys_mq_open , 4)
|
1748 |
MIPS_SYS(sys_mq_unlink , 1)
|
1749 |
MIPS_SYS(sys_mq_timedsend, 5)
|
1750 |
MIPS_SYS(sys_mq_timedreceive, 5)
|
1751 |
MIPS_SYS(sys_mq_notify , 2) /* 4275 */ |
1752 |
MIPS_SYS(sys_mq_getsetattr, 3)
|
1753 |
MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ |
1754 |
MIPS_SYS(sys_waitid , 4)
|
1755 |
MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ |
1756 |
MIPS_SYS(sys_add_key , 5)
|
1757 |
MIPS_SYS(sys_request_key, 4)
|
1758 |
MIPS_SYS(sys_keyctl , 5)
|
1759 |
MIPS_SYS(sys_set_thread_area, 1)
|
1760 |
MIPS_SYS(sys_inotify_init, 0)
|
1761 |
MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ |
1762 |
MIPS_SYS(sys_inotify_rm_watch, 2)
|
1763 |
MIPS_SYS(sys_migrate_pages, 4)
|
1764 |
MIPS_SYS(sys_openat, 4)
|
1765 |
MIPS_SYS(sys_mkdirat, 3)
|
1766 |
MIPS_SYS(sys_mknodat, 4) /* 4290 */ |
1767 |
MIPS_SYS(sys_fchownat, 5)
|
1768 |
MIPS_SYS(sys_futimesat, 3)
|
1769 |
MIPS_SYS(sys_fstatat64, 4)
|
1770 |
MIPS_SYS(sys_unlinkat, 3)
|
1771 |
MIPS_SYS(sys_renameat, 4) /* 4295 */ |
1772 |
MIPS_SYS(sys_linkat, 5)
|
1773 |
MIPS_SYS(sys_symlinkat, 3)
|
1774 |
MIPS_SYS(sys_readlinkat, 4)
|
1775 |
MIPS_SYS(sys_fchmodat, 3)
|
1776 |
MIPS_SYS(sys_faccessat, 3) /* 4300 */ |
1777 |
MIPS_SYS(sys_pselect6, 6)
|
1778 |
MIPS_SYS(sys_ppoll, 5)
|
1779 |
MIPS_SYS(sys_unshare, 1)
|
1780 |
MIPS_SYS(sys_splice, 4)
|
1781 |
MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ |
1782 |
MIPS_SYS(sys_tee, 4)
|
1783 |
MIPS_SYS(sys_vmsplice, 4)
|
1784 |
MIPS_SYS(sys_move_pages, 6)
|
1785 |
MIPS_SYS(sys_set_robust_list, 2)
|
1786 |
MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ |
1787 |
MIPS_SYS(sys_kexec_load, 4)
|
1788 |
MIPS_SYS(sys_getcpu, 3)
|
1789 |
MIPS_SYS(sys_epoll_pwait, 6)
|
1790 |
MIPS_SYS(sys_ioprio_set, 3)
|
1791 |
MIPS_SYS(sys_ioprio_get, 2)
|
1792 |
}; |
1793 |
|
1794 |
#undef MIPS_SYS
|
1795 |
|
1796 |
void cpu_loop(CPUMIPSState *env)
|
1797 |
{ |
1798 |
target_siginfo_t info; |
1799 |
int trapnr, ret;
|
1800 |
unsigned int syscall_num; |
1801 |
|
1802 |
for(;;) {
|
1803 |
trapnr = cpu_mips_exec(env); |
1804 |
switch(trapnr) {
|
1805 |
case EXCP_SYSCALL:
|
1806 |
syscall_num = env->active_tc.gpr[2] - 4000; |
1807 |
env->active_tc.PC += 4;
|
1808 |
if (syscall_num >= sizeof(mips_syscall_args)) { |
1809 |
ret = -ENOSYS; |
1810 |
} else {
|
1811 |
int nb_args;
|
1812 |
abi_ulong sp_reg; |
1813 |
abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; |
1814 |
|
1815 |
nb_args = mips_syscall_args[syscall_num]; |
1816 |
sp_reg = env->active_tc.gpr[29];
|
1817 |
switch (nb_args) {
|
1818 |
/* these arguments are taken from the stack */
|
1819 |
/* FIXME - what to do if get_user() fails? */
|
1820 |
case 8: get_user_ual(arg8, sp_reg + 28); |
1821 |
case 7: get_user_ual(arg7, sp_reg + 24); |
1822 |
case 6: get_user_ual(arg6, sp_reg + 20); |
1823 |
case 5: get_user_ual(arg5, sp_reg + 16); |
1824 |
default:
|
1825 |
break;
|
1826 |
} |
1827 |
ret = do_syscall(env, env->active_tc.gpr[2],
|
1828 |
env->active_tc.gpr[4],
|
1829 |
env->active_tc.gpr[5],
|
1830 |
env->active_tc.gpr[6],
|
1831 |
env->active_tc.gpr[7],
|
1832 |
arg5, arg6/*, arg7, arg8*/);
|
1833 |
} |
1834 |
if ((unsigned int)ret >= (unsigned int)(-1133)) { |
1835 |
env->active_tc.gpr[7] = 1; /* error flag */ |
1836 |
ret = -ret; |
1837 |
} else {
|
1838 |
env->active_tc.gpr[7] = 0; /* error flag */ |
1839 |
} |
1840 |
env->active_tc.gpr[2] = ret;
|
1841 |
break;
|
1842 |
case EXCP_TLBL:
|
1843 |
case EXCP_TLBS:
|
1844 |
case EXCP_CpU:
|
1845 |
case EXCP_RI:
|
1846 |
info.si_signo = TARGET_SIGILL; |
1847 |
info.si_errno = 0;
|
1848 |
info.si_code = 0;
|
1849 |
queue_signal(env, info.si_signo, &info); |
1850 |
break;
|
1851 |
case EXCP_INTERRUPT:
|
1852 |
/* just indicate that signals should be handled asap */
|
1853 |
break;
|
1854 |
case EXCP_DEBUG:
|
1855 |
{ |
1856 |
int sig;
|
1857 |
|
1858 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
1859 |
if (sig)
|
1860 |
{ |
1861 |
info.si_signo = sig; |
1862 |
info.si_errno = 0;
|
1863 |
info.si_code = TARGET_TRAP_BRKPT; |
1864 |
queue_signal(env, info.si_signo, &info); |
1865 |
} |
1866 |
} |
1867 |
break;
|
1868 |
default:
|
1869 |
// error:
|
1870 |
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
|
1871 |
trapnr); |
1872 |
cpu_dump_state(env, stderr, fprintf, 0);
|
1873 |
abort(); |
1874 |
} |
1875 |
process_pending_signals(env); |
1876 |
} |
1877 |
} |
1878 |
#endif
|
1879 |
|
1880 |
#ifdef TARGET_SH4
|
1881 |
void cpu_loop (CPUState *env)
|
1882 |
{ |
1883 |
int trapnr, ret;
|
1884 |
target_siginfo_t info; |
1885 |
|
1886 |
while (1) { |
1887 |
trapnr = cpu_sh4_exec (env); |
1888 |
|
1889 |
switch (trapnr) {
|
1890 |
case 0x160: |
1891 |
env->pc += 2;
|
1892 |
ret = do_syscall(env, |
1893 |
env->gregs[3],
|
1894 |
env->gregs[4],
|
1895 |
env->gregs[5],
|
1896 |
env->gregs[6],
|
1897 |
env->gregs[7],
|
1898 |
env->gregs[0],
|
1899 |
env->gregs[1]);
|
1900 |
env->gregs[0] = ret;
|
1901 |
break;
|
1902 |
case EXCP_INTERRUPT:
|
1903 |
/* just indicate that signals should be handled asap */
|
1904 |
break;
|
1905 |
case EXCP_DEBUG:
|
1906 |
{ |
1907 |
int sig;
|
1908 |
|
1909 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
1910 |
if (sig)
|
1911 |
{ |
1912 |
info.si_signo = sig; |
1913 |
info.si_errno = 0;
|
1914 |
info.si_code = TARGET_TRAP_BRKPT; |
1915 |
queue_signal(env, info.si_signo, &info); |
1916 |
} |
1917 |
} |
1918 |
break;
|
1919 |
case 0xa0: |
1920 |
case 0xc0: |
1921 |
info.si_signo = SIGSEGV; |
1922 |
info.si_errno = 0;
|
1923 |
info.si_code = TARGET_SEGV_MAPERR; |
1924 |
info._sifields._sigfault._addr = env->tea; |
1925 |
queue_signal(env, info.si_signo, &info); |
1926 |
break;
|
1927 |
|
1928 |
default:
|
1929 |
printf ("Unhandled trap: 0x%x\n", trapnr);
|
1930 |
cpu_dump_state(env, stderr, fprintf, 0);
|
1931 |
exit (1);
|
1932 |
} |
1933 |
process_pending_signals (env); |
1934 |
} |
1935 |
} |
1936 |
#endif
|
1937 |
|
1938 |
#ifdef TARGET_CRIS
|
1939 |
void cpu_loop (CPUState *env)
|
1940 |
{ |
1941 |
int trapnr, ret;
|
1942 |
target_siginfo_t info; |
1943 |
|
1944 |
while (1) { |
1945 |
trapnr = cpu_cris_exec (env); |
1946 |
switch (trapnr) {
|
1947 |
case 0xaa: |
1948 |
{ |
1949 |
info.si_signo = SIGSEGV; |
1950 |
info.si_errno = 0;
|
1951 |
/* XXX: check env->error_code */
|
1952 |
info.si_code = TARGET_SEGV_MAPERR; |
1953 |
info._sifields._sigfault._addr = env->pregs[PR_EDA]; |
1954 |
queue_signal(env, info.si_signo, &info); |
1955 |
} |
1956 |
break;
|
1957 |
case EXCP_INTERRUPT:
|
1958 |
/* just indicate that signals should be handled asap */
|
1959 |
break;
|
1960 |
case EXCP_BREAK:
|
1961 |
ret = do_syscall(env, |
1962 |
env->regs[9],
|
1963 |
env->regs[10],
|
1964 |
env->regs[11],
|
1965 |
env->regs[12],
|
1966 |
env->regs[13],
|
1967 |
env->pregs[7],
|
1968 |
env->pregs[11]);
|
1969 |
env->regs[10] = ret;
|
1970 |
break;
|
1971 |
case EXCP_DEBUG:
|
1972 |
{ |
1973 |
int sig;
|
1974 |
|
1975 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
1976 |
if (sig)
|
1977 |
{ |
1978 |
info.si_signo = sig; |
1979 |
info.si_errno = 0;
|
1980 |
info.si_code = TARGET_TRAP_BRKPT; |
1981 |
queue_signal(env, info.si_signo, &info); |
1982 |
} |
1983 |
} |
1984 |
break;
|
1985 |
default:
|
1986 |
printf ("Unhandled trap: 0x%x\n", trapnr);
|
1987 |
cpu_dump_state(env, stderr, fprintf, 0);
|
1988 |
exit (1);
|
1989 |
} |
1990 |
process_pending_signals (env); |
1991 |
} |
1992 |
} |
1993 |
#endif
|
1994 |
|
1995 |
#ifdef TARGET_M68K
|
1996 |
|
1997 |
void cpu_loop(CPUM68KState *env)
|
1998 |
{ |
1999 |
int trapnr;
|
2000 |
unsigned int n; |
2001 |
target_siginfo_t info; |
2002 |
TaskState *ts = env->opaque; |
2003 |
|
2004 |
for(;;) {
|
2005 |
trapnr = cpu_m68k_exec(env); |
2006 |
switch(trapnr) {
|
2007 |
case EXCP_ILLEGAL:
|
2008 |
{ |
2009 |
if (ts->sim_syscalls) {
|
2010 |
uint16_t nr; |
2011 |
nr = lduw(env->pc + 2);
|
2012 |
env->pc += 4;
|
2013 |
do_m68k_simcall(env, nr); |
2014 |
} else {
|
2015 |
goto do_sigill;
|
2016 |
} |
2017 |
} |
2018 |
break;
|
2019 |
case EXCP_HALT_INSN:
|
2020 |
/* Semihosing syscall. */
|
2021 |
env->pc += 4;
|
2022 |
do_m68k_semihosting(env, env->dregs[0]);
|
2023 |
break;
|
2024 |
case EXCP_LINEA:
|
2025 |
case EXCP_LINEF:
|
2026 |
case EXCP_UNSUPPORTED:
|
2027 |
do_sigill:
|
2028 |
info.si_signo = SIGILL; |
2029 |
info.si_errno = 0;
|
2030 |
info.si_code = TARGET_ILL_ILLOPN; |
2031 |
info._sifields._sigfault._addr = env->pc; |
2032 |
queue_signal(env, info.si_signo, &info); |
2033 |
break;
|
2034 |
case EXCP_TRAP0:
|
2035 |
{ |
2036 |
ts->sim_syscalls = 0;
|
2037 |
n = env->dregs[0];
|
2038 |
env->pc += 2;
|
2039 |
env->dregs[0] = do_syscall(env,
|
2040 |
n, |
2041 |
env->dregs[1],
|
2042 |
env->dregs[2],
|
2043 |
env->dregs[3],
|
2044 |
env->dregs[4],
|
2045 |
env->dregs[5],
|
2046 |
env->aregs[0]);
|
2047 |
} |
2048 |
break;
|
2049 |
case EXCP_INTERRUPT:
|
2050 |
/* just indicate that signals should be handled asap */
|
2051 |
break;
|
2052 |
case EXCP_ACCESS:
|
2053 |
{ |
2054 |
info.si_signo = SIGSEGV; |
2055 |
info.si_errno = 0;
|
2056 |
/* XXX: check env->error_code */
|
2057 |
info.si_code = TARGET_SEGV_MAPERR; |
2058 |
info._sifields._sigfault._addr = env->mmu.ar; |
2059 |
queue_signal(env, info.si_signo, &info); |
2060 |
} |
2061 |
break;
|
2062 |
case EXCP_DEBUG:
|
2063 |
{ |
2064 |
int sig;
|
2065 |
|
2066 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
2067 |
if (sig)
|
2068 |
{ |
2069 |
info.si_signo = sig; |
2070 |
info.si_errno = 0;
|
2071 |
info.si_code = TARGET_TRAP_BRKPT; |
2072 |
queue_signal(env, info.si_signo, &info); |
2073 |
} |
2074 |
} |
2075 |
break;
|
2076 |
default:
|
2077 |
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
|
2078 |
trapnr); |
2079 |
cpu_dump_state(env, stderr, fprintf, 0);
|
2080 |
abort(); |
2081 |
} |
2082 |
process_pending_signals(env); |
2083 |
} |
2084 |
} |
2085 |
#endif /* TARGET_M68K */ |
2086 |
|
2087 |
#ifdef TARGET_ALPHA
|
2088 |
void cpu_loop (CPUState *env)
|
2089 |
{ |
2090 |
int trapnr;
|
2091 |
target_siginfo_t info; |
2092 |
|
2093 |
while (1) { |
2094 |
trapnr = cpu_alpha_exec (env); |
2095 |
|
2096 |
switch (trapnr) {
|
2097 |
case EXCP_RESET:
|
2098 |
fprintf(stderr, "Reset requested. Exit\n");
|
2099 |
exit(1);
|
2100 |
break;
|
2101 |
case EXCP_MCHK:
|
2102 |
fprintf(stderr, "Machine check exception. Exit\n");
|
2103 |
exit(1);
|
2104 |
break;
|
2105 |
case EXCP_ARITH:
|
2106 |
fprintf(stderr, "Arithmetic trap.\n");
|
2107 |
exit(1);
|
2108 |
break;
|
2109 |
case EXCP_HW_INTERRUPT:
|
2110 |
fprintf(stderr, "External interrupt. Exit\n");
|
2111 |
exit(1);
|
2112 |
break;
|
2113 |
case EXCP_DFAULT:
|
2114 |
fprintf(stderr, "MMU data fault\n");
|
2115 |
exit(1);
|
2116 |
break;
|
2117 |
case EXCP_DTB_MISS_PAL:
|
2118 |
fprintf(stderr, "MMU data TLB miss in PALcode\n");
|
2119 |
exit(1);
|
2120 |
break;
|
2121 |
case EXCP_ITB_MISS:
|
2122 |
fprintf(stderr, "MMU instruction TLB miss\n");
|
2123 |
exit(1);
|
2124 |
break;
|
2125 |
case EXCP_ITB_ACV:
|
2126 |
fprintf(stderr, "MMU instruction access violation\n");
|
2127 |
exit(1);
|
2128 |
break;
|
2129 |
case EXCP_DTB_MISS_NATIVE:
|
2130 |
fprintf(stderr, "MMU data TLB miss\n");
|
2131 |
exit(1);
|
2132 |
break;
|
2133 |
case EXCP_UNALIGN:
|
2134 |
fprintf(stderr, "Unaligned access\n");
|
2135 |
exit(1);
|
2136 |
break;
|
2137 |
case EXCP_OPCDEC:
|
2138 |
fprintf(stderr, "Invalid instruction\n");
|
2139 |
exit(1);
|
2140 |
break;
|
2141 |
case EXCP_FEN:
|
2142 |
fprintf(stderr, "Floating-point not allowed\n");
|
2143 |
exit(1);
|
2144 |
break;
|
2145 |
case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1): |
2146 |
call_pal(env, (trapnr >> 6) | 0x80); |
2147 |
break;
|
2148 |
case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1): |
2149 |
fprintf(stderr, "Privileged call to PALcode\n");
|
2150 |
exit(1);
|
2151 |
break;
|
2152 |
case EXCP_DEBUG:
|
2153 |
{ |
2154 |
int sig;
|
2155 |
|
2156 |
sig = gdb_handlesig (env, TARGET_SIGTRAP); |
2157 |
if (sig)
|
2158 |
{ |
2159 |
info.si_signo = sig; |
2160 |
info.si_errno = 0;
|
2161 |
info.si_code = TARGET_TRAP_BRKPT; |
2162 |
queue_signal(env, info.si_signo, &info); |
2163 |
} |
2164 |
} |
2165 |
break;
|
2166 |
default:
|
2167 |
printf ("Unhandled trap: 0x%x\n", trapnr);
|
2168 |
cpu_dump_state(env, stderr, fprintf, 0);
|
2169 |
exit (1);
|
2170 |
} |
2171 |
process_pending_signals (env); |
2172 |
} |
2173 |
} |
2174 |
#endif /* TARGET_ALPHA */ |
2175 |
|
2176 |
static void usage(void) |
2177 |
{ |
2178 |
printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n" |
2179 |
"usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" |
2180 |
"Linux CPU emulator (compiled for %s emulation)\n"
|
2181 |
"\n"
|
2182 |
"Standard options:\n"
|
2183 |
"-h print this help\n"
|
2184 |
"-g port wait gdb connection to port\n"
|
2185 |
"-L path set the elf interpreter prefix (default=%s)\n"
|
2186 |
"-s size set the stack size in bytes (default=%ld)\n"
|
2187 |
"-cpu model select CPU (-cpu ? for list)\n"
|
2188 |
"-drop-ld-preload drop LD_PRELOAD for target process\n"
|
2189 |
"\n"
|
2190 |
"Debug options:\n"
|
2191 |
"-d options activate log (logfile=%s)\n"
|
2192 |
"-p pagesize set the host page size to 'pagesize'\n"
|
2193 |
"-strace log system calls\n"
|
2194 |
"\n"
|
2195 |
"Environment variables:\n"
|
2196 |
"QEMU_STRACE Print system calls and arguments similar to the\n"
|
2197 |
" 'strace' program. Enable by setting to any value.\n"
|
2198 |
, |
2199 |
TARGET_ARCH, |
2200 |
interp_prefix, |
2201 |
x86_stack_size, |
2202 |
DEBUG_LOGFILE); |
2203 |
_exit(1);
|
2204 |
} |
2205 |
|
2206 |
THREAD CPUState *thread_env; |
2207 |
|
2208 |
/* Assumes contents are already zeroed. */
|
2209 |
void init_task_state(TaskState *ts)
|
2210 |
{ |
2211 |
int i;
|
2212 |
|
2213 |
ts->used = 1;
|
2214 |
ts->first_free = ts->sigqueue_table; |
2215 |
for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { |
2216 |
ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
|
2217 |
} |
2218 |
ts->sigqueue_table[i].next = NULL;
|
2219 |
} |
2220 |
|
2221 |
int main(int argc, char **argv, char **envp) |
2222 |
{ |
2223 |
const char *filename; |
2224 |
const char *cpu_model; |
2225 |
struct target_pt_regs regs1, *regs = ®s1;
|
2226 |
struct image_info info1, *info = &info1;
|
2227 |
TaskState ts1, *ts = &ts1; |
2228 |
CPUState *env; |
2229 |
int optind;
|
2230 |
const char *r; |
2231 |
int gdbstub_port = 0; |
2232 |
int drop_ld_preload = 0, environ_count = 0; |
2233 |
char **target_environ, **wrk, **dst;
|
2234 |
|
2235 |
if (argc <= 1) |
2236 |
usage(); |
2237 |
|
2238 |
qemu_cache_utils_init(envp); |
2239 |
|
2240 |
/* init debug */
|
2241 |
cpu_set_log_filename(DEBUG_LOGFILE); |
2242 |
|
2243 |
cpu_model = NULL;
|
2244 |
optind = 1;
|
2245 |
for(;;) {
|
2246 |
if (optind >= argc)
|
2247 |
break;
|
2248 |
r = argv[optind]; |
2249 |
if (r[0] != '-') |
2250 |
break;
|
2251 |
optind++; |
2252 |
r++; |
2253 |
if (!strcmp(r, "-")) { |
2254 |
break;
|
2255 |
} else if (!strcmp(r, "d")) { |
2256 |
int mask;
|
2257 |
const CPULogItem *item;
|
2258 |
|
2259 |
if (optind >= argc)
|
2260 |
break;
|
2261 |
|
2262 |
r = argv[optind++]; |
2263 |
mask = cpu_str_to_log_mask(r); |
2264 |
if (!mask) {
|
2265 |
printf("Log items (comma separated):\n");
|
2266 |
for(item = cpu_log_items; item->mask != 0; item++) { |
2267 |
printf("%-10s %s\n", item->name, item->help);
|
2268 |
} |
2269 |
exit(1);
|
2270 |
} |
2271 |
cpu_set_log(mask); |
2272 |
} else if (!strcmp(r, "s")) { |
2273 |
r = argv[optind++]; |
2274 |
x86_stack_size = strtol(r, (char **)&r, 0); |
2275 |
if (x86_stack_size <= 0) |
2276 |
usage(); |
2277 |
if (*r == 'M') |
2278 |
x86_stack_size *= 1024 * 1024; |
2279 |
else if (*r == 'k' || *r == 'K') |
2280 |
x86_stack_size *= 1024;
|
2281 |
} else if (!strcmp(r, "L")) { |
2282 |
interp_prefix = argv[optind++]; |
2283 |
} else if (!strcmp(r, "p")) { |
2284 |
qemu_host_page_size = atoi(argv[optind++]); |
2285 |
if (qemu_host_page_size == 0 || |
2286 |
(qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { |
2287 |
fprintf(stderr, "page size must be a power of two\n");
|
2288 |
exit(1);
|
2289 |
} |
2290 |
} else if (!strcmp(r, "g")) { |
2291 |
gdbstub_port = atoi(argv[optind++]); |
2292 |
} else if (!strcmp(r, "r")) { |
2293 |
qemu_uname_release = argv[optind++]; |
2294 |
} else if (!strcmp(r, "cpu")) { |
2295 |
cpu_model = argv[optind++]; |
2296 |
if (strcmp(cpu_model, "?") == 0) { |
2297 |
/* XXX: implement xxx_cpu_list for targets that still miss it */
|
2298 |
#if defined(cpu_list)
|
2299 |
cpu_list(stdout, &fprintf); |
2300 |
#endif
|
2301 |
_exit(1);
|
2302 |
} |
2303 |
} else if (!strcmp(r, "drop-ld-preload")) { |
2304 |
drop_ld_preload = 1;
|
2305 |
} else if (!strcmp(r, "strace")) { |
2306 |
do_strace = 1;
|
2307 |
} else
|
2308 |
{ |
2309 |
usage(); |
2310 |
} |
2311 |
} |
2312 |
if (optind >= argc)
|
2313 |
usage(); |
2314 |
filename = argv[optind]; |
2315 |
|
2316 |
/* Zero out regs */
|
2317 |
memset(regs, 0, sizeof(struct target_pt_regs)); |
2318 |
|
2319 |
/* Zero out image_info */
|
2320 |
memset(info, 0, sizeof(struct image_info)); |
2321 |
|
2322 |
/* Scan interp_prefix dir for replacement files. */
|
2323 |
init_paths(interp_prefix); |
2324 |
|
2325 |
if (cpu_model == NULL) { |
2326 |
#if defined(TARGET_I386)
|
2327 |
#ifdef TARGET_X86_64
|
2328 |
cpu_model = "qemu64";
|
2329 |
#else
|
2330 |
cpu_model = "qemu32";
|
2331 |
#endif
|
2332 |
#elif defined(TARGET_ARM)
|
2333 |
cpu_model = "arm926";
|
2334 |
#elif defined(TARGET_M68K)
|
2335 |
cpu_model = "any";
|
2336 |
#elif defined(TARGET_SPARC)
|
2337 |
#ifdef TARGET_SPARC64
|
2338 |
cpu_model = "TI UltraSparc II";
|
2339 |
#else
|
2340 |
cpu_model = "Fujitsu MB86904";
|
2341 |
#endif
|
2342 |
#elif defined(TARGET_MIPS)
|
2343 |
#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
|
2344 |
cpu_model = "20Kc";
|
2345 |
#else
|
2346 |
cpu_model = "24Kf";
|
2347 |
#endif
|
2348 |
#elif defined(TARGET_PPC)
|
2349 |
#ifdef TARGET_PPC64
|
2350 |
cpu_model = "970";
|
2351 |
#else
|
2352 |
cpu_model = "750";
|
2353 |
#endif
|
2354 |
#else
|
2355 |
cpu_model = "any";
|
2356 |
#endif
|
2357 |
} |
2358 |
cpu_exec_init_all(0);
|
2359 |
/* NOTE: we need to init the CPU at this stage to get
|
2360 |
qemu_host_page_size */
|
2361 |
env = cpu_init(cpu_model); |
2362 |
if (!env) {
|
2363 |
fprintf(stderr, "Unable to find CPU definition\n");
|
2364 |
exit(1);
|
2365 |
} |
2366 |
thread_env = env; |
2367 |
|
2368 |
if (getenv("QEMU_STRACE")) { |
2369 |
do_strace = 1;
|
2370 |
} |
2371 |
|
2372 |
wrk = environ; |
2373 |
while (*(wrk++))
|
2374 |
environ_count++; |
2375 |
|
2376 |
target_environ = malloc((environ_count + 1) * sizeof(char *)); |
2377 |
if (!target_environ)
|
2378 |
abort(); |
2379 |
for (wrk = environ, dst = target_environ; *wrk; wrk++) {
|
2380 |
if (drop_ld_preload && !strncmp(*wrk, "LD_PRELOAD=", 11)) |
2381 |
continue;
|
2382 |
*(dst++) = strdup(*wrk); |
2383 |
} |
2384 |
*dst = NULL; /* NULL terminate target_environ */ |
2385 |
|
2386 |
if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) { |
2387 |
printf("Error loading %s\n", filename);
|
2388 |
_exit(1);
|
2389 |
} |
2390 |
|
2391 |
for (wrk = target_environ; *wrk; wrk++) {
|
2392 |
free(*wrk); |
2393 |
} |
2394 |
|
2395 |
free(target_environ); |
2396 |
|
2397 |
log_page_dump(); |
2398 |
|
2399 |
qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); |
2400 |
qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); |
2401 |
qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", |
2402 |
info->start_code); |
2403 |
qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", |
2404 |
info->start_data); |
2405 |
qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); |
2406 |
qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", |
2407 |
info->start_stack); |
2408 |
qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); |
2409 |
qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); |
2410 |
|
2411 |
target_set_brk(info->brk); |
2412 |
syscall_init(); |
2413 |
signal_init(); |
2414 |
|
2415 |
/* build Task State */
|
2416 |
memset(ts, 0, sizeof(TaskState)); |
2417 |
init_task_state(ts); |
2418 |
ts->info = info; |
2419 |
env->opaque = ts; |
2420 |
|
2421 |
#if defined(TARGET_I386)
|
2422 |
cpu_x86_set_cpl(env, 3);
|
2423 |
|
2424 |
env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
|
2425 |
env->hflags |= HF_PE_MASK; |
2426 |
if (env->cpuid_features & CPUID_SSE) {
|
2427 |
env->cr[4] |= CR4_OSFXSR_MASK;
|
2428 |
env->hflags |= HF_OSFXSR_MASK; |
2429 |
} |
2430 |
#ifndef TARGET_ABI32
|
2431 |
/* enable 64 bit mode if possible */
|
2432 |
if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
|
2433 |
fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
|
2434 |
exit(1);
|
2435 |
} |
2436 |
env->cr[4] |= CR4_PAE_MASK;
|
2437 |
env->efer |= MSR_EFER_LMA | MSR_EFER_LME; |
2438 |
env->hflags |= HF_LMA_MASK; |
2439 |
#endif
|
2440 |
|
2441 |
/* flags setup : we activate the IRQs by default as in user mode */
|
2442 |
env->eflags |= IF_MASK; |
2443 |
|
2444 |
/* linux register setup */
|
2445 |
#ifndef TARGET_ABI32
|
2446 |
env->regs[R_EAX] = regs->rax; |
2447 |
env->regs[R_EBX] = regs->rbx; |
2448 |
env->regs[R_ECX] = regs->rcx; |
2449 |
env->regs[R_EDX] = regs->rdx; |
2450 |
env->regs[R_ESI] = regs->rsi; |
2451 |
env->regs[R_EDI] = regs->rdi; |
2452 |
env->regs[R_EBP] = regs->rbp; |
2453 |
env->regs[R_ESP] = regs->rsp; |
2454 |
env->eip = regs->rip; |
2455 |
#else
|
2456 |
env->regs[R_EAX] = regs->eax; |
2457 |
env->regs[R_EBX] = regs->ebx; |
2458 |
env->regs[R_ECX] = regs->ecx; |
2459 |
env->regs[R_EDX] = regs->edx; |
2460 |
env->regs[R_ESI] = regs->esi; |
2461 |
env->regs[R_EDI] = regs->edi; |
2462 |
env->regs[R_EBP] = regs->ebp; |
2463 |
env->regs[R_ESP] = regs->esp; |
2464 |
env->eip = regs->eip; |
2465 |
#endif
|
2466 |
|
2467 |
/* linux interrupt setup */
|
2468 |
#ifndef TARGET_ABI32
|
2469 |
env->idt.limit = 511;
|
2470 |
#else
|
2471 |
env->idt.limit = 255;
|
2472 |
#endif
|
2473 |
env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), |
2474 |
PROT_READ|PROT_WRITE, |
2475 |
MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); |
2476 |
idt_table = g2h(env->idt.base); |
2477 |
set_idt(0, 0); |
2478 |
set_idt(1, 0); |
2479 |
set_idt(2, 0); |
2480 |
set_idt(3, 3); |
2481 |
set_idt(4, 3); |
2482 |
set_idt(5, 0); |
2483 |
set_idt(6, 0); |
2484 |
set_idt(7, 0); |
2485 |
set_idt(8, 0); |
2486 |
set_idt(9, 0); |
2487 |
set_idt(10, 0); |
2488 |
set_idt(11, 0); |
2489 |
set_idt(12, 0); |
2490 |
set_idt(13, 0); |
2491 |
set_idt(14, 0); |
2492 |
set_idt(15, 0); |
2493 |
set_idt(16, 0); |
2494 |
set_idt(17, 0); |
2495 |
set_idt(18, 0); |
2496 |
set_idt(19, 0); |
2497 |
set_idt(0x80, 3); |
2498 |
|
2499 |
/* linux segment setup */
|
2500 |
{ |
2501 |
uint64_t *gdt_table; |
2502 |
env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, |
2503 |
PROT_READ|PROT_WRITE, |
2504 |
MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); |
2505 |
env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; |
2506 |
gdt_table = g2h(env->gdt.base); |
2507 |
#ifdef TARGET_ABI32
|
2508 |
write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
2509 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | |
2510 |
(3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); |
2511 |
#else
|
2512 |
/* 64 bit code segment */
|
2513 |
write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
2514 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | |
2515 |
DESC_L_MASK | |
2516 |
(3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); |
2517 |
#endif
|
2518 |
write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, |
2519 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | |
2520 |
(3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); |
2521 |
} |
2522 |
cpu_x86_load_seg(env, R_CS, __USER_CS); |
2523 |
cpu_x86_load_seg(env, R_SS, __USER_DS); |
2524 |
#ifdef TARGET_ABI32
|
2525 |
cpu_x86_load_seg(env, R_DS, __USER_DS); |
2526 |
cpu_x86_load_seg(env, R_ES, __USER_DS); |
2527 |
cpu_x86_load_seg(env, R_FS, __USER_DS); |
2528 |
cpu_x86_load_seg(env, R_GS, __USER_DS); |
2529 |
/* This hack makes Wine work... */
|
2530 |
env->segs[R_FS].selector = 0;
|
2531 |
#else
|
2532 |
cpu_x86_load_seg(env, R_DS, 0);
|
2533 |
cpu_x86_load_seg(env, R_ES, 0);
|
2534 |
cpu_x86_load_seg(env, R_FS, 0);
|
2535 |
cpu_x86_load_seg(env, R_GS, 0);
|
2536 |
#endif
|
2537 |
#elif defined(TARGET_ARM)
|
2538 |
{ |
2539 |
int i;
|
2540 |
cpsr_write(env, regs->uregs[16], 0xffffffff); |
2541 |
for(i = 0; i < 16; i++) { |
2542 |
env->regs[i] = regs->uregs[i]; |
2543 |
} |
2544 |
} |
2545 |
#elif defined(TARGET_SPARC)
|
2546 |
{ |
2547 |
int i;
|
2548 |
env->pc = regs->pc; |
2549 |
env->npc = regs->npc; |
2550 |
env->y = regs->y; |
2551 |
for(i = 0; i < 8; i++) |
2552 |
env->gregs[i] = regs->u_regs[i]; |
2553 |
for(i = 0; i < 8; i++) |
2554 |
env->regwptr[i] = regs->u_regs[i + 8];
|
2555 |
} |
2556 |
#elif defined(TARGET_PPC)
|
2557 |
{ |
2558 |
int i;
|
2559 |
|
2560 |
#if defined(TARGET_PPC64)
|
2561 |
#if defined(TARGET_ABI32)
|
2562 |
env->msr &= ~((target_ulong)1 << MSR_SF);
|
2563 |
#else
|
2564 |
env->msr |= (target_ulong)1 << MSR_SF;
|
2565 |
#endif
|
2566 |
#endif
|
2567 |
env->nip = regs->nip; |
2568 |
for(i = 0; i < 32; i++) { |
2569 |
env->gpr[i] = regs->gpr[i]; |
2570 |
} |
2571 |
} |
2572 |
#elif defined(TARGET_M68K)
|
2573 |
{ |
2574 |
env->pc = regs->pc; |
2575 |
env->dregs[0] = regs->d0;
|
2576 |
env->dregs[1] = regs->d1;
|
2577 |
env->dregs[2] = regs->d2;
|
2578 |
env->dregs[3] = regs->d3;
|
2579 |
env->dregs[4] = regs->d4;
|
2580 |
env->dregs[5] = regs->d5;
|
2581 |
env->dregs[6] = regs->d6;
|
2582 |
env->dregs[7] = regs->d7;
|
2583 |
env->aregs[0] = regs->a0;
|
2584 |
env->aregs[1] = regs->a1;
|
2585 |
env->aregs[2] = regs->a2;
|
2586 |
env->aregs[3] = regs->a3;
|
2587 |
env->aregs[4] = regs->a4;
|
2588 |
env->aregs[5] = regs->a5;
|
2589 |
env->aregs[6] = regs->a6;
|
2590 |
env->aregs[7] = regs->usp;
|
2591 |
env->sr = regs->sr; |
2592 |
ts->sim_syscalls = 1;
|
2593 |
} |
2594 |
#elif defined(TARGET_MIPS)
|
2595 |
{ |
2596 |
int i;
|
2597 |
|
2598 |
for(i = 0; i < 32; i++) { |
2599 |
env->active_tc.gpr[i] = regs->regs[i]; |
2600 |
} |
2601 |
env->active_tc.PC = regs->cp0_epc; |
2602 |
} |
2603 |
#elif defined(TARGET_SH4)
|
2604 |
{ |
2605 |
int i;
|
2606 |
|
2607 |
for(i = 0; i < 16; i++) { |
2608 |
env->gregs[i] = regs->regs[i]; |
2609 |
} |
2610 |
env->pc = regs->pc; |
2611 |
} |
2612 |
#elif defined(TARGET_ALPHA)
|
2613 |
{ |
2614 |
int i;
|
2615 |
|
2616 |
for(i = 0; i < 28; i++) { |
2617 |
env->ir[i] = ((abi_ulong *)regs)[i]; |
2618 |
} |
2619 |
env->ipr[IPR_USP] = regs->usp; |
2620 |
env->ir[30] = regs->usp;
|
2621 |
env->pc = regs->pc; |
2622 |
env->unique = regs->unique; |
2623 |
} |
2624 |
#elif defined(TARGET_CRIS)
|
2625 |
{ |
2626 |
env->regs[0] = regs->r0;
|
2627 |
env->regs[1] = regs->r1;
|
2628 |
env->regs[2] = regs->r2;
|
2629 |
env->regs[3] = regs->r3;
|
2630 |
env->regs[4] = regs->r4;
|
2631 |
env->regs[5] = regs->r5;
|
2632 |
env->regs[6] = regs->r6;
|
2633 |
env->regs[7] = regs->r7;
|
2634 |
env->regs[8] = regs->r8;
|
2635 |
env->regs[9] = regs->r9;
|
2636 |
env->regs[10] = regs->r10;
|
2637 |
env->regs[11] = regs->r11;
|
2638 |
env->regs[12] = regs->r12;
|
2639 |
env->regs[13] = regs->r13;
|
2640 |
env->regs[14] = info->start_stack;
|
2641 |
env->regs[15] = regs->acr;
|
2642 |
env->pc = regs->erp; |
2643 |
} |
2644 |
#else
|
2645 |
#error unsupported target CPU
|
2646 |
#endif
|
2647 |
|
2648 |
#if defined(TARGET_ARM) || defined(TARGET_M68K)
|
2649 |
ts->stack_base = info->start_stack; |
2650 |
ts->heap_base = info->brk; |
2651 |
/* This will be filled in on the first SYS_HEAPINFO call. */
|
2652 |
ts->heap_limit = 0;
|
2653 |
#endif
|
2654 |
|
2655 |
if (gdbstub_port) {
|
2656 |
gdbserver_start (gdbstub_port); |
2657 |
gdb_handlesig(env, 0);
|
2658 |
} |
2659 |
cpu_loop(env); |
2660 |
/* never exits */
|
2661 |
return 0; |
2662 |
} |