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/*
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* QEMU USB EHCI Emulation
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*
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* Copyright(c) 2008 Emutex Ltd. (address@hidden)
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*
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* EHCI project was started by Mark Burkley, with contributions by
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* Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
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* Jan Kiszka and Vincent Palatin contributed bugfixes.
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* TODO:
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* o Downstream port handoff
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "usb.h"
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#include "pci.h"
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#include "monitor.h"
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#define EHCI_DEBUG 0
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#define STATE_DEBUG 0 /* state transitions */
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#if EHCI_DEBUG || STATE_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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#if STATE_DEBUG
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#define DPRINTF_ST DPRINTF
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#else
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#define DPRINTF_ST(...)
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#endif
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/* internal processing - reset HC to try and recover */
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#define USB_RET_PROCERR (-99)
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#define MMIO_SIZE 0x1000
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/* Capability Registers Base Address - section 2.2 */
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#define CAPREGBASE 0x0000
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#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
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#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
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#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
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#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
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#define EECP HCCPARAMS + 1
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#define HCSPPORTROUTE1 CAPREGBASE + 0x000c
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#define HCSPPORTROUTE2 CAPREGBASE + 0x0010
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#define OPREGBASE 0x0020 // Operational Registers Base Address
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#define USBCMD OPREGBASE + 0x0000
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop
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#define USBCMD_HCRESET (1 << 1) // HC Reset
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#define USBCMD_FLS (3 << 2) // Frame List Size
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#define USBCMD_FLS_SH 2 // Frame List Size Shift
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift
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#define USBSTS OPREGBASE + 0x0004
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#define USBSTS_RO_MASK 0x0000003f
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#define USBSTS_INT (1 << 0) // USB Interrupt
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt
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#define USBSTS_PCD (1 << 2) // Port Change Detect
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#define USBSTS_FLR (1 << 3) // Frame List Rollover
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#define USBSTS_HSE (1 << 4) // Host System Error
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
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#define USBSTS_HALT (1 << 12) // HC Halted
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#define USBSTS_REC (1 << 13) // Reclamation
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR OPREGBASE + 0x0008
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#define USBINTR_MASK 0x0000003f
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#define FRINDEX OPREGBASE + 0x000c
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#define CTRLDSSEGMENT OPREGBASE + 0x0010
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#define PERIODICLISTBASE OPREGBASE + 0x0014
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#define ASYNCLISTADDR OPREGBASE + 0x0018
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#define ASYNCLISTADDR_MASK 0xffffffe0
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#define CONFIGFLAG OPREGBASE + 0x0040
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#define PORTSC (OPREGBASE + 0x0044)
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#define PORTSC_BEGIN PORTSC
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#define PORTSC_END (PORTSC + 4 * NB_PORTS)
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/*
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* Bits that are reserverd or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007021c5
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#define PORTSC_RWC_MASK 0x0000002a
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
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#define PORTSC_PTC (15 << 16) // Port Test Control
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#define PORTSC_PTC_SH 16 // Port Test Control shift
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#define PORTSC_PIC (3 << 14) // Port Indicator Control
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift
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#define PORTSC_POWNER (1 << 13) // Port Owner
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#define PORTSC_PPOWER (1 << 12) // Port Power
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
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#define PORTSC_PRESET (1 << 8) // Port Reset
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend
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#define PORTSC_FPRES (1 << 6) // Force Port Resume
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#define PORTSC_OCC (1 << 5) // Over Current Change
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#define PORTSC_OCA (1 << 4) // Over Current Active
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
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#define PORTSC_PED (1 << 2) // Port Enable/Disable
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#define PORTSC_CSC (1 << 1) // Connect Status Change
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status
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#define FRAME_TIMER_FREQ 1000
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#define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
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#define NB_MAXINTRATE 8 // Max rate at which controller issues ints
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#define NB_PORTS 4 // Number of downstream ports
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#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
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#define MAX_ITERATIONS 20 // Max number of QH before we break the loop
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#define MAX_QH 100 // Max allowable queue heads in a chain
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/* Internal periodic / asynchronous schedule state machine states
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*/
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typedef enum {
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EST_INACTIVE = 1000,
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EST_ACTIVE,
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EST_EXECUTING,
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EST_SLEEPING,
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/* The following states are internal to the state machine function
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*/
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EST_WAITLISTHEAD,
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EST_FETCHENTRY,
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EST_FETCHQH,
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EST_FETCHITD,
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EST_ADVANCEQUEUE,
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EST_FETCHQTD,
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EST_EXECUTE,
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EST_WRITEBACK,
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EST_HORIZONTALQH
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} EHCI_STATES;
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/* macros for accessing fields within next link pointer entry */
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#define NLPTR_GET(x) ((x) & 0xffffffe0)
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#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
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#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
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/* link pointer types */
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#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
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#define NLPTR_TYPE_QH 1 // queue head
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#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
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#define NLPTR_TYPE_FSTN 3 // frame span traversal node
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/* EHCI spec version 1.0 Section 3.3
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*/
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typedef struct EHCIitd {
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uint32_t next;
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uint32_t transact[8];
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#define ITD_XACT_ACTIVE (1 << 31)
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#define ITD_XACT_DBERROR (1 << 30)
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#define ITD_XACT_BABBLE (1 << 29)
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#define ITD_XACT_XACTERR (1 << 28)
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#define ITD_XACT_LENGTH_MASK 0x0fff0000
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#define ITD_XACT_LENGTH_SH 16
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#define ITD_XACT_IOC (1 << 15)
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#define ITD_XACT_PGSEL_MASK 0x00007000
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#define ITD_XACT_PGSEL_SH 12
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#define ITD_XACT_OFFSET_MASK 0x00000fff
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uint32_t bufptr[7];
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#define ITD_BUFPTR_MASK 0xfffff000
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#define ITD_BUFPTR_SH 12
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#define ITD_BUFPTR_EP_MASK 0x00000f00
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#define ITD_BUFPTR_EP_SH 8
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#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
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#define ITD_BUFPTR_DEVADDR_SH 0
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#define ITD_BUFPTR_DIRECTION (1 << 11)
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#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
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#define ITD_BUFPTR_MAXPKT_SH 0
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#define ITD_BUFPTR_MULT_MASK 0x00000003
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} EHCIitd;
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/* EHCI spec version 1.0 Section 3.4
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*/
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typedef struct EHCIsitd {
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uint32_t next; // Standard next link pointer
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uint32_t epchar;
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#define SITD_EPCHAR_IO (1 << 31)
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#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
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#define SITD_EPCHAR_PORTNUM_SH 24
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#define SITD_EPCHAR_HUBADD_MASK 0x007f0000
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#define SITD_EPCHAR_HUBADDR_SH 16
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#define SITD_EPCHAR_EPNUM_MASK 0x00000f00
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#define SITD_EPCHAR_EPNUM_SH 8
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#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
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uint32_t uframe;
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#define SITD_UFRAME_CMASK_MASK 0x0000ff00
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#define SITD_UFRAME_CMASK_SH 8
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#define SITD_UFRAME_SMASK_MASK 0x000000ff
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uint32_t results;
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#define SITD_RESULTS_IOC (1 << 31)
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#define SITD_RESULTS_PGSEL (1 << 30)
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#define SITD_RESULTS_TBYTES_MASK 0x03ff0000
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#define SITD_RESULTS_TYBYTES_SH 16
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#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
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#define SITD_RESULTS_CPROGMASK_SH 8
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#define SITD_RESULTS_ACTIVE (1 << 7)
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#define SITD_RESULTS_ERR (1 << 6)
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#define SITD_RESULTS_DBERR (1 << 5)
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#define SITD_RESULTS_BABBLE (1 << 4)
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#define SITD_RESULTS_XACTERR (1 << 3)
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#define SITD_RESULTS_MISSEDUF (1 << 2)
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#define SITD_RESULTS_SPLITXSTATE (1 << 1)
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uint32_t bufptr[2];
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#define SITD_BUFPTR_MASK 0xfffff000
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#define SITD_BUFPTR_CURROFF_MASK 0x00000fff
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#define SITD_BUFPTR_TPOS_MASK 0x00000018
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#define SITD_BUFPTR_TPOS_SH 3
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#define SITD_BUFPTR_TCNT_MASK 0x00000007
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uint32_t backptr; // Standard next link pointer
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} EHCIsitd;
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/* EHCI spec version 1.0 Section 3.5
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*/
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typedef struct EHCIqtd {
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uint32_t next; // Standard next link pointer
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uint32_t altnext; // Standard next link pointer
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uint32_t token;
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#define QTD_TOKEN_DTOGGLE (1 << 31)
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#define QTD_TOKEN_TBYTES_MASK 0x7fff0000
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#define QTD_TOKEN_TBYTES_SH 16
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#define QTD_TOKEN_IOC (1 << 15)
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#define QTD_TOKEN_CPAGE_MASK 0x00007000
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#define QTD_TOKEN_CPAGE_SH 12
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#define QTD_TOKEN_CERR_MASK 0x00000c00
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#define QTD_TOKEN_CERR_SH 10
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#define QTD_TOKEN_PID_MASK 0x00000300
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#define QTD_TOKEN_PID_SH 8
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#define QTD_TOKEN_ACTIVE (1 << 7)
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#define QTD_TOKEN_HALT (1 << 6)
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#define QTD_TOKEN_DBERR (1 << 5)
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#define QTD_TOKEN_BABBLE (1 << 4)
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#define QTD_TOKEN_XACTERR (1 << 3)
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#define QTD_TOKEN_MISSEDUF (1 << 2)
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#define QTD_TOKEN_SPLITXSTATE (1 << 1)
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#define QTD_TOKEN_PING (1 << 0)
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uint32_t bufptr[5]; // Standard buffer pointer
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#define QTD_BUFPTR_MASK 0xfffff000
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} EHCIqtd;
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/* EHCI spec version 1.0 Section 3.6
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*/
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typedef struct EHCIqh {
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uint32_t next; // Standard next link pointer
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/* endpoint characteristics */
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uint32_t epchar;
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#define QH_EPCHAR_RL_MASK 0xf0000000
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#define QH_EPCHAR_RL_SH 28
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#define QH_EPCHAR_C (1 << 27)
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#define QH_EPCHAR_MPLEN_MASK 0x07FF0000
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#define QH_EPCHAR_MPLEN_SH 16
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#define QH_EPCHAR_H (1 << 15)
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#define QH_EPCHAR_DTC (1 << 14)
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#define QH_EPCHAR_EPS_MASK 0x00003000
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#define QH_EPCHAR_EPS_SH 12
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#define EHCI_QH_EPS_FULL 0
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#define EHCI_QH_EPS_LOW 1
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#define EHCI_QH_EPS_HIGH 2
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#define EHCI_QH_EPS_RESERVED 3
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#define QH_EPCHAR_EP_MASK 0x00000f00
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#define QH_EPCHAR_EP_SH 8
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#define QH_EPCHAR_I (1 << 7)
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#define QH_EPCHAR_DEVADDR_MASK 0x0000007f
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#define QH_EPCHAR_DEVADDR_SH 0
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/* endpoint capabilities */
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uint32_t epcap;
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#define QH_EPCAP_MULT_MASK 0xc0000000
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#define QH_EPCAP_MULT_SH 30
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#define QH_EPCAP_PORTNUM_MASK 0x3f800000
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#define QH_EPCAP_PORTNUM_SH 23
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#define QH_EPCAP_HUBADDR_MASK 0x007f0000
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#define QH_EPCAP_HUBADDR_SH 16
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#define QH_EPCAP_CMASK_MASK 0x0000ff00
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#define QH_EPCAP_CMASK_SH 8
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#define QH_EPCAP_SMASK_MASK 0x000000ff
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#define QH_EPCAP_SMASK_SH 0
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uint32_t current_qtd; // Standard next link pointer
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uint32_t next_qtd; // Standard next link pointer
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uint32_t altnext_qtd;
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#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
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#define QH_ALTNEXT_NAKCNT_SH 1
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uint32_t token; // Same as QTD token
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uint32_t bufptr[5]; // Standard buffer pointer
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#define BUFPTR_CPROGMASK_MASK 0x000000ff
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#define BUFPTR_FRAMETAG_MASK 0x0000001f
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#define BUFPTR_SBYTES_MASK 0x00000fe0
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#define BUFPTR_SBYTES_SH 5
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} EHCIqh;
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/* EHCI spec version 1.0 Section 3.7
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*/
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typedef struct EHCIfstn {
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uint32_t next; // Standard next link pointer
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uint32_t backptr; // Standard next link pointer
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} EHCIfstn;
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typedef struct {
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PCIDevice dev;
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qemu_irq irq;
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target_phys_addr_t mem_base;
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int mem;
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int num_ports;
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/*
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* EHCI spec version 1.0 Section 2.3
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* Host Controller Operational Registers
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*/
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union {
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uint8_t mmio[MMIO_SIZE];
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struct {
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uint8_t cap[OPREGBASE];
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uint32_t usbcmd;
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uint32_t usbsts;
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|
359 |
uint32_t usbintr;
|
|
360 |
uint32_t frindex;
|
|
361 |
uint32_t ctrldssegment;
|
|
362 |
uint32_t periodiclistbase;
|
|
363 |
uint32_t asynclistaddr;
|
|
364 |
uint32_t notused[9];
|
|
365 |
uint32_t configflag;
|
|
366 |
uint32_t portsc[NB_PORTS];
|
|
367 |
};
|
|
368 |
};
|
|
369 |
/*
|
|
370 |
* Internal states, shadow registers, etc
|
|
371 |
*/
|
|
372 |
uint32_t sofv;
|
|
373 |
QEMUTimer *frame_timer;
|
|
374 |
int attach_poll_counter;
|
|
375 |
int astate; // Current state in asynchronous schedule
|
|
376 |
int pstate; // Current state in periodic schedule
|
|
377 |
USBPort ports[NB_PORTS];
|
|
378 |
uint8_t buffer[BUFF_SIZE];
|
|
379 |
uint32_t usbsts_pending;
|
|
380 |
|
|
381 |
/* cached data from guest - needs to be flushed
|
|
382 |
* when guest removes an entry (doorbell, handshake sequence)
|
|
383 |
*/
|
|
384 |
EHCIqh qh; // copy of current QH (being worked on)
|
|
385 |
uint32_t qhaddr; // address QH read from
|
|
386 |
|
|
387 |
EHCIqtd qtd; // copy of current QTD (being worked on)
|
|
388 |
uint32_t qtdaddr; // address QTD read from
|
|
389 |
|
|
390 |
uint32_t itdaddr; // current ITD
|
|
391 |
|
|
392 |
uint32_t fetch_addr; // which address to look at next
|
|
393 |
|
|
394 |
USBBus bus;
|
|
395 |
USBPacket usb_packet;
|
|
396 |
int async_complete;
|
|
397 |
uint32_t tbytes;
|
|
398 |
int pid;
|
|
399 |
int exec_status;
|
|
400 |
int isoch_pause;
|
|
401 |
uint32_t last_run_usec;
|
|
402 |
uint32_t frame_end_usec;
|
|
403 |
} EHCIState;
|
|
404 |
|
|
405 |
#define SET_LAST_RUN_CLOCK(s) \
|
|
406 |
(s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
|
|
407 |
|
|
408 |
/* nifty macros from Arnon's EHCI version */
|
|
409 |
#define get_field(data, field) \
|
|
410 |
(((data) & field##_MASK) >> field##_SH)
|
|
411 |
|
|
412 |
#define set_field(data, newval, field) do { \
|
|
413 |
uint32_t val = *data; \
|
|
414 |
val &= ~ field##_MASK; \
|
|
415 |
val |= ((newval) << field##_SH) & field##_MASK; \
|
|
416 |
*data = val; \
|
|
417 |
} while(0)
|
|
418 |
|
|
419 |
|
|
420 |
#if EHCI_DEBUG
|
|
421 |
static const char *addr2str(unsigned addr)
|
|
422 |
{
|
|
423 |
const char *r = " unknown";
|
|
424 |
const char *n[] = {
|
|
425 |
[ CAPLENGTH ] = " CAPLENGTH",
|
|
426 |
[ HCIVERSION ] = "HCIVERSION",
|
|
427 |
[ HCSPARAMS ] = " HCSPARAMS",
|
|
428 |
[ HCCPARAMS ] = " HCCPARAMS",
|
|
429 |
[ USBCMD ] = " COMMAND",
|
|
430 |
[ USBSTS ] = " STATUS",
|
|
431 |
[ USBINTR ] = " INTERRUPT",
|
|
432 |
[ FRINDEX ] = " FRAME IDX",
|
|
433 |
[ PERIODICLISTBASE ] = "P-LIST BASE",
|
|
434 |
[ ASYNCLISTADDR ] = "A-LIST ADDR",
|
|
435 |
[ PORTSC_BEGIN ...
|
|
436 |
PORTSC_END ] = "PORT STATUS",
|
|
437 |
[ CONFIGFLAG ] = "CONFIG FLAG",
|
|
438 |
};
|
|
439 |
|
|
440 |
if (addr < ARRAY_SIZE(n) && n[addr] != NULL) {
|
|
441 |
return n[addr];
|
|
442 |
} else {
|
|
443 |
return r;
|
|
444 |
}
|
|
445 |
}
|
|
446 |
#endif
|
|
447 |
|
|
448 |
|
|
449 |
static inline void ehci_set_interrupt(EHCIState *s, int intr)
|
|
450 |
{
|
|
451 |
int level = 0;
|
|
452 |
|
|
453 |
// TODO honour interrupt threshold requests
|
|
454 |
|
|
455 |
s->usbsts |= intr;
|
|
456 |
|
|
457 |
if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
|
|
458 |
level = 1;
|
|
459 |
}
|
|
460 |
|
|
461 |
qemu_set_irq(s->irq, level);
|
|
462 |
}
|
|
463 |
|
|
464 |
static inline void ehci_record_interrupt(EHCIState *s, int intr)
|
|
465 |
{
|
|
466 |
s->usbsts_pending |= intr;
|
|
467 |
}
|
|
468 |
|
|
469 |
static inline void ehci_commit_interrupt(EHCIState *s)
|
|
470 |
{
|
|
471 |
if (!s->usbsts_pending) {
|
|
472 |
return;
|
|
473 |
}
|
|
474 |
ehci_set_interrupt(s, s->usbsts_pending);
|
|
475 |
s->usbsts_pending = 0;
|
|
476 |
}
|
|
477 |
|
|
478 |
/* Attach or detach a device on root hub */
|
|
479 |
|
|
480 |
static void ehci_attach(USBPort *port)
|
|
481 |
{
|
|
482 |
EHCIState *s = port->opaque;
|
|
483 |
uint32_t *portsc = &s->portsc[port->index];
|
|
484 |
|
|
485 |
DPRINTF("ehci_attach invoked for index %d, portsc 0x%x, desc %s\n",
|
|
486 |
port->index, *portsc, port->dev->product_desc);
|
|
487 |
|
|
488 |
*portsc |= PORTSC_CONNECT;
|
|
489 |
*portsc |= PORTSC_CSC;
|
|
490 |
|
|
491 |
/*
|
|
492 |
* If a high speed device is attached then we own this port(indicated
|
|
493 |
* by zero in the PORTSC_POWNER bit field) so set the status bit
|
|
494 |
* and set an interrupt if enabled.
|
|
495 |
*/
|
|
496 |
if ( !(*portsc & PORTSC_POWNER)) {
|
|
497 |
ehci_set_interrupt(s, USBSTS_PCD);
|
|
498 |
}
|
|
499 |
}
|
|
500 |
|
|
501 |
static void ehci_detach(USBPort *port)
|
|
502 |
{
|
|
503 |
EHCIState *s = port->opaque;
|
|
504 |
uint32_t *portsc = &s->portsc[port->index];
|
|
505 |
|
|
506 |
DPRINTF("ehci_attach invoked for index %d, portsc 0x%x\n",
|
|
507 |
port->index, *portsc);
|
|
508 |
|
|
509 |
*portsc &= ~PORTSC_CONNECT;
|
|
510 |
*portsc |= PORTSC_CSC;
|
|
511 |
|
|
512 |
/*
|
|
513 |
* If a high speed device is attached then we own this port(indicated
|
|
514 |
* by zero in the PORTSC_POWNER bit field) so set the status bit
|
|
515 |
* and set an interrupt if enabled.
|
|
516 |
*/
|
|
517 |
if ( !(*portsc & PORTSC_POWNER)) {
|
|
518 |
ehci_set_interrupt(s, USBSTS_PCD);
|
|
519 |
}
|
|
520 |
}
|
|
521 |
|
|
522 |
/* 4.1 host controller initialization */
|
|
523 |
static void ehci_reset(void *opaque)
|
|
524 |
{
|
|
525 |
EHCIState *s = opaque;
|
|
526 |
uint8_t *pci_conf;
|
|
527 |
int i;
|
|
528 |
|
|
529 |
pci_conf = s->dev.config;
|
|
530 |
|
|
531 |
memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
|
|
532 |
|
|
533 |
s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
|
|
534 |
s->usbsts = USBSTS_HALT;
|
|
535 |
|
|
536 |
s->astate = EST_INACTIVE;
|
|
537 |
s->pstate = EST_INACTIVE;
|
|
538 |
s->async_complete = 0;
|
|
539 |
s->isoch_pause = -1;
|
|
540 |
s->attach_poll_counter = 0;
|
|
541 |
|
|
542 |
for(i = 0; i < NB_PORTS; i++) {
|
|
543 |
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
|
|
544 |
|
|
545 |
if (s->ports[i].dev) {
|
|
546 |
usb_attach(&s->ports[i], s->ports[i].dev);
|
|
547 |
}
|
|
548 |
}
|
|
549 |
}
|
|
550 |
|
|
551 |
static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
|
|
552 |
{
|
|
553 |
EHCIState *s = ptr;
|
|
554 |
uint32_t val;
|
|
555 |
|
|
556 |
val = s->mmio[addr];
|
|
557 |
|
|
558 |
return val;
|
|
559 |
}
|
|
560 |
|
|
561 |
static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
|
|
562 |
{
|
|
563 |
EHCIState *s = ptr;
|
|
564 |
uint32_t val;
|
|
565 |
|
|
566 |
val = s->mmio[addr] | (s->mmio[addr+1] << 8);
|
|
567 |
|
|
568 |
return val;
|
|
569 |
}
|
|
570 |
|
|
571 |
static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
|
|
572 |
{
|
|
573 |
EHCIState *s = ptr;
|
|
574 |
uint32_t val;
|
|
575 |
|
|
576 |
val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
|
|
577 |
(s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
|
|
578 |
|
|
579 |
return val;
|
|
580 |
}
|
|
581 |
|
|
582 |
static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
|
|
583 |
{
|
|
584 |
fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
|
|
585 |
exit(1);
|
|
586 |
}
|
|
587 |
|
|
588 |
static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
|
|
589 |
{
|
|
590 |
fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
|
|
591 |
exit(1);
|
|
592 |
}
|
|
593 |
|
|
594 |
static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
|
|
595 |
{
|
|
596 |
uint32_t *portsc = &s->portsc[port];
|
|
597 |
int rwc;
|
|
598 |
USBDevice *dev = s->ports[port].dev;
|
|
599 |
|
|
600 |
DPRINTF("port_status_write: "
|
|
601 |
"PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",
|
|
602 |
port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);
|
|
603 |
|
|
604 |
rwc = val & PORTSC_RWC_MASK;
|
|
605 |
val &= PORTSC_RO_MASK;
|
|
606 |
|
|
607 |
// handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
|
|
608 |
|
|
609 |
*portsc &= ~rwc;
|
|
610 |
|
|
611 |
if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
|
|
612 |
DPRINTF("port_status_write: USBTRAN Port %d reset begin\n", port);
|
|
613 |
}
|
|
614 |
|
|
615 |
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
|
|
616 |
DPRINTF("port_status_write: USBTRAN Port %d reset done\n", port);
|
|
617 |
usb_attach(&s->ports[port], dev);
|
|
618 |
|
|
619 |
// TODO how to handle reset of ports with no device
|
|
620 |
if (dev) {
|
|
621 |
usb_send_msg(dev, USB_MSG_RESET);
|
|
622 |
}
|
|
623 |
|
|
624 |
if (s->ports[port].dev) {
|
|
625 |
DPRINTF("port_status_write: "
|
|
626 |
"Device was connected before reset, clearing CSC bit\n");
|
|
627 |
*portsc &= ~PORTSC_CSC;
|
|
628 |
}
|
|
629 |
|
|
630 |
/* Table 2.16 Set the enable bit(and enable bit change) to indicate
|
|
631 |
* to SW that this port has a high speed device attached
|
|
632 |
*
|
|
633 |
* TODO - when to disable?
|
|
634 |
*/
|
|
635 |
val |= PORTSC_PED;
|
|
636 |
val |= PORTSC_PEDC;
|
|
637 |
}
|
|
638 |
|
|
639 |
*portsc &= ~PORTSC_RO_MASK;
|
|
640 |
*portsc |= val;
|
|
641 |
DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);
|
|
642 |
}
|
|
643 |
|
|
644 |
static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
|
|
645 |
{
|
|
646 |
EHCIState *s = ptr;
|
|
647 |
int i;
|
|
648 |
#if EHCI_DEBUG
|
|
649 |
const char *str;
|
|
650 |
#endif
|
|
651 |
|
|
652 |
/* Only aligned reads are allowed on OHCI */
|
|
653 |
if (addr & 3) {
|
|
654 |
fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
|
|
655 |
TARGET_FMT_plx "\n", addr);
|
|
656 |
return;
|
|
657 |
}
|
|
658 |
|
|
659 |
if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
|
|
660 |
handle_port_status_write(s, (addr-PORTSC)/4, val);
|
|
661 |
return;
|
|
662 |
}
|
|
663 |
|
|
664 |
if (addr < OPREGBASE) {
|
|
665 |
fprintf(stderr, "usb-ehci: write attempt to read-only register"
|
|
666 |
TARGET_FMT_plx "\n", addr);
|
|
667 |
return;
|
|
668 |
}
|
|
669 |
|
|
670 |
|
|
671 |
/* Do any register specific pre-write processing here. */
|
|
672 |
#if EHCI_DEBUG
|
|
673 |
str = addr2str((unsigned) addr);
|
|
674 |
#endif
|
|
675 |
switch(addr) {
|
|
676 |
case USBCMD:
|
|
677 |
DPRINTF("ehci_mem_writel: USBCMD val=0x%08X, current cmd=0x%08X\n",
|
|
678 |
val, s->usbcmd);
|
|
679 |
|
|
680 |
if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
|
|
681 |
DPRINTF("ehci_mem_writel: %s run, clear halt\n", str);
|
|
682 |
qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
|
|
683 |
SET_LAST_RUN_CLOCK(s);
|
|
684 |
s->usbsts &= ~USBSTS_HALT;
|
|
685 |
}
|
|
686 |
|
|
687 |
if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
|
|
688 |
DPRINTF(" ** STOP **\n");
|
|
689 |
qemu_del_timer(s->frame_timer);
|
|
690 |
// TODO - should finish out some stuff before setting halt
|
|
691 |
s->usbsts |= USBSTS_HALT;
|
|
692 |
}
|
|
693 |
|
|
694 |
if (val & USBCMD_HCRESET) {
|
|
695 |
DPRINTF("ehci_mem_writel: %s run, resetting\n", str);
|
|
696 |
ehci_reset(s);
|
|
697 |
val &= ~USBCMD_HCRESET;
|
|
698 |
}
|
|
699 |
|
|
700 |
/* not supporting dynamic frame list size at the moment */
|
|
701 |
if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
|
|
702 |
fprintf(stderr, "attempt to set frame list size -- value %d\n",
|
|
703 |
val & USBCMD_FLS);
|
|
704 |
val &= ~USBCMD_FLS;
|
|
705 |
}
|
|
706 |
#if EHCI_DEBUG
|
|
707 |
if ((val & USBCMD_PSE) && !(s->usbcmd & USBCMD_PSE)) {
|
|
708 |
DPRINTF("periodic scheduling enabled\n");
|
|
709 |
}
|
|
710 |
if (!(val & USBCMD_PSE) && (s->usbcmd & USBCMD_PSE)) {
|
|
711 |
DPRINTF("periodic scheduling disabled\n");
|
|
712 |
}
|
|
713 |
if ((val & USBCMD_ASE) && !(s->usbcmd & USBCMD_ASE)) {
|
|
714 |
DPRINTF("asynchronous scheduling enabled\n");
|
|
715 |
}
|
|
716 |
if (!(val & USBCMD_ASE) && (s->usbcmd & USBCMD_ASE)) {
|
|
717 |
DPRINTF("asynchronous scheduling disabled\n");
|
|
718 |
}
|
|
719 |
if ((val & USBCMD_IAAD) && !(s->usbcmd & USBCMD_IAAD)) {
|
|
720 |
DPRINTF("doorbell request received\n");
|
|
721 |
}
|
|
722 |
if ((val & USBCMD_LHCR) && !(s->usbcmd & USBCMD_LHCR)) {
|
|
723 |
DPRINTF("light host controller reset received\n");
|
|
724 |
}
|
|
725 |
if ((val & USBCMD_ITC) != (s->usbcmd & USBCMD_ITC)) {
|
|
726 |
DPRINTF("interrupt threshold control set to %x\n",
|
|
727 |
(val & USBCMD_ITC)>>USBCMD_ITC_SH);
|
|
728 |
}
|
|
729 |
#endif
|
|
730 |
break;
|
|
731 |
|
|
732 |
|
|
733 |
case USBSTS:
|
|
734 |
val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
|
|
735 |
DPRINTF("ehci_mem_writel: %s RWC set to 0x%08X\n", str, val);
|
|
736 |
|
|
737 |
val = (s->usbsts &= ~val); // bits 0 thru 5 are R/WC
|
|
738 |
|
|
739 |
DPRINTF("ehci_mem_writel: %s updating interrupt condition\n", str);
|
|
740 |
ehci_set_interrupt(s, 0);
|
|
741 |
break;
|
|
742 |
|
|
743 |
|
|
744 |
case USBINTR:
|
|
745 |
val &= USBINTR_MASK;
|
|
746 |
DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
|
|
747 |
break;
|
|
748 |
|
|
749 |
case FRINDEX:
|
|
750 |
s->sofv = val >> 3;
|
|
751 |
DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
|
|
752 |
break;
|
|
753 |
|
|
754 |
case CONFIGFLAG:
|
|
755 |
DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
|
|
756 |
val &= 0x1;
|
|
757 |
if (val) {
|
|
758 |
for(i = 0; i < NB_PORTS; i++)
|
|
759 |
s->portsc[i] &= ~PORTSC_POWNER;
|
|
760 |
}
|
|
761 |
break;
|
|
762 |
|
|
763 |
case PERIODICLISTBASE:
|
|
764 |
if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
|
|
765 |
fprintf(stderr,
|
|
766 |
"ehci: PERIODIC list base register set while periodic schedule\n"
|
|
767 |
" is enabled and HC is enabled\n");
|
|
768 |
}
|
|
769 |
DPRINTF("ehci_mem_writel: P-LIST BASE set to 0x%08X\n", val);
|
|
770 |
break;
|
|
771 |
|
|
772 |
case ASYNCLISTADDR:
|
|
773 |
if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
|
|
774 |
fprintf(stderr,
|
|
775 |
"ehci: ASYNC list address register set while async schedule\n"
|
|
776 |
" is enabled and HC is enabled\n");
|
|
777 |
}
|
|
778 |
DPRINTF("ehci_mem_writel: A-LIST ADDR set to 0x%08X\n", val);
|
|
779 |
break;
|
|
780 |
}
|
|
781 |
|
|
782 |
*(uint32_t *)(&s->mmio[addr]) = val;
|
|
783 |
}
|
|
784 |
|
|
785 |
|
|
786 |
// TODO : Put in common header file, duplication from usb-ohci.c
|
|
787 |
|
|
788 |
/* Get an array of dwords from main memory */
|
|
789 |
static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
|
|
790 |
{
|
|
791 |
int i;
|
|
792 |
|
|
793 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
|
794 |
cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
|
|
795 |
*buf = le32_to_cpu(*buf);
|
|
796 |
}
|
|
797 |
|
|
798 |
return 1;
|
|
799 |
}
|
|
800 |
|
|
801 |
/* Put an array of dwords in to main memory */
|
|
802 |
static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
|
|
803 |
{
|
|
804 |
int i;
|
|
805 |
|
|
806 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
|
|
807 |
uint32_t tmp = cpu_to_le32(*buf);
|
|
808 |
cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
|
|
809 |
}
|
|
810 |
|
|
811 |
return 1;
|
|
812 |
}
|
|
813 |
|
|
814 |
// 4.10.2
|
|
815 |
|
|
816 |
static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
|
|
817 |
{
|
|
818 |
int i;
|
|
819 |
int dtoggle;
|
|
820 |
int ping;
|
|
821 |
int eps;
|
|
822 |
int reload;
|
|
823 |
|
|
824 |
// remember values in fields to preserve in qh after overlay
|
|
825 |
|
|
826 |
dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
|
|
827 |
ping = qh->token & QTD_TOKEN_PING;
|
|
828 |
|
|
829 |
DPRINTF("setting qh.current from %08X to 0x%08X\n", qh->current_qtd,
|
|
830 |
ehci->qtdaddr);
|
|
831 |
qh->current_qtd = ehci->qtdaddr;
|
|
832 |
qh->next_qtd = qtd->next;
|
|
833 |
qh->altnext_qtd = qtd->altnext;
|
|
834 |
qh->token = qtd->token;
|
|
835 |
|
|
836 |
|
|
837 |
eps = get_field(qh->epchar, QH_EPCHAR_EPS);
|
|
838 |
if (eps == EHCI_QH_EPS_HIGH) {
|
|
839 |
qh->token &= ~QTD_TOKEN_PING;
|
|
840 |
qh->token |= ping;
|
|
841 |
}
|
|
842 |
|
|
843 |
reload = get_field(qh->epchar, QH_EPCHAR_RL);
|
|
844 |
set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
|
|
845 |
|
|
846 |
for (i = 0; i < 5; i++) {
|
|
847 |
qh->bufptr[i] = qtd->bufptr[i];
|
|
848 |
}
|
|
849 |
|
|
850 |
if (!(qh->epchar & QH_EPCHAR_DTC)) {
|
|
851 |
// preserve QH DT bit
|
|
852 |
qh->token &= ~QTD_TOKEN_DTOGGLE;
|
|
853 |
qh->token |= dtoggle;
|
|
854 |
}
|
|
855 |
|
|
856 |
qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
|
|
857 |
qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
|
|
858 |
|
|
859 |
put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
|
|
860 |
|
|
861 |
return 0;
|
|
862 |
}
|
|
863 |
|
|
864 |
static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
|
|
865 |
{
|
|
866 |
int bufpos = 0;
|
|
867 |
int cpage, offset;
|
|
868 |
uint32_t head;
|
|
869 |
uint32_t tail;
|
|
870 |
|
|
871 |
|
|
872 |
if (!bytes) {
|
|
873 |
return 0;
|
|
874 |
}
|
|
875 |
|
|
876 |
cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
|
|
877 |
if (cpage > 4) {
|
|
878 |
fprintf(stderr, "cpage out of range (%d)\n", cpage);
|
|
879 |
return USB_RET_PROCERR;
|
|
880 |
}
|
|
881 |
|
|
882 |
offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
|
|
883 |
DPRINTF("ehci_buffer_rw: %sing %d bytes %08x cpage %d offset %d\n",
|
|
884 |
rw ? "writ" : "read", bytes, qh->bufptr[0], cpage, offset);
|
|
885 |
|
|
886 |
do {
|
|
887 |
/* start and end of this page */
|
|
888 |
head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
|
|
889 |
tail = head + ~QTD_BUFPTR_MASK + 1;
|
|
890 |
/* add offset into page */
|
|
891 |
head |= offset;
|
|
892 |
|
|
893 |
if (bytes <= (tail - head)) {
|
|
894 |
tail = head + bytes;
|
|
895 |
}
|
|
896 |
|
|
897 |
DPRINTF("DATA %s cpage:%d head:%08X tail:%08X target:%08X\n",
|
|
898 |
rw ? "WRITE" : "READ ", cpage, head, tail, bufpos);
|
|
899 |
|
|
900 |
cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
|
|
901 |
|
|
902 |
bufpos += (tail - head);
|
|
903 |
bytes -= (tail - head);
|
|
904 |
|
|
905 |
if (bytes > 0) {
|
|
906 |
cpage++;
|
|
907 |
offset = 0;
|
|
908 |
}
|
|
909 |
} while (bytes > 0);
|
|
910 |
|
|
911 |
/* save cpage */
|
|
912 |
set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
|
|
913 |
|
|
914 |
/* save offset into cpage */
|
|
915 |
offset = tail - head;
|
|
916 |
qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
|
|
917 |
qh->bufptr[0] |= offset;
|
|
918 |
|
|
919 |
return 0;
|
|
920 |
}
|
|
921 |
|
|
922 |
static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
|
|
923 |
{
|
|
924 |
EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
|
|
925 |
|
|
926 |
DPRINTF("Async packet complete\n");
|
|
927 |
ehci->async_complete = 1;
|
|
928 |
ehci->exec_status = packet->len;
|
|
929 |
}
|
|
930 |
|
|
931 |
static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
|
|
932 |
{
|
|
933 |
int c_err, reload;
|
|
934 |
|
|
935 |
if (ret == USB_RET_ASYNC && !ehci->async_complete) {
|
|
936 |
DPRINTF("not done yet\n");
|
|
937 |
return ret;
|
|
938 |
}
|
|
939 |
|
|
940 |
ehci->async_complete = 0;
|
|
941 |
|
|
942 |
DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
|
|
943 |
ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
|
|
944 |
|
|
945 |
if (ret < 0) {
|
|
946 |
err:
|
|
947 |
/* TO-DO: put this is in a function that can be invoked below as well */
|
|
948 |
c_err = get_field(qh->token, QTD_TOKEN_CERR);
|
|
949 |
c_err--;
|
|
950 |
set_field(&qh->token, c_err, QTD_TOKEN_CERR);
|
|
951 |
|
|
952 |
switch(ret) {
|
|
953 |
case USB_RET_NODEV:
|
|
954 |
fprintf(stderr, "USB no device\n");
|
|
955 |
break;
|
|
956 |
case USB_RET_STALL:
|
|
957 |
fprintf(stderr, "USB stall\n");
|
|
958 |
qh->token |= QTD_TOKEN_HALT;
|
|
959 |
ehci_record_interrupt(ehci, USBSTS_ERRINT);
|
|
960 |
break;
|
|
961 |
case USB_RET_NAK:
|
|
962 |
/* 4.10.3 */
|
|
963 |
reload = get_field(qh->epchar, QH_EPCHAR_RL);
|
|
964 |
if ((ehci->pid == USB_TOKEN_IN) && reload) {
|
|
965 |
int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
|
|
966 |
nakcnt--;
|
|
967 |
set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
|
|
968 |
} else if (!reload) {
|
|
969 |
return USB_RET_NAK;
|
|
970 |
}
|
|
971 |
break;
|
|
972 |
case USB_RET_BABBLE:
|
|
973 |
fprintf(stderr, "USB babble TODO\n");
|
|
974 |
qh->token |= QTD_TOKEN_BABBLE;
|
|
975 |
ehci_record_interrupt(ehci, USBSTS_ERRINT);
|
|
976 |
break;
|
|
977 |
default:
|
|
978 |
fprintf(stderr, "USB invalid response %d to handle\n", ret);
|
|
979 |
/* TO-DO: transaction error */
|
|
980 |
ret = USB_RET_PROCERR;
|
|
981 |
break;
|
|
982 |
}
|
|
983 |
} else {
|
|
984 |
// DPRINTF("Short packet condition\n");
|
|
985 |
// TODO check 4.12 for splits
|
|
986 |
|
|
987 |
if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
|
|
988 |
ret = USB_RET_BABBLE;
|
|
989 |
goto err;
|
|
990 |
}
|
|
991 |
|
|
992 |
if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
|
|
993 |
if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
|
|
994 |
return USB_RET_PROCERR;
|
|
995 |
}
|
|
996 |
ehci->tbytes -= ret;
|
|
997 |
} else {
|
|
998 |
ehci->tbytes = 0;
|
|
999 |
}
|
|
1000 |
|
|
1001 |
DPRINTF("updating tbytes to %d\n", ehci->tbytes);
|
|
1002 |
set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
|
|
1003 |
}
|
|
1004 |
|
|
1005 |
qh->token ^= QTD_TOKEN_DTOGGLE;
|
|
1006 |
qh->token &= ~QTD_TOKEN_ACTIVE;
|
|
1007 |
|
|
1008 |
if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
|
|
1009 |
ehci_record_interrupt(ehci, USBSTS_INT);
|
|
1010 |
}
|
|
1011 |
|
|
1012 |
return ret;
|
|
1013 |
}
|
|
1014 |
|
|
1015 |
// 4.10.3
|
|
1016 |
|
|
1017 |
static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
|
|
1018 |
{
|
|
1019 |
USBPort *port;
|
|
1020 |
USBDevice *dev;
|
|
1021 |
int ret;
|
|
1022 |
int i;
|
|
1023 |
int endp;
|
|
1024 |
int devadr;
|
|
1025 |
|
|
1026 |
if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
|
|
1027 |
fprintf(stderr, "Attempting to execute inactive QH\n");
|
|
1028 |
return USB_RET_PROCERR;
|
|
1029 |
}
|
|
1030 |
|
|
1031 |
ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
|
|
1032 |
if (ehci->tbytes > BUFF_SIZE) {
|
|
1033 |
fprintf(stderr, "Request for more bytes than allowed\n");
|
|
1034 |
return USB_RET_PROCERR;
|
|
1035 |
}
|
|
1036 |
|
|
1037 |
ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
|
|
1038 |
switch(ehci->pid) {
|
|
1039 |
case 0: ehci->pid = USB_TOKEN_OUT; break;
|
|
1040 |
case 1: ehci->pid = USB_TOKEN_IN; break;
|
|
1041 |
case 2: ehci->pid = USB_TOKEN_SETUP; break;
|
|
1042 |
default: fprintf(stderr, "bad token\n"); break;
|
|
1043 |
}
|
|
1044 |
|
|
1045 |
if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
|
|
1046 |
(ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
|
|
1047 |
return USB_RET_PROCERR;
|
|
1048 |
}
|
|
1049 |
|
|
1050 |
endp = get_field(qh->epchar, QH_EPCHAR_EP);
|
|
1051 |
devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
|
|
1052 |
|
|
1053 |
ret = USB_RET_NODEV;
|
|
1054 |
|
|
1055 |
// TO-DO: associating device with ehci port
|
|
1056 |
for(i = 0; i < NB_PORTS; i++) {
|
|
1057 |
port = &ehci->ports[i];
|
|
1058 |
dev = port->dev;
|
|
1059 |
|
|
1060 |
// TODO sometime we will also need to check if we are the port owner
|
|
1061 |
|
|
1062 |
if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
|
|
1063 |
DPRINTF("Port %d, no exec, not connected(%08X)\n",
|
|
1064 |
i, ehci->portsc[i]);
|
|
1065 |
continue;
|
|
1066 |
}
|
|
1067 |
|
|
1068 |
ehci->usb_packet.pid = ehci->pid;
|
|
1069 |
ehci->usb_packet.devaddr = devadr;
|
|
1070 |
ehci->usb_packet.devep = endp;
|
|
1071 |
ehci->usb_packet.data = ehci->buffer;
|
|
1072 |
ehci->usb_packet.len = ehci->tbytes;
|
|
1073 |
|
|
1074 |
ret = usb_handle_packet(dev, &ehci->usb_packet);
|
|
1075 |
|
|
1076 |
DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
|
|
1077 |
ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
|
|
1078 |
ehci->usb_packet.len, ehci->tbytes, endp, ret);
|
|
1079 |
|
|
1080 |
if (ret != USB_RET_NODEV) {
|
|
1081 |
break;
|
|
1082 |
}
|
|
1083 |
}
|
|
1084 |
|
|
1085 |
if (ret > BUFF_SIZE) {
|
|
1086 |
fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
|
|
1087 |
return USB_RET_PROCERR;
|
|
1088 |
}
|
|
1089 |
|
|
1090 |
if (ret == USB_RET_ASYNC) {
|
|
1091 |
ehci->async_complete = 0;
|
|
1092 |
}
|
|
1093 |
|
|
1094 |
return ret;
|
|
1095 |
}
|
|
1096 |
|
|
1097 |
/* 4.7.2
|
|
1098 |
*/
|
|
1099 |
|
|
1100 |
static int ehci_process_itd(EHCIState *ehci,
|
|
1101 |
EHCIitd *itd)
|
|
1102 |
{
|
|
1103 |
USBPort *port;
|
|
1104 |
USBDevice *dev;
|
|
1105 |
int ret;
|
|
1106 |
int i, j;
|
|
1107 |
int ptr;
|
|
1108 |
int pid;
|
|
1109 |
int pg;
|
|
1110 |
int len;
|
|
1111 |
int dir;
|
|
1112 |
int devadr;
|
|
1113 |
int endp;
|
|
1114 |
int maxpkt;
|
|
1115 |
|
|
1116 |
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
|
|
1117 |
devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
|
|
1118 |
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
|
|
1119 |
maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
|
|
1120 |
|
|
1121 |
for(i = 0; i < 8; i++) {
|
|
1122 |
if (itd->transact[i] & ITD_XACT_ACTIVE) {
|
|
1123 |
DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
|
|
1124 |
ehci->frindex >> 3, i);
|
|
1125 |
|
|
1126 |
pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
|
|
1127 |
ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
|
|
1128 |
(itd->transact[i] & ITD_XACT_OFFSET_MASK);
|
|
1129 |
len = get_field(itd->transact[i], ITD_XACT_LENGTH);
|
|
1130 |
|
|
1131 |
if (len > BUFF_SIZE) {
|
|
1132 |
return USB_RET_PROCERR;
|
|
1133 |
}
|
|
1134 |
|
|
1135 |
DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
|
|
1136 |
|
|
1137 |
if (!dir) {
|
|
1138 |
cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
|
|
1139 |
pid = USB_TOKEN_OUT;
|
|
1140 |
} else
|
|
1141 |
pid = USB_TOKEN_IN;
|
|
1142 |
|
|
1143 |
ret = USB_RET_NODEV;
|
|
1144 |
|
|
1145 |
for (j = 0; j < NB_PORTS; j++) {
|
|
1146 |
port = &ehci->ports[j];
|
|
1147 |
dev = port->dev;
|
|
1148 |
|
|
1149 |
// TODO sometime we will also need to check if we are the port owner
|
|
1150 |
|
|
1151 |
if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
|
|
1152 |
DPRINTF("Port %d, no exec, not connected(%08X)\n",
|
|
1153 |
j, ehci->portsc[j]);
|
|
1154 |
continue;
|
|
1155 |
}
|
|
1156 |
|
|
1157 |
ehci->usb_packet.pid = ehci->pid;
|
|
1158 |
ehci->usb_packet.devaddr = devadr;
|
|
1159 |
ehci->usb_packet.devep = endp;
|
|
1160 |
ehci->usb_packet.data = ehci->buffer;
|
|
1161 |
ehci->usb_packet.len = len;
|
|
1162 |
|
|
1163 |
DPRINTF("calling usb_handle_packet\n");
|
|
1164 |
ret = usb_handle_packet(dev, &ehci->usb_packet);
|
|
1165 |
|
|
1166 |
if (ret != USB_RET_NODEV) {
|
|
1167 |
break;
|
|
1168 |
}
|
|
1169 |
}
|
|
1170 |
|
|
1171 |
/* In isoch, there is no facility to indicate a NAK so let's
|
|
1172 |
* instead just complete a zero-byte transaction. Setting
|
|
1173 |
* DBERR seems too draconian.
|
|
1174 |
*/
|
|
1175 |
|
|
1176 |
if (ret == USB_RET_NAK) {
|
|
1177 |
if (ehci->isoch_pause > 0) {
|
|
1178 |
DPRINTF("ISOCH: received a NAK but paused so returning\n");
|
|
1179 |
ehci->isoch_pause--;
|
|
1180 |
return 0;
|
|
1181 |
} else if (ehci->isoch_pause == -1) {
|
|
1182 |
DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
|
|
1183 |
// Pause frindex for up to 50 msec waiting for data from
|
|
1184 |
// remote
|
|
1185 |
ehci->isoch_pause = 50;
|
|
1186 |
return 0;
|
|
1187 |
} else {
|
|
1188 |
DPRINTF("ISOCH: isoch pause timeout! return 0\n");
|
|
1189 |
ret = 0;
|
|
1190 |
}
|
|
1191 |
} else {
|
|
1192 |
DPRINTF("ISOCH: received ACK, clearing pause\n");
|
|
1193 |
ehci->isoch_pause = -1;
|
|
1194 |
}
|
|
1195 |
|
|
1196 |
if (ret >= 0) {
|
|
1197 |
itd->transact[i] &= ~ITD_XACT_ACTIVE;
|
|
1198 |
|
|
1199 |
if (itd->transact[i] & ITD_XACT_IOC) {
|
|
1200 |
ehci_record_interrupt(ehci, USBSTS_INT);
|
|
1201 |
}
|
|
1202 |
}
|
|
1203 |
|
|
1204 |
if (ret >= 0 && dir) {
|
|
1205 |
cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
|
|
1206 |
|
|
1207 |
if (ret != len) {
|
|
1208 |
DPRINTF("ISOCH IN expected %d, got %d\n",
|
|
1209 |
len, ret);
|
|
1210 |
set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
|
|
1211 |
}
|
|
1212 |
}
|
|
1213 |
}
|
|
1214 |
}
|
|
1215 |
return 0;
|
|
1216 |
}
|
|
1217 |
|
|
1218 |
/* This state is the entry point for asynchronous schedule
|
|
1219 |
* processing. Entry here consitutes a EHCI start event state (4.8.5)
|
|
1220 |
*/
|
|
1221 |
static int ehci_state_waitlisthead(EHCIState *ehci, int async, int *state)
|
|
1222 |
{
|
|
1223 |
EHCIqh *qh = &ehci->qh;
|
|
1224 |
int i = 0;
|
|
1225 |
int again = 0;
|
|
1226 |
uint32_t entry = ehci->asynclistaddr;
|
|
1227 |
|
|
1228 |
/* set reclamation flag at start event (4.8.6) */
|
|
1229 |
if (async) {
|
|
1230 |
ehci->usbsts |= USBSTS_REC;
|
|
1231 |
}
|
|
1232 |
|
|
1233 |
/* Find the head of the list (4.9.1.1) */
|
|
1234 |
for(i = 0; i < MAX_QH; i++) {
|
|
1235 |
get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
|
|
1236 |
|
|
1237 |
if (qh->epchar & QH_EPCHAR_H) {
|
|
1238 |
DPRINTF_ST("WAITLISTHEAD: QH %08X is the HEAD of the list\n",
|
|
1239 |
entry);
|
|
1240 |
if (async) {
|
|
1241 |
entry |= (NLPTR_TYPE_QH << 1);
|
|
1242 |
}
|
|
1243 |
|
|
1244 |
ehci->fetch_addr = entry;
|
|
1245 |
*state = EST_FETCHENTRY;
|
|
1246 |
again = 1;
|
|
1247 |
goto out;
|
|
1248 |
}
|
|
1249 |
|
|
1250 |
DPRINTF_ST("WAITLISTHEAD: QH %08X is NOT the HEAD of the list\n",
|
|
1251 |
entry);
|
|
1252 |
entry = qh->next;
|
|
1253 |
if (entry == ehci->asynclistaddr) {
|
|
1254 |
DPRINTF("WAITLISTHEAD: reached beginning of QH list\n");
|
|
1255 |
break;
|
|
1256 |
}
|
|
1257 |
}
|
|
1258 |
|
|
1259 |
/* no head found for list. */
|
|
1260 |
|
|
1261 |
*state = EST_ACTIVE;
|
|
1262 |
|
|
1263 |
out:
|
|
1264 |
return again;
|
|
1265 |
}
|
|
1266 |
|
|
1267 |
|
|
1268 |
/* This state is the entry point for periodic schedule processing as
|
|
1269 |
* well as being a continuation state for async processing.
|
|
1270 |
*/
|
|
1271 |
static int ehci_state_fetchentry(EHCIState *ehci, int async, int *state)
|
|
1272 |
{
|
|
1273 |
int again = 0;
|
|
1274 |
uint32_t entry = ehci->fetch_addr;
|
|
1275 |
|
|
1276 |
#if EHCI_DEBUG == 0
|
|
1277 |
if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
|
|
1278 |
if (async) {
|
|
1279 |
DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
|
|
1280 |
goto out;
|
|
1281 |
} else {
|
|
1282 |
DPRINTF("FETCHENTRY: WARNING "
|
|
1283 |
"- frame timer elapsed during periodic\n");
|
|
1284 |
}
|
|
1285 |
}
|
|
1286 |
#endif
|
|
1287 |
if (entry < 0x1000) {
|
|
1288 |
DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
|
|
1289 |
*state = EST_ACTIVE;
|
|
1290 |
goto out;
|
|
1291 |
}
|
|
1292 |
|
|
1293 |
/* section 4.8, only QH in async schedule */
|
|
1294 |
if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
|
|
1295 |
fprintf(stderr, "non queue head request in async schedule\n");
|
|
1296 |
return -1;
|
|
1297 |
}
|
|
1298 |
|
|
1299 |
switch (NLPTR_TYPE_GET(entry)) {
|
|
1300 |
case NLPTR_TYPE_QH:
|
|
1301 |
DPRINTF_ST("FETCHENTRY: entry %X is a Queue Head\n", entry);
|
|
1302 |
*state = EST_FETCHQH;
|
|
1303 |
ehci->qhaddr = entry;
|
|
1304 |
again = 1;
|
|
1305 |
break;
|
|
1306 |
|
|
1307 |
case NLPTR_TYPE_ITD:
|
|
1308 |
DPRINTF_ST("FETCHENTRY: entry %X is an ITD\n", entry);
|
|
1309 |
*state = EST_FETCHITD;
|
|
1310 |
ehci->itdaddr = entry;
|
|
1311 |
again = 1;
|
|
1312 |
break;
|
|
1313 |
|
|
1314 |
default:
|
|
1315 |
// TODO: handle siTD and FSTN types
|
|
1316 |
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
|
|
1317 |
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
|
|
1318 |
return -1;
|
|
1319 |
}
|
|
1320 |
|
|
1321 |
out:
|
|
1322 |
return again;
|
|
1323 |
}
|
|
1324 |
|
|
1325 |
static int ehci_state_fetchqh(EHCIState *ehci, int async, int *state)
|
|
1326 |
{
|
|
1327 |
EHCIqh *qh = &ehci->qh;
|
|
1328 |
int reload;
|
|
1329 |
int again = 0;
|
|
1330 |
|
|
1331 |
get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
|
|
1332 |
|
|
1333 |
if (async && (qh->epchar & QH_EPCHAR_H)) {
|
|
1334 |
|
|
1335 |
/* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
|
|
1336 |
if (ehci->usbsts & USBSTS_REC) {
|
|
1337 |
ehci->usbsts &= ~USBSTS_REC;
|
|
1338 |
} else {
|
|
1339 |
DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
|
|
1340 |
" - done processing\n", ehci->qhaddr);
|
|
1341 |
*state = EST_ACTIVE;
|
|
1342 |
goto out;
|
|
1343 |
}
|
|
1344 |
}
|
|
1345 |
|
|
1346 |
#if EHCI_DEBUG
|
|
1347 |
if (ehci->qhaddr != qh->next) {
|
|
1348 |
DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
|
|
1349 |
ehci->qhaddr,
|
|
1350 |
qh->epchar & QH_EPCHAR_H,
|
|
1351 |
qh->token & QTD_TOKEN_HALT,
|
|
1352 |
qh->token & QTD_TOKEN_ACTIVE,
|
|
1353 |
qh->next);
|
|
1354 |
}
|
|
1355 |
#endif
|
|
1356 |
|
|
1357 |
reload = get_field(qh->epchar, QH_EPCHAR_RL);
|
|
1358 |
if (reload) {
|
|
1359 |
DPRINTF_ST("FETCHQH: reloading nakcnt to %d\n", reload);
|
|
1360 |
set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
|
|
1361 |
}
|
|
1362 |
|
|
1363 |
if (qh->token & QTD_TOKEN_HALT) {
|
|
1364 |
DPRINTF_ST("FETCHQH: QH Halted, go horizontal\n");
|
|
1365 |
*state = EST_HORIZONTALQH;
|
|
1366 |
again = 1;
|
|
1367 |
|
|
1368 |
} else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
|
|
1369 |
DPRINTF_ST("FETCHQH: Active, !Halt, execute - fetch qTD\n");
|
|
1370 |
ehci->qtdaddr = qh->current_qtd;
|
|
1371 |
*state = EST_FETCHQTD;
|
|
1372 |
again = 1;
|
|
1373 |
|
|
1374 |
} else {
|
|
1375 |
/* EHCI spec version 1.0 Section 4.10.2 */
|
|
1376 |
DPRINTF_ST("FETCHQH: !Active, !Halt, advance queue\n");
|
|
1377 |
*state = EST_ADVANCEQUEUE;
|
|
1378 |
again = 1;
|
|
1379 |
}
|
|
1380 |
|
|
1381 |
out:
|
|
1382 |
return again;
|
|
1383 |
}
|
|
1384 |
|
|
1385 |
static int ehci_state_fetchitd(EHCIState *ehci, int async, int *state)
|
|
1386 |
{
|
|
1387 |
EHCIitd itd;
|
|
1388 |
|
|
1389 |
get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
|
|
1390 |
sizeof(EHCIitd) >> 2);
|
|
1391 |
DPRINTF_ST("FETCHITD: Fetched ITD at address %08X " "(next is %08X)\n",
|