Revision 9467d44c
| b/cpu-all.h | ||
|---|---|---|
| 692 | 692 |
void page_set_flags(target_ulong start, target_ulong end, int flags); |
| 693 | 693 |
void page_unprotect_range(target_ulong data, target_ulong data_size); |
| 694 | 694 |
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| 695 |
#define SINGLE_CPU_DEFINES |
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#ifdef SINGLE_CPU_DEFINES |
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#if defined(TARGET_I386) |
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#define CPUState CPUX86State |
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#define cpu_init cpu_x86_init |
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#define cpu_exec cpu_x86_exec |
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#define cpu_gen_code cpu_x86_gen_code |
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#define cpu_signal_handler cpu_x86_signal_handler |
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#elif defined(TARGET_ARM) |
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#define CPUState CPUARMState |
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#define cpu_init cpu_arm_init |
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#define cpu_exec cpu_arm_exec |
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#define cpu_gen_code cpu_arm_gen_code |
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#define cpu_signal_handler cpu_arm_signal_handler |
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#elif defined(TARGET_SPARC) |
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#define CPUState CPUSPARCState |
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#define cpu_init cpu_sparc_init |
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#define cpu_exec cpu_sparc_exec |
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#define cpu_gen_code cpu_sparc_gen_code |
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#define cpu_signal_handler cpu_sparc_signal_handler |
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#elif defined(TARGET_PPC) |
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#define CPUState CPUPPCState |
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#define cpu_init cpu_ppc_init |
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#define cpu_exec cpu_ppc_exec |
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#define cpu_gen_code cpu_ppc_gen_code |
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#define cpu_signal_handler cpu_ppc_signal_handler |
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#elif defined(TARGET_M68K) |
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#define CPUState CPUM68KState |
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#define cpu_init cpu_m68k_init |
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#define cpu_exec cpu_m68k_exec |
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#define cpu_gen_code cpu_m68k_gen_code |
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#define cpu_signal_handler cpu_m68k_signal_handler |
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#elif defined(TARGET_MIPS) |
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#define CPUState CPUMIPSState |
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#define cpu_init cpu_mips_init |
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#define cpu_exec cpu_mips_exec |
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#define cpu_gen_code cpu_mips_gen_code |
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#define cpu_signal_handler cpu_mips_signal_handler |
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#elif defined(TARGET_SH4) |
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#define CPUState CPUSH4State |
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#define cpu_init cpu_sh4_init |
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#define cpu_exec cpu_sh4_exec |
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#define cpu_gen_code cpu_sh4_gen_code |
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#define cpu_signal_handler cpu_sh4_signal_handler |
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#elif defined(TARGET_ALPHA) |
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#define CPUState CPUAlphaState |
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#define cpu_init cpu_alpha_init |
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#define cpu_exec cpu_alpha_exec |
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#define cpu_gen_code cpu_alpha_gen_code |
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#define cpu_signal_handler cpu_alpha_signal_handler |
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#else |
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#error unsupported target CPU |
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#endif |
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#endif /* SINGLE_CPU_DEFINES */ |
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CPUState *cpu_copy(CPUState *env); |
| 767 | 696 |
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| 768 | 697 |
void cpu_dump_state(CPUState *env, FILE *f, |
| b/target-alpha/cpu.h | ||
|---|---|---|
| 300 | 300 |
pal_handler_t *pal_handler; |
| 301 | 301 |
}; |
| 302 | 302 |
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#define CPUState CPUAlphaState |
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#define cpu_init cpu_alpha_init |
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#define cpu_exec cpu_alpha_exec |
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#define cpu_gen_code cpu_alpha_gen_code |
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#define cpu_signal_handler cpu_alpha_signal_handler |
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| 303 | 309 |
#include "cpu-all.h" |
| 304 | 310 |
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| 305 | 311 |
enum {
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| b/target-arm/cpu.h | ||
|---|---|---|
| 285 | 285 |
architecture revisions. Maybe an a configure option to disable them. */ |
| 286 | 286 |
#define TARGET_PAGE_BITS 10 |
| 287 | 287 |
#endif |
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#define CPUState CPUARMState |
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#define cpu_init cpu_arm_init |
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#define cpu_exec cpu_arm_exec |
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#define cpu_gen_code cpu_arm_gen_code |
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#define cpu_signal_handler cpu_arm_signal_handler |
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| 288 | 295 |
#include "cpu-all.h" |
| 289 | 296 |
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| 290 | 297 |
#endif |
| b/target-i386/cpu.h | ||
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| 661 | 661 |
#endif |
| 662 | 662 |
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| 663 | 663 |
#define TARGET_PAGE_BITS 12 |
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#define CPUState CPUX86State |
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#define cpu_init cpu_x86_init |
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#define cpu_exec cpu_x86_exec |
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#define cpu_gen_code cpu_x86_gen_code |
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#define cpu_signal_handler cpu_x86_signal_handler |
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| 664 | 671 |
#include "cpu-all.h" |
| 665 | 672 |
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| 666 | 673 |
#endif /* CPU_I386_H */ |
| b/target-m68k/cpu.h | ||
|---|---|---|
| 216 | 216 |
/* Smallest TLB entry size is 1k. */ |
| 217 | 217 |
#define TARGET_PAGE_BITS 10 |
| 218 | 218 |
#endif |
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#define CPUState CPUM68KState |
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#define cpu_init cpu_m68k_init |
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#define cpu_exec cpu_m68k_exec |
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#define cpu_gen_code cpu_m68k_gen_code |
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#define cpu_signal_handler cpu_m68k_signal_handler |
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| 219 | 226 |
#include "cpu-all.h" |
| 220 | 227 |
|
| 221 | 228 |
#endif |
| b/target-mips/cpu.h | ||
|---|---|---|
| 317 | 317 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 318 | 318 |
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def); |
| 319 | 319 |
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#define CPUState CPUMIPSState |
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#define cpu_init cpu_mips_init |
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#define cpu_exec cpu_mips_exec |
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#define cpu_gen_code cpu_mips_gen_code |
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#define cpu_signal_handler cpu_mips_signal_handler |
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| 320 | 326 |
#include "cpu-all.h" |
| 321 | 327 |
|
| 322 | 328 |
/* Memory access type : |
| b/target-ppc/cpu.h | ||
|---|---|---|
| 899 | 899 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
| 900 | 900 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
| 901 | 901 |
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#define CPUState CPUPPCState |
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#define cpu_init cpu_ppc_init |
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#define cpu_exec cpu_ppc_exec |
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#define cpu_gen_code cpu_ppc_gen_code |
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#define cpu_signal_handler cpu_ppc_signal_handler |
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| 902 | 908 |
#include "cpu-all.h" |
| 903 | 909 |
|
| 904 | 910 |
/*****************************************************************************/ |
| b/target-sh4/cpu.h | ||
|---|---|---|
| 126 | 126 |
|
| 127 | 127 |
#include "softfloat.h" |
| 128 | 128 |
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#define CPUState CPUSH4State |
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#define cpu_init cpu_sh4_init |
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#define cpu_exec cpu_sh4_exec |
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#define cpu_gen_code cpu_sh4_gen_code |
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#define cpu_signal_handler cpu_sh4_signal_handler |
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| 129 | 135 |
#include "cpu-all.h" |
| 130 | 136 |
|
| 131 | 137 |
/* Memory access type */ |
| b/target-sparc/cpu.h | ||
|---|---|---|
| 302 | 302 |
uint64_t do_tick_get_count(void *opaque); |
| 303 | 303 |
void do_tick_set_limit(void *opaque, uint64_t limit); |
| 304 | 304 |
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#define CPUState CPUSPARCState |
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#define cpu_init cpu_sparc_init |
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#define cpu_exec cpu_sparc_exec |
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#define cpu_gen_code cpu_sparc_gen_code |
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#define cpu_signal_handler cpu_sparc_signal_handler |
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| 305 | 311 |
#include "cpu-all.h" |
| 306 | 312 |
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| 307 | 313 |
#endif |
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