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/*
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 * QEMU generic PowerPC hardware System Emulator
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 *
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 * Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "ppc.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "nvram.h"
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#include "qemu-log.h"
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#include "loader.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
33

    
34
//#define PPC_DEBUG_IRQ
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//#define PPC_DEBUG_TB
36

    
37
#ifdef PPC_DEBUG_IRQ
38
#  define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39
#else
40
#  define LOG_IRQ(...) do { } while (0)
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#endif
42

    
43

    
44
#ifdef PPC_DEBUG_TB
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#  define LOG_TB(...) qemu_log(__VA_ARGS__)
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#else
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#  define LOG_TB(...) do { } while (0)
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#endif
49

    
50
static void cpu_ppc_tb_stop (CPUState *env);
51
static void cpu_ppc_tb_start (CPUState *env);
52

    
53
static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
54
{
55
    unsigned int old_pending = env->pending_interrupts;
56

    
57
    if (level) {
58
        env->pending_interrupts |= 1 << n_IRQ;
59
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
60
    } else {
61
        env->pending_interrupts &= ~(1 << n_IRQ);
62
        if (env->pending_interrupts == 0)
63
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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    }
65

    
66
    if (old_pending != env->pending_interrupts) {
67
#ifdef CONFIG_KVM
68
        kvmppc_set_interrupt(env, n_IRQ, level);
69
#endif
70
    }
71

    
72
    LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
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                "req %08x\n", __func__, env, n_IRQ, level,
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                env->pending_interrupts, env->interrupt_request);
75
}
76

    
77
/* PowerPC 6xx / 7xx internal IRQ controller */
78
static void ppc6xx_set_irq (void *opaque, int pin, int level)
79
{
80
    CPUState *env = opaque;
81
    int cur_level;
82

    
83
    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
84
                env, pin, level);
85
    cur_level = (env->irq_input_state >> pin) & 1;
86
    /* Don't generate spurious events */
87
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
88
        switch (pin) {
89
        case PPC6xx_INPUT_TBEN:
90
            /* Level sensitive - active high */
91
            LOG_IRQ("%s: %s the time base\n",
92
                        __func__, level ? "start" : "stop");
93
            if (level) {
94
                cpu_ppc_tb_start(env);
95
            } else {
96
                cpu_ppc_tb_stop(env);
97
            }
98
        case PPC6xx_INPUT_INT:
99
            /* Level sensitive - active high */
100
            LOG_IRQ("%s: set the external IRQ state to %d\n",
101
                        __func__, level);
102
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
103
            break;
104
        case PPC6xx_INPUT_SMI:
105
            /* Level sensitive - active high */
106
            LOG_IRQ("%s: set the SMI IRQ state to %d\n",
107
                        __func__, level);
108
            ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
109
            break;
110
        case PPC6xx_INPUT_MCP:
111
            /* Negative edge sensitive */
112
            /* XXX: TODO: actual reaction may depends on HID0 status
113
             *            603/604/740/750: check HID0[EMCP]
114
             */
115
            if (cur_level == 1 && level == 0) {
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                LOG_IRQ("%s: raise machine check state\n",
117
                            __func__);
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                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
119
            }
120
            break;
121
        case PPC6xx_INPUT_CKSTP_IN:
122
            /* Level sensitive - active low */
123
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */
124
            /* XXX: Note that the only way to restart the CPU is to reset it */
125
            if (level) {
126
                LOG_IRQ("%s: stop the CPU\n", __func__);
127
                env->halted = 1;
128
            }
129
            break;
130
        case PPC6xx_INPUT_HRESET:
131
            /* Level sensitive - active low */
132
            if (level) {
133
                LOG_IRQ("%s: reset the CPU\n", __func__);
134
                env->interrupt_request |= CPU_INTERRUPT_EXITTB;
135
                /* XXX: TOFIX */
136
#if 0
137
                cpu_reset(env);
138
#else
139
                qemu_system_reset_request();
140
#endif
141
            }
142
            break;
143
        case PPC6xx_INPUT_SRESET:
144
            LOG_IRQ("%s: set the RESET IRQ state to %d\n",
145
                        __func__, level);
146
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
147
            break;
148
        default:
149
            /* Unknown pin - do nothing */
150
            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
151
            return;
152
        }
153
        if (level)
154
            env->irq_input_state |= 1 << pin;
155
        else
156
            env->irq_input_state &= ~(1 << pin);
157
    }
158
}
159

    
160
void ppc6xx_irq_init (CPUState *env)
161
{
162
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
163
                                                  PPC6xx_INPUT_NB);
164
}
165

    
166
#if defined(TARGET_PPC64)
167
/* PowerPC 970 internal IRQ controller */
168
static void ppc970_set_irq (void *opaque, int pin, int level)
169
{
170
    CPUState *env = opaque;
171
    int cur_level;
172

    
173
    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
174
                env, pin, level);
175
    cur_level = (env->irq_input_state >> pin) & 1;
176
    /* Don't generate spurious events */
177
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
178
        switch (pin) {
179
        case PPC970_INPUT_INT:
180
            /* Level sensitive - active high */
181
            LOG_IRQ("%s: set the external IRQ state to %d\n",
182
                        __func__, level);
183
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
184
            break;
185
        case PPC970_INPUT_THINT:
186
            /* Level sensitive - active high */
187
            LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
188
                        level);
189
            ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
190
            break;
191
        case PPC970_INPUT_MCP:
192
            /* Negative edge sensitive */
193
            /* XXX: TODO: actual reaction may depends on HID0 status
194
             *            603/604/740/750: check HID0[EMCP]
195
             */
196
            if (cur_level == 1 && level == 0) {
197
                LOG_IRQ("%s: raise machine check state\n",
198
                            __func__);
199
                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
200
            }
201
            break;
202
        case PPC970_INPUT_CKSTP:
203
            /* Level sensitive - active low */
204
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */
205
            if (level) {
206
                LOG_IRQ("%s: stop the CPU\n", __func__);
207
                env->halted = 1;
208
            } else {
209
                LOG_IRQ("%s: restart the CPU\n", __func__);
210
                env->halted = 0;
211
                qemu_cpu_kick(env);
212
            }
213
            break;
214
        case PPC970_INPUT_HRESET:
215
            /* Level sensitive - active low */
216
            if (level) {
217
#if 0 // XXX: TOFIX
218
                LOG_IRQ("%s: reset the CPU\n", __func__);
219
                cpu_reset(env);
220
#endif
221
            }
222
            break;
223
        case PPC970_INPUT_SRESET:
224
            LOG_IRQ("%s: set the RESET IRQ state to %d\n",
225
                        __func__, level);
226
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
227
            break;
228
        case PPC970_INPUT_TBEN:
229
            LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
230
                        level);
231
            /* XXX: TODO */
232
            break;
233
        default:
234
            /* Unknown pin - do nothing */
235
            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
236
            return;
237
        }
238
        if (level)
239
            env->irq_input_state |= 1 << pin;
240
        else
241
            env->irq_input_state &= ~(1 << pin);
242
    }
243
}
244

    
245
void ppc970_irq_init (CPUState *env)
246
{
247
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
248
                                                  PPC970_INPUT_NB);
249
}
250
#endif /* defined(TARGET_PPC64) */
251

    
252
/* PowerPC 40x internal IRQ controller */
253
static void ppc40x_set_irq (void *opaque, int pin, int level)
254
{
255
    CPUState *env = opaque;
256
    int cur_level;
257

    
258
    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
259
                env, pin, level);
260
    cur_level = (env->irq_input_state >> pin) & 1;
261
    /* Don't generate spurious events */
262
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
263
        switch (pin) {
264
        case PPC40x_INPUT_RESET_SYS:
265
            if (level) {
266
                LOG_IRQ("%s: reset the PowerPC system\n",
267
                            __func__);
268
                ppc40x_system_reset(env);
269
            }
270
            break;
271
        case PPC40x_INPUT_RESET_CHIP:
272
            if (level) {
273
                LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
274
                ppc40x_chip_reset(env);
275
            }
276
            break;
277
        case PPC40x_INPUT_RESET_CORE:
278
            /* XXX: TODO: update DBSR[MRR] */
279
            if (level) {
280
                LOG_IRQ("%s: reset the PowerPC core\n", __func__);
281
                ppc40x_core_reset(env);
282
            }
283
            break;
284
        case PPC40x_INPUT_CINT:
285
            /* Level sensitive - active high */
286
            LOG_IRQ("%s: set the critical IRQ state to %d\n",
287
                        __func__, level);
288
            ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
289
            break;
290
        case PPC40x_INPUT_INT:
291
            /* Level sensitive - active high */
292
            LOG_IRQ("%s: set the external IRQ state to %d\n",
293
                        __func__, level);
294
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
295
            break;
296
        case PPC40x_INPUT_HALT:
297
            /* Level sensitive - active low */
298
            if (level) {
299
                LOG_IRQ("%s: stop the CPU\n", __func__);
300
                env->halted = 1;
301
            } else {
302
                LOG_IRQ("%s: restart the CPU\n", __func__);
303
                env->halted = 0;
304
                qemu_cpu_kick(env);
305
            }
306
            break;
307
        case PPC40x_INPUT_DEBUG:
308
            /* Level sensitive - active high */
309
            LOG_IRQ("%s: set the debug pin state to %d\n",
310
                        __func__, level);
311
            ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
312
            break;
313
        default:
314
            /* Unknown pin - do nothing */
315
            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
316
            return;
317
        }
318
        if (level)
319
            env->irq_input_state |= 1 << pin;
320
        else
321
            env->irq_input_state &= ~(1 << pin);
322
    }
323
}
324

    
325
void ppc40x_irq_init (CPUState *env)
326
{
327
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
328
                                                  env, PPC40x_INPUT_NB);
329
}
330

    
331
/* PowerPC E500 internal IRQ controller */
332
static void ppce500_set_irq (void *opaque, int pin, int level)
333
{
334
    CPUState *env = opaque;
335
    int cur_level;
336

    
337
    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
338
                env, pin, level);
339
    cur_level = (env->irq_input_state >> pin) & 1;
340
    /* Don't generate spurious events */
341
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
342
        switch (pin) {
343
        case PPCE500_INPUT_MCK:
344
            if (level) {
345
                LOG_IRQ("%s: reset the PowerPC system\n",
346
                            __func__);
347
                qemu_system_reset_request();
348
            }
349
            break;
350
        case PPCE500_INPUT_RESET_CORE:
351
            if (level) {
352
                LOG_IRQ("%s: reset the PowerPC core\n", __func__);
353
                ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
354
            }
355
            break;
356
        case PPCE500_INPUT_CINT:
357
            /* Level sensitive - active high */
358
            LOG_IRQ("%s: set the critical IRQ state to %d\n",
359
                        __func__, level);
360
            ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
361
            break;
362
        case PPCE500_INPUT_INT:
363
            /* Level sensitive - active high */
364
            LOG_IRQ("%s: set the core IRQ state to %d\n",
365
                        __func__, level);
366
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
367
            break;
368
        case PPCE500_INPUT_DEBUG:
369
            /* Level sensitive - active high */
370
            LOG_IRQ("%s: set the debug pin state to %d\n",
371
                        __func__, level);
372
            ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
373
            break;
374
        default:
375
            /* Unknown pin - do nothing */
376
            LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
377
            return;
378
        }
379
        if (level)
380
            env->irq_input_state |= 1 << pin;
381
        else
382
            env->irq_input_state &= ~(1 << pin);
383
    }
384
}
385

    
386
void ppce500_irq_init (CPUState *env)
387
{
388
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
389
                                        env, PPCE500_INPUT_NB);
390
}
391
/*****************************************************************************/
392
/* PowerPC time base and decrementer emulation */
393
struct ppc_tb_t {
394
    /* Time base management */
395
    int64_t  tb_offset;    /* Compensation                    */
396
    int64_t  atb_offset;   /* Compensation                    */
397
    uint32_t tb_freq;      /* TB frequency                    */
398
    /* Decrementer management */
399
    uint64_t decr_next;    /* Tick for next decr interrupt    */
400
    uint32_t decr_freq;    /* decrementer frequency           */
401
    struct QEMUTimer *decr_timer;
402
    /* Hypervisor decrementer management */
403
    uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
404
    struct QEMUTimer *hdecr_timer;
405
    uint64_t purr_load;
406
    uint64_t purr_start;
407
    void *opaque;
408
};
409

    
410
static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
411
                                      int64_t tb_offset)
412
{
413
    /* TB time in tb periods */
414
    return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
415
}
416

    
417
uint64_t cpu_ppc_load_tbl (CPUState *env)
418
{
419
    ppc_tb_t *tb_env = env->tb_env;
420
    uint64_t tb;
421

    
422
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
423
    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
424

    
425
    return tb;
426
}
427

    
428
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
429
{
430
    ppc_tb_t *tb_env = env->tb_env;
431
    uint64_t tb;
432

    
433
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
434
    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
435

    
436
    return tb >> 32;
437
}
438

    
439
uint32_t cpu_ppc_load_tbu (CPUState *env)
440
{
441
    return _cpu_ppc_load_tbu(env);
442
}
443

    
444
static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
445
                                    int64_t *tb_offsetp, uint64_t value)
446
{
447
    *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
448
    LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
449
                __func__, value, *tb_offsetp);
450
}
451

    
452
void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
453
{
454
    ppc_tb_t *tb_env = env->tb_env;
455
    uint64_t tb;
456

    
457
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
458
    tb &= 0xFFFFFFFF00000000ULL;
459
    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
460
                     &tb_env->tb_offset, tb | (uint64_t)value);
461
}
462

    
463
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
464
{
465
    ppc_tb_t *tb_env = env->tb_env;
466
    uint64_t tb;
467

    
468
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
469
    tb &= 0x00000000FFFFFFFFULL;
470
    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
471
                     &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
472
}
473

    
474
void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
475
{
476
    _cpu_ppc_store_tbu(env, value);
477
}
478

    
479
uint64_t cpu_ppc_load_atbl (CPUState *env)
480
{
481
    ppc_tb_t *tb_env = env->tb_env;
482
    uint64_t tb;
483

    
484
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
485
    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
486

    
487
    return tb;
488
}
489

    
490
uint32_t cpu_ppc_load_atbu (CPUState *env)
491
{
492
    ppc_tb_t *tb_env = env->tb_env;
493
    uint64_t tb;
494

    
495
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
496
    LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
497

    
498
    return tb >> 32;
499
}
500

    
501
void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
502
{
503
    ppc_tb_t *tb_env = env->tb_env;
504
    uint64_t tb;
505

    
506
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
507
    tb &= 0xFFFFFFFF00000000ULL;
508
    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
509
                     &tb_env->atb_offset, tb | (uint64_t)value);
510
}
511

    
512
void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
513
{
514
    ppc_tb_t *tb_env = env->tb_env;
515
    uint64_t tb;
516

    
517
    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
518
    tb &= 0x00000000FFFFFFFFULL;
519
    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),
520
                     &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
521
}
522

    
523
static void cpu_ppc_tb_stop (CPUState *env)
524
{
525
    ppc_tb_t *tb_env = env->tb_env;
526
    uint64_t tb, atb, vmclk;
527

    
528
    /* If the time base is already frozen, do nothing */
529
    if (tb_env->tb_freq != 0) {
530
        vmclk = qemu_get_clock(vm_clock);
531
        /* Get the time base */
532
        tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
533
        /* Get the alternate time base */
534
        atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
535
        /* Store the time base value (ie compute the current offset) */
536
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
537
        /* Store the alternate time base value (compute the current offset) */
538
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
539
        /* Set the time base frequency to zero */
540
        tb_env->tb_freq = 0;
541
        /* Now, the time bases are frozen to tb_offset / atb_offset value */
542
    }
543
}
544

    
545
static void cpu_ppc_tb_start (CPUState *env)
546
{
547
    ppc_tb_t *tb_env = env->tb_env;
548
    uint64_t tb, atb, vmclk;
549

    
550
    /* If the time base is not frozen, do nothing */
551
    if (tb_env->tb_freq == 0) {
552
        vmclk = qemu_get_clock(vm_clock);
553
        /* Get the time base from tb_offset */
554
        tb = tb_env->tb_offset;
555
        /* Get the alternate time base from atb_offset */
556
        atb = tb_env->atb_offset;
557
        /* Restore the tb frequency from the decrementer frequency */
558
        tb_env->tb_freq = tb_env->decr_freq;
559
        /* Store the time base value */
560
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
561
        /* Store the alternate time base value */
562
        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
563
    }
564
}
565

    
566
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
567
{
568
    ppc_tb_t *tb_env = env->tb_env;
569
    uint32_t decr;
570
    int64_t diff;
571

    
572
    diff = next - qemu_get_clock(vm_clock);
573
    if (diff >= 0)
574
        decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
575
    else
576
        decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec());
577
    LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
578

    
579
    return decr;
580
}
581

    
582
uint32_t cpu_ppc_load_decr (CPUState *env)
583
{
584
    ppc_tb_t *tb_env = env->tb_env;
585

    
586
    return _cpu_ppc_load_decr(env, tb_env->decr_next);
587
}
588

    
589
uint32_t cpu_ppc_load_hdecr (CPUState *env)
590
{
591
    ppc_tb_t *tb_env = env->tb_env;
592

    
593
    return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
594
}
595

    
596
uint64_t cpu_ppc_load_purr (CPUState *env)
597
{
598
    ppc_tb_t *tb_env = env->tb_env;
599
    uint64_t diff;
600

    
601
    diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
602

    
603
    return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
604
}
605

    
606
/* When decrementer expires,
607
 * all we need to do is generate or queue a CPU exception
608
 */
609
static inline void cpu_ppc_decr_excp(CPUState *env)
610
{
611
    /* Raise it */
612
    LOG_TB("raise decrementer exception\n");
613
    ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
614
}
615

    
616
static inline void cpu_ppc_hdecr_excp(CPUState *env)
617
{
618
    /* Raise it */
619
    LOG_TB("raise decrementer exception\n");
620
    ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
621
}
622

    
623
static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
624
                                  struct QEMUTimer *timer,
625
                                  void (*raise_excp)(CPUState *),
626
                                  uint32_t decr, uint32_t value,
627
                                  int is_excp)
628
{
629
    ppc_tb_t *tb_env = env->tb_env;
630
    uint64_t now, next;
631

    
632
    LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
633
                decr, value);
634
    now = qemu_get_clock(vm_clock);
635
    next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
636
    if (is_excp)
637
        next += *nextp - now;
638
    if (next == now)
639
        next++;
640
    *nextp = next;
641
    /* Adjust timer */
642
    qemu_mod_timer(timer, next);
643
    /* If we set a negative value and the decrementer was positive,
644
     * raise an exception.
645
     */
646
    if ((value & 0x80000000) && !(decr & 0x80000000))
647
        (*raise_excp)(env);
648
}
649

    
650
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
651
                                       uint32_t value, int is_excp)
652
{
653
    ppc_tb_t *tb_env = env->tb_env;
654

    
655
    __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
656
                         &cpu_ppc_decr_excp, decr, value, is_excp);
657
}
658

    
659
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
660
{
661
    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
662
}
663

    
664
static void cpu_ppc_decr_cb (void *opaque)
665
{
666
    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
667
}
668

    
669
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
670
                                        uint32_t value, int is_excp)
671
{
672
    ppc_tb_t *tb_env = env->tb_env;
673

    
674
    if (tb_env->hdecr_timer != NULL) {
675
        __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
676
                             &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
677
    }
678
}
679

    
680
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
681
{
682
    _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
683
}
684

    
685
static void cpu_ppc_hdecr_cb (void *opaque)
686
{
687
    _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
688
}
689

    
690
void cpu_ppc_store_purr (CPUState *env, uint64_t value)
691
{
692
    ppc_tb_t *tb_env = env->tb_env;
693

    
694
    tb_env->purr_load = value;
695
    tb_env->purr_start = qemu_get_clock(vm_clock);
696
}
697

    
698
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
699
{
700
    CPUState *env = opaque;
701
    ppc_tb_t *tb_env = env->tb_env;
702

    
703
    tb_env->tb_freq = freq;
704
    tb_env->decr_freq = freq;
705
    /* There is a bug in Linux 2.4 kernels:
706
     * if a decrementer exception is pending when it enables msr_ee at startup,
707
     * it's not ready to handle it...
708
     */
709
    _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
710
    _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
711
    cpu_ppc_store_purr(env, 0x0000000000000000ULL);
712
}
713

    
714
/* Set up (once) timebase frequency (in Hz) */
715
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
716
{
717
    ppc_tb_t *tb_env;
718

    
719
    tb_env = qemu_mallocz(sizeof(ppc_tb_t));
720
    env->tb_env = tb_env;
721
    /* Create new timer */
722
    tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
723
    if (0) {
724
        /* XXX: find a suitable condition to enable the hypervisor decrementer
725
         */
726
        tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
727
    } else {
728
        tb_env->hdecr_timer = NULL;
729
    }
730
    cpu_ppc_set_tb_clk(env, freq);
731

    
732
    return &cpu_ppc_set_tb_clk;
733
}
734

    
735
/* Specific helpers for POWER & PowerPC 601 RTC */
736
#if 0
737
static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
738
{
739
    return cpu_ppc_tb_init(env, 7812500);
740
}
741
#endif
742

    
743
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
744
{
745
    _cpu_ppc_store_tbu(env, value);
746
}
747

    
748
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
749
{
750
    return _cpu_ppc_load_tbu(env);
751
}
752

    
753
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
754
{
755
    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
756
}
757

    
758
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
759
{
760
    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
761
}
762

    
763
/*****************************************************************************/
764
/* Embedded PowerPC timers */
765

    
766
/* PIT, FIT & WDT */
767
typedef struct ppcemb_timer_t ppcemb_timer_t;
768
struct ppcemb_timer_t {
769
    uint64_t pit_reload;  /* PIT auto-reload value        */
770
    uint64_t fit_next;    /* Tick for next FIT interrupt  */
771
    struct QEMUTimer *fit_timer;
772
    uint64_t wdt_next;    /* Tick for next WDT interrupt  */
773
    struct QEMUTimer *wdt_timer;
774

    
775
    /* 405 have the PIT, 440 have a DECR.  */
776
    unsigned int decr_excp;
777
};
778

    
779
/* Fixed interval timer */
780
static void cpu_4xx_fit_cb (void *opaque)
781
{
782
    CPUState *env;
783
    ppc_tb_t *tb_env;
784
    ppcemb_timer_t *ppcemb_timer;
785
    uint64_t now, next;
786

    
787
    env = opaque;
788
    tb_env = env->tb_env;
789
    ppcemb_timer = tb_env->opaque;
790
    now = qemu_get_clock(vm_clock);
791
    switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
792
    case 0:
793
        next = 1 << 9;
794
        break;
795
    case 1:
796
        next = 1 << 13;
797
        break;
798
    case 2:
799
        next = 1 << 17;
800
        break;
801
    case 3:
802
        next = 1 << 21;
803
        break;
804
    default:
805
        /* Cannot occur, but makes gcc happy */
806
        return;
807
    }
808
    next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
809
    if (next == now)
810
        next++;
811
    qemu_mod_timer(ppcemb_timer->fit_timer, next);
812
    env->spr[SPR_40x_TSR] |= 1 << 26;
813
    if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
814
        ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
815
    LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
816
           (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
817
           env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
818
}
819

    
820
/* Programmable interval timer */
821
static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
822
{
823
    ppcemb_timer_t *ppcemb_timer;
824
    uint64_t now, next;
825

    
826
    ppcemb_timer = tb_env->opaque;
827
    if (ppcemb_timer->pit_reload <= 1 ||
828
        !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
829
        (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
830
        /* Stop PIT */
831
        LOG_TB("%s: stop PIT\n", __func__);
832
        qemu_del_timer(tb_env->decr_timer);
833
    } else {
834
        LOG_TB("%s: start PIT %016" PRIx64 "\n",
835
                    __func__, ppcemb_timer->pit_reload);
836
        now = qemu_get_clock(vm_clock);
837
        next = now + muldiv64(ppcemb_timer->pit_reload,
838
                              get_ticks_per_sec(), tb_env->decr_freq);
839
        if (is_excp)
840
            next += tb_env->decr_next - now;
841
        if (next == now)
842
            next++;
843
        qemu_mod_timer(tb_env->decr_timer, next);
844
        tb_env->decr_next = next;
845
    }
846
}
847

    
848
static void cpu_4xx_pit_cb (void *opaque)
849
{
850
    CPUState *env;
851
    ppc_tb_t *tb_env;
852
    ppcemb_timer_t *ppcemb_timer;
853

    
854
    env = opaque;
855
    tb_env = env->tb_env;
856
    ppcemb_timer = tb_env->opaque;
857
    env->spr[SPR_40x_TSR] |= 1 << 27;
858
    if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
859
        ppc_set_irq(env, ppcemb_timer->decr_excp, 1);
860
    start_stop_pit(env, tb_env, 1);
861
    LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
862
           "%016" PRIx64 "\n", __func__,
863
           (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
864
           (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
865
           env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
866
           ppcemb_timer->pit_reload);
867
}
868

    
869
/* Watchdog timer */
870
static void cpu_4xx_wdt_cb (void *opaque)
871
{
872
    CPUState *env;
873
    ppc_tb_t *tb_env;
874
    ppcemb_timer_t *ppcemb_timer;
875
    uint64_t now, next;
876

    
877
    env = opaque;
878
    tb_env = env->tb_env;
879
    ppcemb_timer = tb_env->opaque;
880
    now = qemu_get_clock(vm_clock);
881
    switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
882
    case 0:
883
        next = 1 << 17;
884
        break;
885
    case 1:
886
        next = 1 << 21;
887
        break;
888
    case 2:
889
        next = 1 << 25;
890
        break;
891
    case 3:
892
        next = 1 << 29;
893
        break;
894
    default:
895
        /* Cannot occur, but makes gcc happy */
896
        return;
897
    }
898
    next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq);
899
    if (next == now)
900
        next++;
901
    LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
902
           env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
903
    switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
904
    case 0x0:
905
    case 0x1:
906
        qemu_mod_timer(ppcemb_timer->wdt_timer, next);
907
        ppcemb_timer->wdt_next = next;
908
        env->spr[SPR_40x_TSR] |= 1 << 31;
909
        break;
910
    case 0x2:
911
        qemu_mod_timer(ppcemb_timer->wdt_timer, next);
912
        ppcemb_timer->wdt_next = next;
913
        env->spr[SPR_40x_TSR] |= 1 << 30;
914
        if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
915
            ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
916
        break;
917
    case 0x3:
918
        env->spr[SPR_40x_TSR] &= ~0x30000000;
919
        env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
920
        switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
921
        case 0x0:
922
            /* No reset */
923
            break;
924
        case 0x1: /* Core reset */
925
            ppc40x_core_reset(env);
926
            break;
927
        case 0x2: /* Chip reset */
928
            ppc40x_chip_reset(env);
929
            break;
930
        case 0x3: /* System reset */
931
            ppc40x_system_reset(env);
932
            break;
933
        }
934
    }
935
}
936

    
937
void store_40x_pit (CPUState *env, target_ulong val)
938
{
939
    ppc_tb_t *tb_env;
940
    ppcemb_timer_t *ppcemb_timer;
941

    
942
    tb_env = env->tb_env;
943
    ppcemb_timer = tb_env->opaque;
944
    LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
945
    ppcemb_timer->pit_reload = val;
946
    start_stop_pit(env, tb_env, 0);
947
}
948

    
949
target_ulong load_40x_pit (CPUState *env)
950
{
951
    return cpu_ppc_load_decr(env);
952
}
953

    
954
void store_booke_tsr (CPUState *env, target_ulong val)
955
{
956
    ppc_tb_t *tb_env = env->tb_env;
957
    ppcemb_timer_t *ppcemb_timer;
958

    
959
    ppcemb_timer = tb_env->opaque;
960

    
961
    LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
962
    env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
963
    if (val & 0x80000000)
964
        ppc_set_irq(env, ppcemb_timer->decr_excp, 0);
965
}
966

    
967
void store_booke_tcr (CPUState *env, target_ulong val)
968
{
969
    ppc_tb_t *tb_env;
970

    
971
    tb_env = env->tb_env;
972
    LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
973
    env->spr[SPR_40x_TCR] = val & 0xFFC00000;
974
    start_stop_pit(env, tb_env, 1);
975
    cpu_4xx_wdt_cb(env);
976
}
977

    
978
static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
979
{
980
    CPUState *env = opaque;
981
    ppc_tb_t *tb_env = env->tb_env;
982

    
983
    LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
984
                freq);
985
    tb_env->tb_freq = freq;
986
    tb_env->decr_freq = freq;
987
    /* XXX: we should also update all timers */
988
}
989

    
990
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq,
991
                                  unsigned int decr_excp)
992
{
993
    ppc_tb_t *tb_env;
994
    ppcemb_timer_t *ppcemb_timer;
995

    
996
    tb_env = qemu_mallocz(sizeof(ppc_tb_t));
997
    env->tb_env = tb_env;
998
    ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
999
    tb_env->tb_freq = freq;
1000
    tb_env->decr_freq = freq;
1001
    tb_env->opaque = ppcemb_timer;
1002
    LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1003
    if (ppcemb_timer != NULL) {
1004
        /* We use decr timer for PIT */
1005
        tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
1006
        ppcemb_timer->fit_timer =
1007
            qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
1008
        ppcemb_timer->wdt_timer =
1009
            qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
1010
        ppcemb_timer->decr_excp = decr_excp;
1011
    }
1012

    
1013
    return &ppc_emb_set_tb_clk;
1014
}
1015

    
1016
/*****************************************************************************/
1017
/* Embedded PowerPC Device Control Registers */
1018
typedef struct ppc_dcrn_t ppc_dcrn_t;
1019
struct ppc_dcrn_t {
1020
    dcr_read_cb dcr_read;
1021
    dcr_write_cb dcr_write;
1022
    void *opaque;
1023
};
1024

    
1025
/* XXX: on 460, DCR addresses are 32 bits wide,
1026
 *      using DCRIPR to get the 22 upper bits of the DCR address
1027
 */
1028
#define DCRN_NB 1024
1029
struct ppc_dcr_t {
1030
    ppc_dcrn_t dcrn[DCRN_NB];
1031
    int (*read_error)(int dcrn);
1032
    int (*write_error)(int dcrn);
1033
};
1034

    
1035
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1036
{
1037
    ppc_dcrn_t *dcr;
1038

    
1039
    if (dcrn < 0 || dcrn >= DCRN_NB)
1040
        goto error;
1041
    dcr = &dcr_env->dcrn[dcrn];
1042
    if (dcr->dcr_read == NULL)
1043
        goto error;
1044
    *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1045

    
1046
    return 0;
1047

    
1048
 error:
1049
    if (dcr_env->read_error != NULL)
1050
        return (*dcr_env->read_error)(dcrn);
1051

    
1052
    return -1;
1053
}
1054

    
1055
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1056
{
1057
    ppc_dcrn_t *dcr;
1058

    
1059
    if (dcrn < 0 || dcrn >= DCRN_NB)
1060
        goto error;
1061
    dcr = &dcr_env->dcrn[dcrn];
1062
    if (dcr->dcr_write == NULL)
1063
        goto error;
1064
    (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1065

    
1066
    return 0;
1067

    
1068
 error:
1069
    if (dcr_env->write_error != NULL)
1070
        return (*dcr_env->write_error)(dcrn);
1071

    
1072
    return -1;
1073
}
1074

    
1075
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1076
                      dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1077
{
1078
    ppc_dcr_t *dcr_env;
1079
    ppc_dcrn_t *dcr;
1080

    
1081
    dcr_env = env->dcr_env;
1082
    if (dcr_env == NULL)
1083
        return -1;
1084
    if (dcrn < 0 || dcrn >= DCRN_NB)
1085
        return -1;
1086
    dcr = &dcr_env->dcrn[dcrn];
1087
    if (dcr->opaque != NULL ||
1088
        dcr->dcr_read != NULL ||
1089
        dcr->dcr_write != NULL)
1090
        return -1;
1091
    dcr->opaque = opaque;
1092
    dcr->dcr_read = dcr_read;
1093
    dcr->dcr_write = dcr_write;
1094

    
1095
    return 0;
1096
}
1097

    
1098
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
1099
                  int (*write_error)(int dcrn))
1100
{
1101
    ppc_dcr_t *dcr_env;
1102

    
1103
    dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
1104
    dcr_env->read_error = read_error;
1105
    dcr_env->write_error = write_error;
1106
    env->dcr_env = dcr_env;
1107

    
1108
    return 0;
1109
}
1110

    
1111
/*****************************************************************************/
1112
/* Debug port */
1113
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1114
{
1115
    addr &= 0xF;
1116
    switch (addr) {
1117
    case 0:
1118
        printf("%c", val);
1119
        break;
1120
    case 1:
1121
        printf("\n");
1122
        fflush(stdout);
1123
        break;
1124
    case 2:
1125
        printf("Set loglevel to %04" PRIx32 "\n", val);
1126
        cpu_set_log(val | 0x100);
1127
        break;
1128
    }
1129
}
1130

    
1131
/*****************************************************************************/
1132
/* NVRAM helpers */
1133
static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
1134
{
1135
    return (*nvram->read_fn)(nvram->opaque, addr);;
1136
}
1137

    
1138
static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
1139
{
1140
    (*nvram->write_fn)(nvram->opaque, addr, val);
1141
}
1142

    
1143
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
1144
{
1145
    nvram_write(nvram, addr, value);
1146
}
1147

    
1148
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr)
1149
{
1150
    return nvram_read(nvram, addr);
1151
}
1152

    
1153
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
1154
{
1155
    nvram_write(nvram, addr, value >> 8);
1156
    nvram_write(nvram, addr + 1, value & 0xFF);
1157
}
1158

    
1159
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr)
1160
{
1161
    uint16_t tmp;
1162

    
1163
    tmp = nvram_read(nvram, addr) << 8;
1164
    tmp |= nvram_read(nvram, addr + 1);
1165

    
1166
    return tmp;
1167
}
1168

    
1169
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
1170
{
1171
    nvram_write(nvram, addr, value >> 24);
1172
    nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
1173
    nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
1174
    nvram_write(nvram, addr + 3, value & 0xFF);
1175
}
1176

    
1177
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
1178
{
1179
    uint32_t tmp;
1180

    
1181
    tmp = nvram_read(nvram, addr) << 24;
1182
    tmp |= nvram_read(nvram, addr + 1) << 16;
1183
    tmp |= nvram_read(nvram, addr + 2) << 8;
1184
    tmp |= nvram_read(nvram, addr + 3);
1185

    
1186
    return tmp;
1187
}
1188

    
1189
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1190
                       const char *str, uint32_t max)
1191
{
1192
    int i;
1193

    
1194
    for (i = 0; i < max && str[i] != '\0'; i++) {
1195
        nvram_write(nvram, addr + i, str[i]);
1196
    }
1197
    nvram_write(nvram, addr + i, str[i]);
1198
    nvram_write(nvram, addr + max - 1, '\0');
1199
}
1200

    
1201
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
1202
{
1203
    int i;
1204

    
1205
    memset(dst, 0, max);
1206
    for (i = 0; i < max; i++) {
1207
        dst[i] = NVRAM_get_byte(nvram, addr + i);
1208
        if (dst[i] == '\0')
1209
            break;
1210
    }
1211

    
1212
    return i;
1213
}
1214

    
1215
static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1216
{
1217
    uint16_t tmp;
1218
    uint16_t pd, pd1, pd2;
1219

    
1220
    tmp = prev >> 8;
1221
    pd = prev ^ value;
1222
    pd1 = pd & 0x000F;
1223
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1224
    tmp ^= (pd1 << 3) | (pd1 << 8);
1225
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1226

    
1227
    return tmp;
1228
}
1229

    
1230
static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
1231
{
1232
    uint32_t i;
1233
    uint16_t crc = 0xFFFF;
1234
    int odd;
1235

    
1236
    odd = count & 1;
1237
    count &= ~1;
1238
    for (i = 0; i != count; i++) {
1239
        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1240
    }
1241
    if (odd) {
1242
        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1243
    }
1244

    
1245
    return crc;
1246
}
1247

    
1248
#define CMDLINE_ADDR 0x017ff000
1249

    
1250
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1251
                          const char *arch,
1252
                          uint32_t RAM_size, int boot_device,
1253
                          uint32_t kernel_image, uint32_t kernel_size,
1254
                          const char *cmdline,
1255
                          uint32_t initrd_image, uint32_t initrd_size,
1256
                          uint32_t NVRAM_image,
1257
                          int width, int height, int depth)
1258
{
1259
    uint16_t crc;
1260

    
1261
    /* Set parameters for Open Hack'Ware BIOS */
1262
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1263
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
1264
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
1265
    NVRAM_set_string(nvram, 0x20, arch, 16);
1266
    NVRAM_set_lword(nvram,  0x30, RAM_size);
1267
    NVRAM_set_byte(nvram,   0x34, boot_device);
1268
    NVRAM_set_lword(nvram,  0x38, kernel_image);
1269
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
1270
    if (cmdline) {
1271
        /* XXX: put the cmdline in NVRAM too ? */
1272
        pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
1273
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
1274
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
1275
    } else {
1276
        NVRAM_set_lword(nvram,  0x40, 0);
1277
        NVRAM_set_lword(nvram,  0x44, 0);
1278
    }
1279
    NVRAM_set_lword(nvram,  0x48, initrd_image);
1280
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
1281
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);
1282

    
1283
    NVRAM_set_word(nvram,   0x54, width);
1284
    NVRAM_set_word(nvram,   0x56, height);
1285
    NVRAM_set_word(nvram,   0x58, depth);
1286
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1287
    NVRAM_set_word(nvram,   0xFC, crc);
1288

    
1289
    return 0;
1290
}