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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS helper routines.
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias.
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * Lesser General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 81fdc5f8 | ths | * License along with this library; if not, write to the Free Software
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19 | 81fdc5f8 | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 81fdc5f8 | ths | */
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21 | 81fdc5f8 | ths | |
22 | 81fdc5f8 | ths | #include <stdio.h> |
23 | 81fdc5f8 | ths | #include <string.h> |
24 | 81fdc5f8 | ths | |
25 | 81fdc5f8 | ths | #include "config.h" |
26 | 81fdc5f8 | ths | #include "cpu.h" |
27 | 81fdc5f8 | ths | #include "mmu.h" |
28 | 81fdc5f8 | ths | #include "exec-all.h" |
29 | 81fdc5f8 | ths | |
30 | 81fdc5f8 | ths | #if defined(CONFIG_USER_ONLY)
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31 | 81fdc5f8 | ths | |
32 | 81fdc5f8 | ths | void do_interrupt (CPUState *env)
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33 | 81fdc5f8 | ths | { |
34 | 81fdc5f8 | ths | env->exception_index = -1;
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35 | 81fdc5f8 | ths | } |
36 | 81fdc5f8 | ths | |
37 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
38 | 81fdc5f8 | ths | int is_user, int is_softmmu) |
39 | 81fdc5f8 | ths | { |
40 | 81fdc5f8 | ths | env->exception_index = 0xaa;
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41 | 81fdc5f8 | ths | env->debug1 = address; |
42 | 81fdc5f8 | ths | cpu_dump_state(env, stderr, fprintf, 0);
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43 | 81fdc5f8 | ths | printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc);
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44 | 81fdc5f8 | ths | return 1; |
45 | 81fdc5f8 | ths | } |
46 | 81fdc5f8 | ths | |
47 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
48 | 81fdc5f8 | ths | { |
49 | 81fdc5f8 | ths | return addr;
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50 | 81fdc5f8 | ths | } |
51 | 81fdc5f8 | ths | |
52 | 81fdc5f8 | ths | #else /* !CONFIG_USER_ONLY */ |
53 | 81fdc5f8 | ths | |
54 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
55 | 81fdc5f8 | ths | int is_user, int is_softmmu) |
56 | 81fdc5f8 | ths | { |
57 | 81fdc5f8 | ths | struct cris_mmu_result_t res;
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58 | 81fdc5f8 | ths | int prot, miss;
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59 | 81fdc5f8 | ths | target_ulong phy; |
60 | 81fdc5f8 | ths | |
61 | 81fdc5f8 | ths | address &= TARGET_PAGE_MASK; |
62 | 81fdc5f8 | ths | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
63 | 81fdc5f8 | ths | // printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu);
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64 | 81fdc5f8 | ths | miss = cris_mmu_translate(&res, env, address, rw, is_user); |
65 | 81fdc5f8 | ths | if (miss)
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66 | 81fdc5f8 | ths | { |
67 | 81fdc5f8 | ths | /* handle the miss. */
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68 | 81fdc5f8 | ths | phy = 0;
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69 | 81fdc5f8 | ths | env->exception_index = EXCP_MMU_MISS; |
70 | 81fdc5f8 | ths | } |
71 | 81fdc5f8 | ths | else
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72 | 81fdc5f8 | ths | { |
73 | 81fdc5f8 | ths | phy = res.phy; |
74 | 81fdc5f8 | ths | } |
75 | 81fdc5f8 | ths | // printf ("a=%x phy=%x\n", address, phy);
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76 | 81fdc5f8 | ths | return tlb_set_page(env, address, phy, prot, is_user, is_softmmu);
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77 | 81fdc5f8 | ths | } |
78 | 81fdc5f8 | ths | |
79 | 81fdc5f8 | ths | |
80 | 81fdc5f8 | ths | static void cris_shift_ccs(CPUState *env) |
81 | 81fdc5f8 | ths | { |
82 | 81fdc5f8 | ths | uint32_t ccs; |
83 | 81fdc5f8 | ths | /* Apply the ccs shift. */
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84 | 81fdc5f8 | ths | ccs = env->pregs[SR_CCS]; |
85 | 81fdc5f8 | ths | ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2); |
86 | 81fdc5f8 | ths | // printf ("ccs=%x %x\n", env->pregs[SR_CCS], ccs);
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87 | 81fdc5f8 | ths | env->pregs[SR_CCS] = ccs; |
88 | 81fdc5f8 | ths | } |
89 | 81fdc5f8 | ths | |
90 | 81fdc5f8 | ths | void do_interrupt(CPUState *env)
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91 | 81fdc5f8 | ths | { |
92 | 81fdc5f8 | ths | uint32_t ebp, isr; |
93 | 81fdc5f8 | ths | int irqnum;
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94 | 81fdc5f8 | ths | |
95 | 81fdc5f8 | ths | fflush(NULL);
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96 | 81fdc5f8 | ths | |
97 | 81fdc5f8 | ths | #if 0
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98 | 81fdc5f8 | ths | printf ("exception index=%d interrupt_req=%d\n",
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99 | 81fdc5f8 | ths | env->exception_index,
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100 | 81fdc5f8 | ths | env->interrupt_request);
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101 | 81fdc5f8 | ths | #endif
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102 | 81fdc5f8 | ths | |
103 | 81fdc5f8 | ths | switch (env->exception_index)
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104 | 81fdc5f8 | ths | { |
105 | 81fdc5f8 | ths | case EXCP_BREAK:
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106 | 81fdc5f8 | ths | // printf ("BREAK! %d\n", env->trapnr);
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107 | 81fdc5f8 | ths | irqnum = env->trapnr; |
108 | 81fdc5f8 | ths | ebp = env->pregs[SR_EBP]; |
109 | 81fdc5f8 | ths | isr = ldl_code(ebp + irqnum * 4);
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110 | 81fdc5f8 | ths | env->pregs[SR_ERP] = env->pc + 2;
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111 | 81fdc5f8 | ths | env->pc = isr; |
112 | 81fdc5f8 | ths | |
113 | 81fdc5f8 | ths | cris_shift_ccs(env); |
114 | 81fdc5f8 | ths | |
115 | 81fdc5f8 | ths | break;
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116 | 81fdc5f8 | ths | case EXCP_MMU_MISS:
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117 | 81fdc5f8 | ths | // printf ("MMU miss\n");
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118 | 81fdc5f8 | ths | irqnum = 4;
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119 | 81fdc5f8 | ths | ebp = env->pregs[SR_EBP]; |
120 | 81fdc5f8 | ths | isr = ldl_code(ebp + irqnum * 4);
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121 | 81fdc5f8 | ths | env->pregs[SR_ERP] = env->pc; |
122 | 81fdc5f8 | ths | env->pc = isr; |
123 | 81fdc5f8 | ths | cris_shift_ccs(env); |
124 | 81fdc5f8 | ths | break;
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125 | 81fdc5f8 | ths | |
126 | 81fdc5f8 | ths | default:
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127 | 81fdc5f8 | ths | { |
128 | 81fdc5f8 | ths | /* Maybe the irq was acked by sw before we got a
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129 | 81fdc5f8 | ths | change to take it. */
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130 | 81fdc5f8 | ths | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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131 | 81fdc5f8 | ths | if (!env->pending_interrupts)
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132 | 81fdc5f8 | ths | return;
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133 | 81fdc5f8 | ths | if (!(env->pregs[SR_CCS] & I_FLAG)) {
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134 | 81fdc5f8 | ths | return;
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135 | 81fdc5f8 | ths | } |
136 | 81fdc5f8 | ths | |
137 | 81fdc5f8 | ths | irqnum = 31 -
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138 | 81fdc5f8 | ths | __builtin_clz(env->pending_interrupts); |
139 | 81fdc5f8 | ths | irqnum += 0x30;
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140 | 81fdc5f8 | ths | ebp = env->pregs[SR_EBP]; |
141 | 81fdc5f8 | ths | isr = ldl_code(ebp + irqnum * 4);
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142 | 81fdc5f8 | ths | env->pregs[SR_ERP] = env->pc; |
143 | 81fdc5f8 | ths | env->pc = isr; |
144 | 81fdc5f8 | ths | |
145 | 81fdc5f8 | ths | cris_shift_ccs(env); |
146 | 81fdc5f8 | ths | #if 0
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147 | 81fdc5f8 | ths | printf ("%s ebp=%x %x isr=%x %d"
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148 | 81fdc5f8 | ths | " ir=%x pending=%x\n",
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149 | 81fdc5f8 | ths | __func__,
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150 | 81fdc5f8 | ths | ebp, ebp + irqnum * 4,
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151 | 81fdc5f8 | ths | isr, env->exception_index,
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152 | 81fdc5f8 | ths | env->interrupt_request,
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153 | 81fdc5f8 | ths | env->pending_interrupts);
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154 | 81fdc5f8 | ths | #endif
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155 | 81fdc5f8 | ths | } |
156 | 81fdc5f8 | ths | |
157 | 81fdc5f8 | ths | } |
158 | 81fdc5f8 | ths | break;
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159 | 81fdc5f8 | ths | } |
160 | 81fdc5f8 | ths | } |
161 | 81fdc5f8 | ths | |
162 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
163 | 81fdc5f8 | ths | { |
164 | 81fdc5f8 | ths | // printf ("%s\n", __func__);
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165 | 81fdc5f8 | ths | uint32_t phy = addr; |
166 | 81fdc5f8 | ths | struct cris_mmu_result_t res;
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167 | 81fdc5f8 | ths | int miss;
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168 | 81fdc5f8 | ths | miss = cris_mmu_translate(&res, env, addr, 0, 0); |
169 | 81fdc5f8 | ths | if (!miss)
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170 | 81fdc5f8 | ths | phy = res.phy; |
171 | 81fdc5f8 | ths | return phy;
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172 | 81fdc5f8 | ths | } |
173 | 81fdc5f8 | ths | #endif |