Revision 94e1a912 hw/pcnet.c
| b/hw/pcnet.c | ||
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| 35 | 35 |
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt |
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*/ |
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#include "sysbus.h" |
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#include "pci.h" |
| 40 | 39 |
#include "net.h" |
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#include "loader.h" |
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#include "qemu-timer.h" |
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#include "qemu_socket.h" |
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#include "pcnet.h" |
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//#define PCNET_DEBUG |
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//#define PCNET_DEBUG_IO |
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//#define PCNET_DEBUG_BCR |
| ... | ... | |
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//#define PCNET_DEBUG_MATCH |
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#define PCNET_IOPORT_SIZE 0x20 |
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#define PCNET_PNPMMIO_SIZE 0x20 |
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#define PCNET_LOOPTEST_CRC 1 |
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#define PCNET_LOOPTEST_NOCRC 2 |
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typedef struct PCNetState_st PCNetState; |
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struct PCNetState_st {
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VLANClientState *vc; |
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NICConf conf; |
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QEMUTimer *poll_timer; |
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int rap, isr, lnkst; |
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uint32_t rdra, tdra; |
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uint8_t prom[16]; |
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uint16_t csr[128]; |
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uint16_t bcr[32]; |
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uint64_t timer; |
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int mmio_index, xmit_pos; |
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uint8_t buffer[4096]; |
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int tx_busy; |
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qemu_irq irq; |
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void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr, |
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uint8_t *buf, int len, int do_bswap); |
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void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr, |
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uint8_t *buf, int len, int do_bswap); |
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void *dma_opaque; |
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int looptest; |
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}; |
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typedef struct {
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PCIDevice pci_dev; |
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PCNetState state; |
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} PCIPCNetState; |
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typedef struct {
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SysBusDevice busdev; |
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PCNetState state; |
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} SysBusPCNetState; |
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struct qemu_ether_header {
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uint8_t ether_dhost[6]; |
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uint8_t ether_shost[6]; |
| ... | ... | |
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return val; |
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} |
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static void pcnet_h_reset(void *opaque)
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void pcnet_h_reset(void *opaque) |
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{
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PCNetState *s = opaque; |
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int i; |
| ... | ... | |
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return val; |
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} |
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static void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{
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PCNetState *s = opaque; |
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pcnet_poll_timer(s); |
| ... | ... | |
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pcnet_update_irq(s); |
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} |
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static uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
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uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr) |
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{
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PCNetState *s = opaque; |
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uint32_t val = -1; |
| ... | ... | |
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} |
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static void pcnet_save(QEMUFile *f, void *opaque)
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void pcnet_save(QEMUFile *f, void *opaque) |
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{
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PCNetState *s = opaque; |
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unsigned int i; |
| ... | ... | |
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qemu_put_timer(f, s->poll_timer); |
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} |
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static int pcnet_load(QEMUFile *f, void *opaque, int version_id)
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int pcnet_load(QEMUFile *f, void *opaque, int version_id) |
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{
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PCNetState *s = opaque; |
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int i, dummy; |
| ... | ... | |
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return pcnet_load(f, &s->state, version_id); |
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} |
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static void pcnet_common_cleanup(PCNetState *d)
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void pcnet_common_cleanup(PCNetState *d) |
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{
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d->vc = NULL; |
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} |
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static int pcnet_common_init(DeviceState *dev, PCNetState *s,
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int pcnet_common_init(DeviceState *dev, PCNetState *s, |
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NetCleanup *cleanup) |
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{
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s->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, s); |
| ... | ... | |
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pcnet_h_reset(&d->state); |
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} |
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/* SPARC32 interface */ |
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#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure |
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#include "sun4m.h" |
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static void parent_lance_reset(void *opaque, int irq, int level) |
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{
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SysBusPCNetState *d = opaque; |
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if (level) |
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pcnet_h_reset(&d->state); |
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} |
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static void lance_mem_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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SysBusPCNetState *d = opaque; |
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#ifdef PCNET_DEBUG_IO |
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printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
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val & 0xffff); |
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#endif |
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pcnet_ioport_writew(&d->state, addr, val & 0xffff); |
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} |
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static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) |
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{
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SysBusPCNetState *d = opaque; |
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uint32_t val; |
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val = pcnet_ioport_readw(&d->state, addr); |
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#ifdef PCNET_DEBUG_IO |
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printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
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val & 0xffff); |
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#endif |
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return val & 0xffff; |
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} |
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static CPUReadMemoryFunc * const lance_mem_read[3] = {
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NULL, |
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lance_mem_readw, |
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NULL, |
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}; |
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static CPUWriteMemoryFunc * const lance_mem_write[3] = {
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NULL, |
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lance_mem_writew, |
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NULL, |
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}; |
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static void lance_cleanup(VLANClientState *vc) |
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{
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PCNetState *d = vc->opaque; |
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pcnet_common_cleanup(d); |
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} |
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static int lance_init(SysBusDevice *dev) |
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{
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SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); |
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PCNetState *s = &d->state; |
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s->mmio_index = |
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cpu_register_io_memory(lance_mem_read, lance_mem_write, d); |
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qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); |
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sysbus_init_mmio(dev, 4, s->mmio_index); |
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sysbus_init_irq(dev, &s->irq); |
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s->phys_mem_read = ledma_memory_read; |
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s->phys_mem_write = ledma_memory_write; |
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register_savevm("pcnet", -1, 3, pcnet_save, pcnet_load, s);
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return pcnet_common_init(&dev->qdev, s, lance_cleanup); |
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} |
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static void lance_reset(DeviceState *dev) |
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{
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SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev); |
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pcnet_h_reset(&d->state); |
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} |
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static SysBusDeviceInfo lance_info = {
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.init = lance_init, |
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.qdev.name = "lance", |
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.qdev.size = sizeof(SysBusPCNetState), |
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.qdev.reset = lance_reset, |
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.qdev.props = (Property[]) {
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DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
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DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), |
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DEFINE_PROP_END_OF_LIST(), |
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} |
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}; |
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#endif /* TARGET_SPARC */ |
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static PCIDeviceInfo pcnet_info = {
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.qdev.name = "pcnet", |
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.qdev.size = sizeof(PCIPCNetState), |
| ... | ... | |
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static void pcnet_register_devices(void) |
| 2207 | 2074 |
{
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| 2208 | 2075 |
pci_qdev_register(&pcnet_info); |
| 2209 |
#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) |
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sysbus_register_withprop(&lance_info); |
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#endif |
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} |
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device_init(pcnet_register_devices) |
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