root / hw / lance.c @ 94e1a912
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/*
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* QEMU AMD PC-Net II (Am79C970A) emulation
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*
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* Copyright (c) 2004 Antony T Curtis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* This software was written to be compatible with the specification:
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* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
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* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
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*/
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/*
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* On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
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*/
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#include "sysbus.h" |
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#include "net.h" |
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#include "qemu-timer.h" |
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#include "qemu_socket.h" |
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#include "sun4m.h" |
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#include "pcnet.h" |
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typedef struct { |
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SysBusDevice busdev; |
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PCNetState state; |
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} SysBusPCNetState; |
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static void parent_lance_reset(void *opaque, int irq, int level) |
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{ |
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SysBusPCNetState *d = opaque; |
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if (level)
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pcnet_h_reset(&d->state); |
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} |
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static void lance_mem_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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SysBusPCNetState *d = opaque; |
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#ifdef PCNET_DEBUG_IO
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printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr, |
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val & 0xffff);
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#endif
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pcnet_ioport_writew(&d->state, addr, val & 0xffff);
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} |
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static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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SysBusPCNetState *d = opaque; |
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uint32_t val; |
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val = pcnet_ioport_readw(&d->state, addr); |
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#ifdef PCNET_DEBUG_IO
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printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr, |
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val & 0xffff);
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#endif
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return val & 0xffff; |
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} |
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static CPUReadMemoryFunc * const lance_mem_read[3] = { |
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NULL,
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lance_mem_readw, |
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NULL,
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}; |
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static CPUWriteMemoryFunc * const lance_mem_write[3] = { |
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NULL,
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lance_mem_writew, |
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NULL,
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}; |
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static void lance_cleanup(VLANClientState *vc) |
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{ |
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PCNetState *d = vc->opaque; |
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pcnet_common_cleanup(d); |
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} |
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static int lance_init(SysBusDevice *dev) |
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{ |
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SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); |
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PCNetState *s = &d->state; |
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s->mmio_index = |
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cpu_register_io_memory(lance_mem_read, lance_mem_write, d); |
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qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
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sysbus_init_mmio(dev, 4, s->mmio_index);
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sysbus_init_irq(dev, &s->irq); |
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s->phys_mem_read = ledma_memory_read; |
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s->phys_mem_write = ledma_memory_write; |
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register_savevm("pcnet", -1, 3, pcnet_save, pcnet_load, s); |
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return pcnet_common_init(&dev->qdev, s, lance_cleanup);
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} |
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static void lance_reset(DeviceState *dev) |
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{ |
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SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev); |
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pcnet_h_reset(&d->state); |
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} |
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static SysBusDeviceInfo lance_info = {
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.init = lance_init, |
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.qdev.name = "lance",
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.qdev.size = sizeof(SysBusPCNetState),
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.qdev.reset = lance_reset, |
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.qdev.props = (Property[]) { |
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DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
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DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), |
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DEFINE_PROP_END_OF_LIST(), |
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} |
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}; |
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static void lance_register_devices(void) |
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{ |
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sysbus_register_withprop(&lance_info); |
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} |
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device_init(lance_register_devices) |