History | View | Annotate | Download (92.9 kB)
powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linuxon virtex5 boards.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSRvalue that is rather simple. If we leave out the HV case, it's almostalways 0.
To reflect this, let's redesign the way that MSR value gets calculated....
powerpc: Avoid TLB related log spamming
Invalid TLB entries are normal and should not spam the log.
target-ppc: remove useless line
This line was a bit clear.The next lines set or reset this bit (LE) depending of another bit (ILE).So the first line is useless.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processorsbecause some interrupt specifics bits of SRR1 are copied to MSR.
SRR1 is a save of MSR during interrupt.During RFI, MSR must be restored from SRR1....
ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Signed-off-by: Paul Brook <paul@codesourcery.com>
PPC: Fix large pages
We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviouslythat breaks, so let's just ignore 1TB SLB entries for now and instead do16MB pages correctly.
This fixes PPC64 Linux boot with -m above 256.
Signed-off-by: Alexander Graf <agraf@suse.de>...
ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused byzone protection bits.
ppc-40x: Correct decoding of zone protection bits.
The 40x MMU has 15 zones in the ZPR register.
user: move CPU reset call to main.c for x86/PPC/Sparc
PPC: rename cpu_ppc_reset to cpu_reset for consistency
PPC: remove unneeded calls to device reset
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Replace REGX with PRIx64
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Update to a hopefully more future proof FSF address
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Fix PPC reset
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Explain why the whole TLB is flushed on SR write
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
Disable BAT for 970
The 970 doesn't know BAT, so let's not search BATs there.This was only in as a hack for OpenHackWare so it wouldwork on PPC64.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Fix NX bit
ctx->nx only got ORed, but never reset. So when one page in thelifetime of the VM was ever NX, all later pages were too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
Enable 64bit mode on interrupts
Real 970s enable MSR_SF on all interrupts. The current code didn't dothis until now, so let's activate it!
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
Implement large pages
The current SLB/PTE code does not support large pages, which arerequired by Linux, as it boots up with the kernel regions up as large.
This patch implements large page support, so we can run Linux.
Signed-off-by: Alexander Graf <alex@csgraf.de>...
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
Turn MMU off on reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6637 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>Acked-by: Hollis Blanchard <hollisb@us.ibm.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6329 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: Enable KVM for ppcemb.
Implement hooks called by generic KVM code.
Also add code that will copy the host's CPU and timebase frequencies to theguest, which is necessary on KVM because the guest can directly access thetimebase.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>...
target-ppc: remove remaining warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove unneeded include
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5990 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: rework exception code
... also remove two warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable SPE and Altivec in user mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5965 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: initialize MSR appropriately in user-mode
Mask the initial MSR with the mask from the PowerPC CPU definition.
Noticed by Nathan Froyd.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable access type in MMU
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5950 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SLB/TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert exceptions generation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: convert effective address computation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
Fix incorrect debug prints (reported by Paul Brook).Remove obsolete / duplicated debug prints and improve output consistency.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
Revert foolish patch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ppc32 register dumps on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 620 MMU do not have the same exact behavior as standard 64 bits PowerPC ones.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
Define Freescale cores specific MMU model, exceptions and input bus. (but do not provide any actual implementation).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
Always make all PowerPC exception definitions visible.Always make the hypervisor timers available.Remove all TARGET_PPC64H checks, keeping a few if (0) tests for casesthat cannot be properly handled with the current PowerPC CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
Allow use of SPE extension by all PowerPC targets, adding gprh registers to store GPR MSBs when GPRs are 32 bits.Remove not-needed-anymore ppcemb-linux-user target.Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space....
Fix usage of the -1 constant in the PowerPC target code:fix invalid size casts and/or sign-extensions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3626 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 601 need specific callbacks for its BATs setup.Implement PowerPC 601 HID0 register, needed for little-endian mode support.As a consequence, we need to merge hflags coming from MSR with other ones.Use little-endian mode from hflags instead of MSR during code translation....
Fix PowerPC program exception that was broken by FPU exception patches (bug reported by Jason Wessel)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3509 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC FPSCR update and floating-point exception generation in most useful cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
Make PowerPC hypervisor resources able to compile, even if not enabled for now.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3446 c046a42c-6fe2-441c-8c8c-71466251a162
Bugfix: PowerPC 64 slbia never invalidates the first segment entry.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3445 c046a42c-6fe2-441c-8c8c-71466251a162
Gprof prooved the PowerPC emulation spent too much time in MSR load and storeroutines. Coming back to a raw MSR storage model then speed-up the emulation.Improve fast MSR updates (wrtee wrteei and mtriee cases).Share rfi family instructions helpers code to avoid bug in duplicated code....
Properly implement non-execute bit on PowerPC segments and PTEs.Fix page protection bits for PowerPC 64 MMU.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162
There is no need of a specific MMU model for PowerPC 601.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
Implement PowerPC 64 SLB invalidation helpers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3391 c046a42c-6fe2-441c-8c8c-71466251a162
Do not allow PowerPC CPU restart after entering checkstop mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3388 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
Remove synonymous in PowerPC MSR bits definitions.Fix MSR EP bit buggy definition.Remove unuseful MSR flags.Fix MSR bits and flags definitions for most supported PowerPC implementations.Add MSR definitions/flags constistency checks and optional dump....
Real-mode only PowerPC 40x do not have any TLBs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3353 c046a42c-6fe2-441c-8c8c-71466251a162
Implement exception prefix feature for PowerPC 601.Fix PowerPC 601 hardware reset vector.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3352 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC target coding style fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC target optimisations: make intensive use of always_inline.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3347 c046a42c-6fe2-441c-8c8c-71466251a162
Add MSR bits signification per PowerPC implementation flags (to be continued).As a side effect, single step and branch step are available again.Remove irrelevant MSR bits definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162
Full implementation of PowerPC 64 MMU, just missing support for 1 TB memory segments.Remove the PowerPC 64 "bridge" MMU model and implement segment registers emulation using SLB entries instead.Make SLB area size implementation dependant.Improve TLB & SLB search debug traces....
PowerPC hardware reset vector is now considered as part of the exception model.Use it at CPU initialisation time.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3332 c046a42c-6fe2-441c-8c8c-71466251a162
Enable PowerPC 64 MMU model and exceptions.Cleanups in MMU exceptions generation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3319 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC initialisation and first reset: reset must occur after we defined the CPU features.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3317 c046a42c-6fe2-441c-8c8c-71466251a162
We never have to export ppc_set_irq.Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162
Fix reproductible crash: call cpu_loop_exit from micro-op, not from helper.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3311 c046a42c-6fe2-441c-8c8c-71466251a162
Handle all MMU models in switches, even if it's just to abort because of lack of supporting code.Implement 74xx software TLB model.Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss on those processors.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid op helpers that would just call helpers for TLB & SLB management: call the helpers directly from the micro-ops.Avoid duplicated code for tlbsx. implementation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3302 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC TLB miss dump code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3295 c046a42c-6fe2-441c-8c8c-71466251a162
XER is to be treated as a 64 bits register on 64 bits implementations, according to the PowerPC 2.04 specification.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3279 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid compilation warnings on 32 bits hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3203 c046a42c-6fe2-441c-8c8c-71466251a162
More PowerPC definitions, from POWER 2.04 specifications and misc sources.Check that at least instructions set and SPRs are correct for PowerPC 401, 403, 405 and 440 cores.Implement PowerPC 401 MMU model (real-mode only).Improve INSNs and SPRs dump to ease parse with standard shell tools....
Make CPU hflags be a masked version of the PowerPC MSR.As a side effect, avoid potential bits shadowing in TB flags on 64 bits BookE.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3199 c046a42c-6fe2-441c-8c8c-71466251a162
Code provision for PowerPC BookE MMU model support.Better MSR flags initialisation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3189 c046a42c-6fe2-441c-8c8c-71466251a162