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1
/*
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 *  PowerPC CPU initialization for qemu.
3
 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
19

    
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/* A lot of PowerPC definition have been included here.
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 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
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 */
24

    
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#include "dis-asm.h"
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#include "gdbstub.h"
27

    
28
//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DUMP_SPR_ACCESSES
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#if defined(CONFIG_USER_ONLY)
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#define TODO_USER_ONLY 1
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#endif
34

    
35
struct ppc_def_t {
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    const char *name;
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    uint32_t pvr;
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    uint32_t svr;
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    uint64_t insns_flags;
40
    uint64_t msr_mask;
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    powerpc_mmu_t   mmu_model;
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    powerpc_excp_t  excp_model;
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    powerpc_input_t bus_model;
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    uint32_t flags;
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    int bfd_mach;
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    void (*init_proc)(CPUPPCState *env);
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    int  (*check_pow)(CPUPPCState *env);
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};
49

    
50
/* For user-mode emulation, we don't emulate any IRQ controller */
51
#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name)                                                 \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
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{                                                                             \
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}
56
#else
57
#define PPC_IRQ_INIT_FN(name)                                                 \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
60

    
61
PPC_IRQ_INIT_FN(40x);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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PPC_IRQ_INIT_FN(e500);
65

    
66
/* Generic callbacks:
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 * do nothing but store/retrieve spr value
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 */
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static void spr_read_generic (void *opaque, int gprn, int sprn)
70
{
71
    gen_load_spr(cpu_gpr[gprn], sprn);
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#ifdef PPC_DUMP_SPR_ACCESSES
73
    {
74
        TCGv t0 = tcg_const_i32(sprn);
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        gen_helper_load_dump_spr(t0);
76
        tcg_temp_free_i32(t0);
77
    }
78
#endif
79
}
80

    
81
static void spr_write_generic (void *opaque, int sprn, int gprn)
82
{
83
    gen_store_spr(sprn, cpu_gpr[gprn]);
84
#ifdef PPC_DUMP_SPR_ACCESSES
85
    {
86
        TCGv t0 = tcg_const_i32(sprn);
87
        gen_helper_store_dump_spr(t0);
88
        tcg_temp_free_i32(t0);
89
    }
90
#endif
91
}
92

    
93
#if !defined(CONFIG_USER_ONLY)
94
static void spr_write_clear (void *opaque, int sprn, int gprn)
95
{
96
    TCGv t0 = tcg_temp_new();
97
    TCGv t1 = tcg_temp_new();
98
    gen_load_spr(t0, sprn);
99
    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
100
    tcg_gen_and_tl(t0, t0, t1);
101
    gen_store_spr(sprn, t0);
102
    tcg_temp_free(t0);
103
    tcg_temp_free(t1);
104
}
105
#endif
106

    
107
/* SPR common to all PowerPC */
108
/* XER */
109
static void spr_read_xer (void *opaque, int gprn, int sprn)
110
{
111
    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
112
}
113

    
114
static void spr_write_xer (void *opaque, int sprn, int gprn)
115
{
116
    tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
117
}
118

    
119
/* LR */
120
static void spr_read_lr (void *opaque, int gprn, int sprn)
121
{
122
    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
123
}
124

    
125
static void spr_write_lr (void *opaque, int sprn, int gprn)
126
{
127
    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
128
}
129

    
130
/* CTR */
131
static void spr_read_ctr (void *opaque, int gprn, int sprn)
132
{
133
    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
134
}
135

    
136
static void spr_write_ctr (void *opaque, int sprn, int gprn)
137
{
138
    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
139
}
140

    
141
/* User read access to SPR */
142
/* USPRx */
143
/* UMMCRx */
144
/* UPMCx */
145
/* USIA */
146
/* UDECR */
147
static void spr_read_ureg (void *opaque, int gprn, int sprn)
148
{
149
    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
150
}
151

    
152
/* SPR common to all non-embedded PowerPC */
153
/* DECR */
154
#if !defined(CONFIG_USER_ONLY)
155
static void spr_read_decr (void *opaque, int gprn, int sprn)
156
{
157
    gen_helper_load_decr(cpu_gpr[gprn]);
158
}
159

    
160
static void spr_write_decr (void *opaque, int sprn, int gprn)
161
{
162
    gen_helper_store_decr(cpu_gpr[gprn]);
163
}
164
#endif
165

    
166
/* SPR common to all non-embedded PowerPC, except 601 */
167
/* Time base */
168
static void spr_read_tbl (void *opaque, int gprn, int sprn)
169
{
170
    gen_helper_load_tbl(cpu_gpr[gprn]);
171
}
172

    
173
static void spr_read_tbu (void *opaque, int gprn, int sprn)
174
{
175
    gen_helper_load_tbu(cpu_gpr[gprn]);
176
}
177

    
178
__attribute__ (( unused ))
179
static void spr_read_atbl (void *opaque, int gprn, int sprn)
180
{
181
    gen_helper_load_atbl(cpu_gpr[gprn]);
182
}
183

    
184
__attribute__ (( unused ))
185
static void spr_read_atbu (void *opaque, int gprn, int sprn)
186
{
187
    gen_helper_load_atbu(cpu_gpr[gprn]);
188
}
189

    
190
#if !defined(CONFIG_USER_ONLY)
191
static void spr_write_tbl (void *opaque, int sprn, int gprn)
192
{
193
    gen_helper_store_tbl(cpu_gpr[gprn]);
194
}
195

    
196
static void spr_write_tbu (void *opaque, int sprn, int gprn)
197
{
198
    gen_helper_store_tbu(cpu_gpr[gprn]);
199
}
200

    
201
__attribute__ (( unused ))
202
static void spr_write_atbl (void *opaque, int sprn, int gprn)
203
{
204
    gen_helper_store_atbl(cpu_gpr[gprn]);
205
}
206

    
207
__attribute__ (( unused ))
208
static void spr_write_atbu (void *opaque, int sprn, int gprn)
209
{
210
    gen_helper_store_atbu(cpu_gpr[gprn]);
211
}
212
#endif
213

    
214
#if !defined(CONFIG_USER_ONLY)
215
/* IBAT0U...IBAT0U */
216
/* IBAT0L...IBAT7L */
217
static void spr_read_ibat (void *opaque, int gprn, int sprn)
218
{
219
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
220
}
221

    
222
static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
223
{
224
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
225
}
226

    
227
static void spr_write_ibatu (void *opaque, int sprn, int gprn)
228
{
229
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
230
    gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
231
    tcg_temp_free_i32(t0);
232
}
233

    
234
static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
235
{
236
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
237
    gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
238
    tcg_temp_free_i32(t0);
239
}
240

    
241
static void spr_write_ibatl (void *opaque, int sprn, int gprn)
242
{
243
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
244
    gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
245
    tcg_temp_free_i32(t0);
246
}
247

    
248
static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
249
{
250
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
251
    gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
252
    tcg_temp_free_i32(t0);
253
}
254

    
255
/* DBAT0U...DBAT7U */
256
/* DBAT0L...DBAT7L */
257
static void spr_read_dbat (void *opaque, int gprn, int sprn)
258
{
259
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
260
}
261

    
262
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
263
{
264
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
265
}
266

    
267
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
268
{
269
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
270
    gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
271
    tcg_temp_free_i32(t0);
272
}
273

    
274
static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
275
{
276
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
277
    gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
278
    tcg_temp_free_i32(t0);
279
}
280

    
281
static void spr_write_dbatl (void *opaque, int sprn, int gprn)
282
{
283
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
284
    gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
285
    tcg_temp_free_i32(t0);
286
}
287

    
288
static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
289
{
290
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
291
    gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
292
    tcg_temp_free_i32(t0);
293
}
294

    
295
/* SDR1 */
296
static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
297
{
298
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
299
}
300

    
301
static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
302
{
303
    gen_helper_store_sdr1(cpu_gpr[gprn]);
304
}
305

    
306
/* 64 bits PowerPC specific SPRs */
307
/* ASR */
308
#if defined(TARGET_PPC64)
309
static void spr_read_hior (void *opaque, int gprn, int sprn)
310
{
311
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
312
}
313

    
314
static void spr_write_hior (void *opaque, int sprn, int gprn)
315
{
316
    TCGv t0 = tcg_temp_new();
317
    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
318
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
319
    tcg_temp_free(t0);
320
}
321

    
322
static void spr_read_asr (void *opaque, int gprn, int sprn)
323
{
324
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
325
}
326

    
327
static void spr_write_asr (void *opaque, int sprn, int gprn)
328
{
329
    gen_helper_store_asr(cpu_gpr[gprn]);
330
}
331
#endif
332
#endif
333

    
334
/* PowerPC 601 specific registers */
335
/* RTC */
336
static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
337
{
338
    gen_helper_load_601_rtcl(cpu_gpr[gprn]);
339
}
340

    
341
static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
342
{
343
    gen_helper_load_601_rtcu(cpu_gpr[gprn]);
344
}
345

    
346
#if !defined(CONFIG_USER_ONLY)
347
static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
348
{
349
    gen_helper_store_601_rtcu(cpu_gpr[gprn]);
350
}
351

    
352
static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
353
{
354
    gen_helper_store_601_rtcl(cpu_gpr[gprn]);
355
}
356

    
357
static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
358
{
359
    DisasContext *ctx = opaque;
360

    
361
    gen_helper_store_hid0_601(cpu_gpr[gprn]);
362
    /* Must stop the translation as endianness may have changed */
363
    gen_stop_exception(ctx);
364
}
365
#endif
366

    
367
/* Unified bats */
368
#if !defined(CONFIG_USER_ONLY)
369
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
370
{
371
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
372
}
373

    
374
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
375
{
376
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
377
    gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
378
    tcg_temp_free_i32(t0);
379
}
380

    
381
static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
382
{
383
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
384
    gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
385
    tcg_temp_free_i32(t0);
386
}
387
#endif
388

    
389
/* PowerPC 40x specific registers */
390
#if !defined(CONFIG_USER_ONLY)
391
static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
392
{
393
    gen_helper_load_40x_pit(cpu_gpr[gprn]);
394
}
395

    
396
static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
397
{
398
    gen_helper_store_40x_pit(cpu_gpr[gprn]);
399
}
400

    
401
static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
402
{
403
    DisasContext *ctx = opaque;
404

    
405
    gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
406
    /* We must stop translation as we may have rebooted */
407
    gen_stop_exception(ctx);
408
}
409

    
410
static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
411
{
412
    gen_helper_store_40x_sler(cpu_gpr[gprn]);
413
}
414

    
415
static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
416
{
417
    gen_helper_store_booke_tcr(cpu_gpr[gprn]);
418
}
419

    
420
static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
421
{
422
    gen_helper_store_booke_tsr(cpu_gpr[gprn]);
423
}
424
#endif
425

    
426
/* PowerPC 403 specific registers */
427
/* PBL1 / PBU1 / PBL2 / PBU2 */
428
#if !defined(CONFIG_USER_ONLY)
429
static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
430
{
431
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
432
}
433

    
434
static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
435
{
436
    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
437
    gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
438
    tcg_temp_free_i32(t0);
439
}
440

    
441
static void spr_write_pir (void *opaque, int sprn, int gprn)
442
{
443
    TCGv t0 = tcg_temp_new();
444
    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
445
    gen_store_spr(SPR_PIR, t0);
446
    tcg_temp_free(t0);
447
}
448
#endif
449

    
450
/* SPE specific registers */
451
static void spr_read_spefscr (void *opaque, int gprn, int sprn)
452
{
453
    TCGv_i32 t0 = tcg_temp_new_i32();
454
    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
455
    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
456
    tcg_temp_free_i32(t0);
457
}
458

    
459
static void spr_write_spefscr (void *opaque, int sprn, int gprn)
460
{
461
    TCGv_i32 t0 = tcg_temp_new_i32();
462
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
463
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
464
    tcg_temp_free_i32(t0);
465
}
466

    
467
#if !defined(CONFIG_USER_ONLY)
468
/* Callback used to write the exception vector base */
469
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
470
{
471
    TCGv t0 = tcg_temp_new();
472
    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
473
    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
474
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
475
    gen_store_spr(sprn, t0);
476
    tcg_temp_free(t0);
477
}
478

    
479
static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
480
{
481
    DisasContext *ctx = opaque;
482

    
483
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
484
        TCGv t0 = tcg_temp_new();
485
        tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
486
        tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
487
        tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
488
        gen_store_spr(sprn, t0);
489
        tcg_temp_free(t0);
490
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
491
        TCGv t0 = tcg_temp_new();
492
        tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
493
        tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
494
        tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
495
        gen_store_spr(sprn, t0);
496
        tcg_temp_free(t0);
497
    } else {
498
        printf("Trying to write an unknown exception vector %d %03x\n",
499
               sprn, sprn);
500
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
501
    }
502
}
503
#endif
504

    
505
static inline void vscr_init (CPUPPCState *env, uint32_t val)
506
{
507
    env->vscr = val;
508
    /* Altivec always uses round-to-nearest */
509
    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
510
    set_flush_to_zero(vscr_nj, &env->vec_status);
511
}
512

    
513
#if defined(CONFIG_USER_ONLY)
514
#define spr_register(env, num, name, uea_read, uea_write,                     \
515
                     oea_read, oea_write, initial_value)                      \
516
do {                                                                          \
517
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
518
} while (0)
519
static inline void _spr_register (CPUPPCState *env, int num,
520
                                  const char *name,
521
                                  void (*uea_read)(void *opaque, int gprn, int sprn),
522
                                  void (*uea_write)(void *opaque, int sprn, int gprn),
523
                                  target_ulong initial_value)
524
#else
525
static inline void spr_register (CPUPPCState *env, int num,
526
                                 const char *name,
527
                                 void (*uea_read)(void *opaque, int gprn, int sprn),
528
                                 void (*uea_write)(void *opaque, int sprn, int gprn),
529
                                 void (*oea_read)(void *opaque, int gprn, int sprn),
530
                                 void (*oea_write)(void *opaque, int sprn, int gprn),
531
                                 target_ulong initial_value)
532
#endif
533
{
534
    ppc_spr_t *spr;
535

    
536
    spr = &env->spr_cb[num];
537
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
538
#if !defined(CONFIG_USER_ONLY)
539
        spr->oea_read != NULL || spr->oea_write != NULL ||
540
#endif
541
        spr->uea_read != NULL || spr->uea_write != NULL) {
542
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
543
        exit(1);
544
    }
545
#if defined(PPC_DEBUG_SPR)
546
    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
547
           name, initial_value);
548
#endif
549
    spr->name = name;
550
    spr->uea_read = uea_read;
551
    spr->uea_write = uea_write;
552
#if !defined(CONFIG_USER_ONLY)
553
    spr->oea_read = oea_read;
554
    spr->oea_write = oea_write;
555
#endif
556
    env->spr[num] = initial_value;
557
}
558

    
559
/* Generic PowerPC SPRs */
560
static void gen_spr_generic (CPUPPCState *env)
561
{
562
    /* Integer processing */
563
    spr_register(env, SPR_XER, "XER",
564
                 &spr_read_xer, &spr_write_xer,
565
                 &spr_read_xer, &spr_write_xer,
566
                 0x00000000);
567
    /* Branch contol */
568
    spr_register(env, SPR_LR, "LR",
569
                 &spr_read_lr, &spr_write_lr,
570
                 &spr_read_lr, &spr_write_lr,
571
                 0x00000000);
572
    spr_register(env, SPR_CTR, "CTR",
573
                 &spr_read_ctr, &spr_write_ctr,
574
                 &spr_read_ctr, &spr_write_ctr,
575
                 0x00000000);
576
    /* Interrupt processing */
577
    spr_register(env, SPR_SRR0, "SRR0",
578
                 SPR_NOACCESS, SPR_NOACCESS,
579
                 &spr_read_generic, &spr_write_generic,
580
                 0x00000000);
581
    spr_register(env, SPR_SRR1, "SRR1",
582
                 SPR_NOACCESS, SPR_NOACCESS,
583
                 &spr_read_generic, &spr_write_generic,
584
                 0x00000000);
585
    /* Processor control */
586
    spr_register(env, SPR_SPRG0, "SPRG0",
587
                 SPR_NOACCESS, SPR_NOACCESS,
588
                 &spr_read_generic, &spr_write_generic,
589
                 0x00000000);
590
    spr_register(env, SPR_SPRG1, "SPRG1",
591
                 SPR_NOACCESS, SPR_NOACCESS,
592
                 &spr_read_generic, &spr_write_generic,
593
                 0x00000000);
594
    spr_register(env, SPR_SPRG2, "SPRG2",
595
                 SPR_NOACCESS, SPR_NOACCESS,
596
                 &spr_read_generic, &spr_write_generic,
597
                 0x00000000);
598
    spr_register(env, SPR_SPRG3, "SPRG3",
599
                 SPR_NOACCESS, SPR_NOACCESS,
600
                 &spr_read_generic, &spr_write_generic,
601
                 0x00000000);
602
}
603

    
604
/* SPR common to all non-embedded PowerPC, including 601 */
605
static void gen_spr_ne_601 (CPUPPCState *env)
606
{
607
    /* Exception processing */
608
    spr_register(env, SPR_DSISR, "DSISR",
609
                 SPR_NOACCESS, SPR_NOACCESS,
610
                 &spr_read_generic, &spr_write_generic,
611
                 0x00000000);
612
    spr_register(env, SPR_DAR, "DAR",
613
                 SPR_NOACCESS, SPR_NOACCESS,
614
                 &spr_read_generic, &spr_write_generic,
615
                 0x00000000);
616
    /* Timer */
617
    spr_register(env, SPR_DECR, "DECR",
618
                 SPR_NOACCESS, SPR_NOACCESS,
619
                 &spr_read_decr, &spr_write_decr,
620
                 0x00000000);
621
    /* Memory management */
622
    spr_register(env, SPR_SDR1, "SDR1",
623
                 SPR_NOACCESS, SPR_NOACCESS,
624
                 &spr_read_sdr1, &spr_write_sdr1,
625
                 0x00000000);
626
}
627

    
628
/* BATs 0-3 */
629
static void gen_low_BATs (CPUPPCState *env)
630
{
631
#if !defined(CONFIG_USER_ONLY)
632
    spr_register(env, SPR_IBAT0U, "IBAT0U",
633
                 SPR_NOACCESS, SPR_NOACCESS,
634
                 &spr_read_ibat, &spr_write_ibatu,
635
                 0x00000000);
636
    spr_register(env, SPR_IBAT0L, "IBAT0L",
637
                 SPR_NOACCESS, SPR_NOACCESS,
638
                 &spr_read_ibat, &spr_write_ibatl,
639
                 0x00000000);
640
    spr_register(env, SPR_IBAT1U, "IBAT1U",
641
                 SPR_NOACCESS, SPR_NOACCESS,
642
                 &spr_read_ibat, &spr_write_ibatu,
643
                 0x00000000);
644
    spr_register(env, SPR_IBAT1L, "IBAT1L",
645
                 SPR_NOACCESS, SPR_NOACCESS,
646
                 &spr_read_ibat, &spr_write_ibatl,
647
                 0x00000000);
648
    spr_register(env, SPR_IBAT2U, "IBAT2U",
649
                 SPR_NOACCESS, SPR_NOACCESS,
650
                 &spr_read_ibat, &spr_write_ibatu,
651
                 0x00000000);
652
    spr_register(env, SPR_IBAT2L, "IBAT2L",
653
                 SPR_NOACCESS, SPR_NOACCESS,
654
                 &spr_read_ibat, &spr_write_ibatl,
655
                 0x00000000);
656
    spr_register(env, SPR_IBAT3U, "IBAT3U",
657
                 SPR_NOACCESS, SPR_NOACCESS,
658
                 &spr_read_ibat, &spr_write_ibatu,
659
                 0x00000000);
660
    spr_register(env, SPR_IBAT3L, "IBAT3L",
661
                 SPR_NOACCESS, SPR_NOACCESS,
662
                 &spr_read_ibat, &spr_write_ibatl,
663
                 0x00000000);
664
    spr_register(env, SPR_DBAT0U, "DBAT0U",
665
                 SPR_NOACCESS, SPR_NOACCESS,
666
                 &spr_read_dbat, &spr_write_dbatu,
667
                 0x00000000);
668
    spr_register(env, SPR_DBAT0L, "DBAT0L",
669
                 SPR_NOACCESS, SPR_NOACCESS,
670
                 &spr_read_dbat, &spr_write_dbatl,
671
                 0x00000000);
672
    spr_register(env, SPR_DBAT1U, "DBAT1U",
673
                 SPR_NOACCESS, SPR_NOACCESS,
674
                 &spr_read_dbat, &spr_write_dbatu,
675
                 0x00000000);
676
    spr_register(env, SPR_DBAT1L, "DBAT1L",
677
                 SPR_NOACCESS, SPR_NOACCESS,
678
                 &spr_read_dbat, &spr_write_dbatl,
679
                 0x00000000);
680
    spr_register(env, SPR_DBAT2U, "DBAT2U",
681
                 SPR_NOACCESS, SPR_NOACCESS,
682
                 &spr_read_dbat, &spr_write_dbatu,
683
                 0x00000000);
684
    spr_register(env, SPR_DBAT2L, "DBAT2L",
685
                 SPR_NOACCESS, SPR_NOACCESS,
686
                 &spr_read_dbat, &spr_write_dbatl,
687
                 0x00000000);
688
    spr_register(env, SPR_DBAT3U, "DBAT3U",
689
                 SPR_NOACCESS, SPR_NOACCESS,
690
                 &spr_read_dbat, &spr_write_dbatu,
691
                 0x00000000);
692
    spr_register(env, SPR_DBAT3L, "DBAT3L",
693
                 SPR_NOACCESS, SPR_NOACCESS,
694
                 &spr_read_dbat, &spr_write_dbatl,
695
                 0x00000000);
696
    env->nb_BATs += 4;
697
#endif
698
}
699

    
700
/* BATs 4-7 */
701
static void gen_high_BATs (CPUPPCState *env)
702
{
703
#if !defined(CONFIG_USER_ONLY)
704
    spr_register(env, SPR_IBAT4U, "IBAT4U",
705
                 SPR_NOACCESS, SPR_NOACCESS,
706
                 &spr_read_ibat_h, &spr_write_ibatu_h,
707
                 0x00000000);
708
    spr_register(env, SPR_IBAT4L, "IBAT4L",
709
                 SPR_NOACCESS, SPR_NOACCESS,
710
                 &spr_read_ibat_h, &spr_write_ibatl_h,
711
                 0x00000000);
712
    spr_register(env, SPR_IBAT5U, "IBAT5U",
713
                 SPR_NOACCESS, SPR_NOACCESS,
714
                 &spr_read_ibat_h, &spr_write_ibatu_h,
715
                 0x00000000);
716
    spr_register(env, SPR_IBAT5L, "IBAT5L",
717
                 SPR_NOACCESS, SPR_NOACCESS,
718
                 &spr_read_ibat_h, &spr_write_ibatl_h,
719
                 0x00000000);
720
    spr_register(env, SPR_IBAT6U, "IBAT6U",
721
                 SPR_NOACCESS, SPR_NOACCESS,
722
                 &spr_read_ibat_h, &spr_write_ibatu_h,
723
                 0x00000000);
724
    spr_register(env, SPR_IBAT6L, "IBAT6L",
725
                 SPR_NOACCESS, SPR_NOACCESS,
726
                 &spr_read_ibat_h, &spr_write_ibatl_h,
727
                 0x00000000);
728
    spr_register(env, SPR_IBAT7U, "IBAT7U",
729
                 SPR_NOACCESS, SPR_NOACCESS,
730
                 &spr_read_ibat_h, &spr_write_ibatu_h,
731
                 0x00000000);
732
    spr_register(env, SPR_IBAT7L, "IBAT7L",
733
                 SPR_NOACCESS, SPR_NOACCESS,
734
                 &spr_read_ibat_h, &spr_write_ibatl_h,
735
                 0x00000000);
736
    spr_register(env, SPR_DBAT4U, "DBAT4U",
737
                 SPR_NOACCESS, SPR_NOACCESS,
738
                 &spr_read_dbat_h, &spr_write_dbatu_h,
739
                 0x00000000);
740
    spr_register(env, SPR_DBAT4L, "DBAT4L",
741
                 SPR_NOACCESS, SPR_NOACCESS,
742
                 &spr_read_dbat_h, &spr_write_dbatl_h,
743
                 0x00000000);
744
    spr_register(env, SPR_DBAT5U, "DBAT5U",
745
                 SPR_NOACCESS, SPR_NOACCESS,
746
                 &spr_read_dbat_h, &spr_write_dbatu_h,
747
                 0x00000000);
748
    spr_register(env, SPR_DBAT5L, "DBAT5L",
749
                 SPR_NOACCESS, SPR_NOACCESS,
750
                 &spr_read_dbat_h, &spr_write_dbatl_h,
751
                 0x00000000);
752
    spr_register(env, SPR_DBAT6U, "DBAT6U",
753
                 SPR_NOACCESS, SPR_NOACCESS,
754
                 &spr_read_dbat_h, &spr_write_dbatu_h,
755
                 0x00000000);
756
    spr_register(env, SPR_DBAT6L, "DBAT6L",
757
                 SPR_NOACCESS, SPR_NOACCESS,
758
                 &spr_read_dbat_h, &spr_write_dbatl_h,
759
                 0x00000000);
760
    spr_register(env, SPR_DBAT7U, "DBAT7U",
761
                 SPR_NOACCESS, SPR_NOACCESS,
762
                 &spr_read_dbat_h, &spr_write_dbatu_h,
763
                 0x00000000);
764
    spr_register(env, SPR_DBAT7L, "DBAT7L",
765
                 SPR_NOACCESS, SPR_NOACCESS,
766
                 &spr_read_dbat_h, &spr_write_dbatl_h,
767
                 0x00000000);
768
    env->nb_BATs += 4;
769
#endif
770
}
771

    
772
/* Generic PowerPC time base */
773
static void gen_tbl (CPUPPCState *env)
774
{
775
    spr_register(env, SPR_VTBL,  "TBL",
776
                 &spr_read_tbl, SPR_NOACCESS,
777
                 &spr_read_tbl, SPR_NOACCESS,
778
                 0x00000000);
779
    spr_register(env, SPR_TBL,   "TBL",
780
                 &spr_read_tbl, SPR_NOACCESS,
781
                 &spr_read_tbl, &spr_write_tbl,
782
                 0x00000000);
783
    spr_register(env, SPR_VTBU,  "TBU",
784
                 &spr_read_tbu, SPR_NOACCESS,
785
                 &spr_read_tbu, SPR_NOACCESS,
786
                 0x00000000);
787
    spr_register(env, SPR_TBU,   "TBU",
788
                 &spr_read_tbu, SPR_NOACCESS,
789
                 &spr_read_tbu, &spr_write_tbu,
790
                 0x00000000);
791
}
792

    
793
/* Softare table search registers */
794
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
795
{
796
#if !defined(CONFIG_USER_ONLY)
797
    env->nb_tlb = nb_tlbs;
798
    env->nb_ways = nb_ways;
799
    env->id_tlbs = 1;
800
    spr_register(env, SPR_DMISS, "DMISS",
801
                 SPR_NOACCESS, SPR_NOACCESS,
802
                 &spr_read_generic, SPR_NOACCESS,
803
                 0x00000000);
804
    spr_register(env, SPR_DCMP, "DCMP",
805
                 SPR_NOACCESS, SPR_NOACCESS,
806
                 &spr_read_generic, SPR_NOACCESS,
807
                 0x00000000);
808
    spr_register(env, SPR_HASH1, "HASH1",
809
                 SPR_NOACCESS, SPR_NOACCESS,
810
                 &spr_read_generic, SPR_NOACCESS,
811
                 0x00000000);
812
    spr_register(env, SPR_HASH2, "HASH2",
813
                 SPR_NOACCESS, SPR_NOACCESS,
814
                 &spr_read_generic, SPR_NOACCESS,
815
                 0x00000000);
816
    spr_register(env, SPR_IMISS, "IMISS",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, SPR_NOACCESS,
819
                 0x00000000);
820
    spr_register(env, SPR_ICMP, "ICMP",
821
                 SPR_NOACCESS, SPR_NOACCESS,
822
                 &spr_read_generic, SPR_NOACCESS,
823
                 0x00000000);
824
    spr_register(env, SPR_RPA, "RPA",
825
                 SPR_NOACCESS, SPR_NOACCESS,
826
                 &spr_read_generic, &spr_write_generic,
827
                 0x00000000);
828
#endif
829
}
830

    
831
/* SPR common to MPC755 and G2 */
832
static void gen_spr_G2_755 (CPUPPCState *env)
833
{
834
    /* SGPRs */
835
    spr_register(env, SPR_SPRG4, "SPRG4",
836
                 SPR_NOACCESS, SPR_NOACCESS,
837
                 &spr_read_generic, &spr_write_generic,
838
                 0x00000000);
839
    spr_register(env, SPR_SPRG5, "SPRG5",
840
                 SPR_NOACCESS, SPR_NOACCESS,
841
                 &spr_read_generic, &spr_write_generic,
842
                 0x00000000);
843
    spr_register(env, SPR_SPRG6, "SPRG6",
844
                 SPR_NOACCESS, SPR_NOACCESS,
845
                 &spr_read_generic, &spr_write_generic,
846
                 0x00000000);
847
    spr_register(env, SPR_SPRG7, "SPRG7",
848
                 SPR_NOACCESS, SPR_NOACCESS,
849
                 &spr_read_generic, &spr_write_generic,
850
                 0x00000000);
851
}
852

    
853
/* SPR common to all 7xx PowerPC implementations */
854
static void gen_spr_7xx (CPUPPCState *env)
855
{
856
    /* Breakpoints */
857
    /* XXX : not implemented */
858
    spr_register(env, SPR_DABR, "DABR",
859
                 SPR_NOACCESS, SPR_NOACCESS,
860
                 &spr_read_generic, &spr_write_generic,
861
                 0x00000000);
862
    /* XXX : not implemented */
863
    spr_register(env, SPR_IABR, "IABR",
864
                 SPR_NOACCESS, SPR_NOACCESS,
865
                 &spr_read_generic, &spr_write_generic,
866
                 0x00000000);
867
    /* Cache management */
868
    /* XXX : not implemented */
869
    spr_register(env, SPR_ICTC, "ICTC",
870
                 SPR_NOACCESS, SPR_NOACCESS,
871
                 &spr_read_generic, &spr_write_generic,
872
                 0x00000000);
873
    /* Performance monitors */
874
    /* XXX : not implemented */
875
    spr_register(env, SPR_MMCR0, "MMCR0",
876
                 SPR_NOACCESS, SPR_NOACCESS,
877
                 &spr_read_generic, &spr_write_generic,
878
                 0x00000000);
879
    /* XXX : not implemented */
880
    spr_register(env, SPR_MMCR1, "MMCR1",
881
                 SPR_NOACCESS, SPR_NOACCESS,
882
                 &spr_read_generic, &spr_write_generic,
883
                 0x00000000);
884
    /* XXX : not implemented */
885
    spr_register(env, SPR_PMC1, "PMC1",
886
                 SPR_NOACCESS, SPR_NOACCESS,
887
                 &spr_read_generic, &spr_write_generic,
888
                 0x00000000);
889
    /* XXX : not implemented */
890
    spr_register(env, SPR_PMC2, "PMC2",
891
                 SPR_NOACCESS, SPR_NOACCESS,
892
                 &spr_read_generic, &spr_write_generic,
893
                 0x00000000);
894
    /* XXX : not implemented */
895
    spr_register(env, SPR_PMC3, "PMC3",
896
                 SPR_NOACCESS, SPR_NOACCESS,
897
                 &spr_read_generic, &spr_write_generic,
898
                 0x00000000);
899
    /* XXX : not implemented */
900
    spr_register(env, SPR_PMC4, "PMC4",
901
                 SPR_NOACCESS, SPR_NOACCESS,
902
                 &spr_read_generic, &spr_write_generic,
903
                 0x00000000);
904
    /* XXX : not implemented */
905
    spr_register(env, SPR_SIAR, "SIAR",
906
                 SPR_NOACCESS, SPR_NOACCESS,
907
                 &spr_read_generic, SPR_NOACCESS,
908
                 0x00000000);
909
    /* XXX : not implemented */
910
    spr_register(env, SPR_UMMCR0, "UMMCR0",
911
                 &spr_read_ureg, SPR_NOACCESS,
912
                 &spr_read_ureg, SPR_NOACCESS,
913
                 0x00000000);
914
    /* XXX : not implemented */
915
    spr_register(env, SPR_UMMCR1, "UMMCR1",
916
                 &spr_read_ureg, SPR_NOACCESS,
917
                 &spr_read_ureg, SPR_NOACCESS,
918
                 0x00000000);
919
    /* XXX : not implemented */
920
    spr_register(env, SPR_UPMC1, "UPMC1",
921
                 &spr_read_ureg, SPR_NOACCESS,
922
                 &spr_read_ureg, SPR_NOACCESS,
923
                 0x00000000);
924
    /* XXX : not implemented */
925
    spr_register(env, SPR_UPMC2, "UPMC2",
926
                 &spr_read_ureg, SPR_NOACCESS,
927
                 &spr_read_ureg, SPR_NOACCESS,
928
                 0x00000000);
929
    /* XXX : not implemented */
930
    spr_register(env, SPR_UPMC3, "UPMC3",
931
                 &spr_read_ureg, SPR_NOACCESS,
932
                 &spr_read_ureg, SPR_NOACCESS,
933
                 0x00000000);
934
    /* XXX : not implemented */
935
    spr_register(env, SPR_UPMC4, "UPMC4",
936
                 &spr_read_ureg, SPR_NOACCESS,
937
                 &spr_read_ureg, SPR_NOACCESS,
938
                 0x00000000);
939
    /* XXX : not implemented */
940
    spr_register(env, SPR_USIAR, "USIAR",
941
                 &spr_read_ureg, SPR_NOACCESS,
942
                 &spr_read_ureg, SPR_NOACCESS,
943
                 0x00000000);
944
    /* External access control */
945
    /* XXX : not implemented */
946
    spr_register(env, SPR_EAR, "EAR",
947
                 SPR_NOACCESS, SPR_NOACCESS,
948
                 &spr_read_generic, &spr_write_generic,
949
                 0x00000000);
950
}
951

    
952
static void gen_spr_thrm (CPUPPCState *env)
953
{
954
    /* Thermal management */
955
    /* XXX : not implemented */
956
    spr_register(env, SPR_THRM1, "THRM1",
957
                 SPR_NOACCESS, SPR_NOACCESS,
958
                 &spr_read_generic, &spr_write_generic,
959
                 0x00000000);
960
    /* XXX : not implemented */
961
    spr_register(env, SPR_THRM2, "THRM2",
962
                 SPR_NOACCESS, SPR_NOACCESS,
963
                 &spr_read_generic, &spr_write_generic,
964
                 0x00000000);
965
    /* XXX : not implemented */
966
    spr_register(env, SPR_THRM3, "THRM3",
967
                 SPR_NOACCESS, SPR_NOACCESS,
968
                 &spr_read_generic, &spr_write_generic,
969
                 0x00000000);
970
}
971

    
972
/* SPR specific to PowerPC 604 implementation */
973
static void gen_spr_604 (CPUPPCState *env)
974
{
975
    /* Processor identification */
976
    spr_register(env, SPR_PIR, "PIR",
977
                 SPR_NOACCESS, SPR_NOACCESS,
978
                 &spr_read_generic, &spr_write_pir,
979
                 0x00000000);
980
    /* Breakpoints */
981
    /* XXX : not implemented */
982
    spr_register(env, SPR_IABR, "IABR",
983
                 SPR_NOACCESS, SPR_NOACCESS,
984
                 &spr_read_generic, &spr_write_generic,
985
                 0x00000000);
986
    /* XXX : not implemented */
987
    spr_register(env, SPR_DABR, "DABR",
988
                 SPR_NOACCESS, SPR_NOACCESS,
989
                 &spr_read_generic, &spr_write_generic,
990
                 0x00000000);
991
    /* Performance counters */
992
    /* XXX : not implemented */
993
    spr_register(env, SPR_MMCR0, "MMCR0",
994
                 SPR_NOACCESS, SPR_NOACCESS,
995
                 &spr_read_generic, &spr_write_generic,
996
                 0x00000000);
997
    /* XXX : not implemented */
998
    spr_register(env, SPR_PMC1, "PMC1",
999
                 SPR_NOACCESS, SPR_NOACCESS,
1000
                 &spr_read_generic, &spr_write_generic,
1001
                 0x00000000);
1002
    /* XXX : not implemented */
1003
    spr_register(env, SPR_PMC2, "PMC2",
1004
                 SPR_NOACCESS, SPR_NOACCESS,
1005
                 &spr_read_generic, &spr_write_generic,
1006
                 0x00000000);
1007
    /* XXX : not implemented */
1008
    spr_register(env, SPR_SIAR, "SIAR",
1009
                 SPR_NOACCESS, SPR_NOACCESS,
1010
                 &spr_read_generic, SPR_NOACCESS,
1011
                 0x00000000);
1012
    /* XXX : not implemented */
1013
    spr_register(env, SPR_SDA, "SDA",
1014
                 SPR_NOACCESS, SPR_NOACCESS,
1015
                 &spr_read_generic, SPR_NOACCESS,
1016
                 0x00000000);
1017
    /* External access control */
1018
    /* XXX : not implemented */
1019
    spr_register(env, SPR_EAR, "EAR",
1020
                 SPR_NOACCESS, SPR_NOACCESS,
1021
                 &spr_read_generic, &spr_write_generic,
1022
                 0x00000000);
1023
}
1024

    
1025
/* SPR specific to PowerPC 603 implementation */
1026
static void gen_spr_603 (CPUPPCState *env)
1027
{
1028
    /* External access control */
1029
    /* XXX : not implemented */
1030
    spr_register(env, SPR_EAR, "EAR",
1031
                 SPR_NOACCESS, SPR_NOACCESS,
1032
                 &spr_read_generic, &spr_write_generic,
1033
                 0x00000000);
1034
}
1035

    
1036
/* SPR specific to PowerPC G2 implementation */
1037
static void gen_spr_G2 (CPUPPCState *env)
1038
{
1039
    /* Memory base address */
1040
    /* MBAR */
1041
    /* XXX : not implemented */
1042
    spr_register(env, SPR_MBAR, "MBAR",
1043
                 SPR_NOACCESS, SPR_NOACCESS,
1044
                 &spr_read_generic, &spr_write_generic,
1045
                 0x00000000);
1046
    /* Exception processing */
1047
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1048
                 SPR_NOACCESS, SPR_NOACCESS,
1049
                 &spr_read_generic, &spr_write_generic,
1050
                 0x00000000);
1051
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1052
                 SPR_NOACCESS, SPR_NOACCESS,
1053
                 &spr_read_generic, &spr_write_generic,
1054
                 0x00000000);
1055
    /* Breakpoints */
1056
    /* XXX : not implemented */
1057
    spr_register(env, SPR_DABR, "DABR",
1058
                 SPR_NOACCESS, SPR_NOACCESS,
1059
                 &spr_read_generic, &spr_write_generic,
1060
                 0x00000000);
1061
    /* XXX : not implemented */
1062
    spr_register(env, SPR_DABR2, "DABR2",
1063
                 SPR_NOACCESS, SPR_NOACCESS,
1064
                 &spr_read_generic, &spr_write_generic,
1065
                 0x00000000);
1066
    /* XXX : not implemented */
1067
    spr_register(env, SPR_IABR, "IABR",
1068
                 SPR_NOACCESS, SPR_NOACCESS,
1069
                 &spr_read_generic, &spr_write_generic,
1070
                 0x00000000);
1071
    /* XXX : not implemented */
1072
    spr_register(env, SPR_IABR2, "IABR2",
1073
                 SPR_NOACCESS, SPR_NOACCESS,
1074
                 &spr_read_generic, &spr_write_generic,
1075
                 0x00000000);
1076
    /* XXX : not implemented */
1077
    spr_register(env, SPR_IBCR, "IBCR",
1078
                 SPR_NOACCESS, SPR_NOACCESS,
1079
                 &spr_read_generic, &spr_write_generic,
1080
                 0x00000000);
1081
    /* XXX : not implemented */
1082
    spr_register(env, SPR_DBCR, "DBCR",
1083
                 SPR_NOACCESS, SPR_NOACCESS,
1084
                 &spr_read_generic, &spr_write_generic,
1085
                 0x00000000);
1086
}
1087

    
1088
/* SPR specific to PowerPC 602 implementation */
1089
static void gen_spr_602 (CPUPPCState *env)
1090
{
1091
    /* ESA registers */
1092
    /* XXX : not implemented */
1093
    spr_register(env, SPR_SER, "SER",
1094
                 SPR_NOACCESS, SPR_NOACCESS,
1095
                 &spr_read_generic, &spr_write_generic,
1096
                 0x00000000);
1097
    /* XXX : not implemented */
1098
    spr_register(env, SPR_SEBR, "SEBR",
1099
                 SPR_NOACCESS, SPR_NOACCESS,
1100
                 &spr_read_generic, &spr_write_generic,
1101
                 0x00000000);
1102
    /* XXX : not implemented */
1103
    spr_register(env, SPR_ESASRR, "ESASRR",
1104
                 SPR_NOACCESS, SPR_NOACCESS,
1105
                 &spr_read_generic, &spr_write_generic,
1106
                 0x00000000);
1107
    /* Floating point status */
1108
    /* XXX : not implemented */
1109
    spr_register(env, SPR_SP, "SP",
1110
                 SPR_NOACCESS, SPR_NOACCESS,
1111
                 &spr_read_generic, &spr_write_generic,
1112
                 0x00000000);
1113
    /* XXX : not implemented */
1114
    spr_register(env, SPR_LT, "LT",
1115
                 SPR_NOACCESS, SPR_NOACCESS,
1116
                 &spr_read_generic, &spr_write_generic,
1117
                 0x00000000);
1118
    /* Watchdog timer */
1119
    /* XXX : not implemented */
1120
    spr_register(env, SPR_TCR, "TCR",
1121
                 SPR_NOACCESS, SPR_NOACCESS,
1122
                 &spr_read_generic, &spr_write_generic,
1123
                 0x00000000);
1124
    /* Interrupt base */
1125
    spr_register(env, SPR_IBR, "IBR",
1126
                 SPR_NOACCESS, SPR_NOACCESS,
1127
                 &spr_read_generic, &spr_write_generic,
1128
                 0x00000000);
1129
    /* XXX : not implemented */
1130
    spr_register(env, SPR_IABR, "IABR",
1131
                 SPR_NOACCESS, SPR_NOACCESS,
1132
                 &spr_read_generic, &spr_write_generic,
1133
                 0x00000000);
1134
}
1135

    
1136
/* SPR specific to PowerPC 601 implementation */
1137
static void gen_spr_601 (CPUPPCState *env)
1138
{
1139
    /* Multiplication/division register */
1140
    /* MQ */
1141
    spr_register(env, SPR_MQ, "MQ",
1142
                 &spr_read_generic, &spr_write_generic,
1143
                 &spr_read_generic, &spr_write_generic,
1144
                 0x00000000);
1145
    /* RTC registers */
1146
    spr_register(env, SPR_601_RTCU, "RTCU",
1147
                 SPR_NOACCESS, SPR_NOACCESS,
1148
                 SPR_NOACCESS, &spr_write_601_rtcu,
1149
                 0x00000000);
1150
    spr_register(env, SPR_601_VRTCU, "RTCU",
1151
                 &spr_read_601_rtcu, SPR_NOACCESS,
1152
                 &spr_read_601_rtcu, SPR_NOACCESS,
1153
                 0x00000000);
1154
    spr_register(env, SPR_601_RTCL, "RTCL",
1155
                 SPR_NOACCESS, SPR_NOACCESS,
1156
                 SPR_NOACCESS, &spr_write_601_rtcl,
1157
                 0x00000000);
1158
    spr_register(env, SPR_601_VRTCL, "RTCL",
1159
                 &spr_read_601_rtcl, SPR_NOACCESS,
1160
                 &spr_read_601_rtcl, SPR_NOACCESS,
1161
                 0x00000000);
1162
    /* Timer */
1163
#if 0 /* ? */
1164
    spr_register(env, SPR_601_UDECR, "UDECR",
1165
                 &spr_read_decr, SPR_NOACCESS,
1166
                 &spr_read_decr, SPR_NOACCESS,
1167
                 0x00000000);
1168
#endif
1169
    /* External access control */
1170
    /* XXX : not implemented */
1171
    spr_register(env, SPR_EAR, "EAR",
1172
                 SPR_NOACCESS, SPR_NOACCESS,
1173
                 &spr_read_generic, &spr_write_generic,
1174
                 0x00000000);
1175
    /* Memory management */
1176
#if !defined(CONFIG_USER_ONLY)
1177
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1178
                 SPR_NOACCESS, SPR_NOACCESS,
1179
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1180
                 0x00000000);
1181
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1182
                 SPR_NOACCESS, SPR_NOACCESS,
1183
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1184
                 0x00000000);
1185
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1186
                 SPR_NOACCESS, SPR_NOACCESS,
1187
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1188
                 0x00000000);
1189
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1190
                 SPR_NOACCESS, SPR_NOACCESS,
1191
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1192
                 0x00000000);
1193
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1194
                 SPR_NOACCESS, SPR_NOACCESS,
1195
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1196
                 0x00000000);
1197
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1198
                 SPR_NOACCESS, SPR_NOACCESS,
1199
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1200
                 0x00000000);
1201
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1202
                 SPR_NOACCESS, SPR_NOACCESS,
1203
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1204
                 0x00000000);
1205
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1208
                 0x00000000);
1209
    env->nb_BATs = 4;
1210
#endif
1211
}
1212

    
1213
static void gen_spr_74xx (CPUPPCState *env)
1214
{
1215
    /* Processor identification */
1216
    spr_register(env, SPR_PIR, "PIR",
1217
                 SPR_NOACCESS, SPR_NOACCESS,
1218
                 &spr_read_generic, &spr_write_pir,
1219
                 0x00000000);
1220
    /* XXX : not implemented */
1221
    spr_register(env, SPR_MMCR2, "MMCR2",
1222
                 SPR_NOACCESS, SPR_NOACCESS,
1223
                 &spr_read_generic, &spr_write_generic,
1224
                 0x00000000);
1225
    /* XXX : not implemented */
1226
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1227
                 &spr_read_ureg, SPR_NOACCESS,
1228
                 &spr_read_ureg, SPR_NOACCESS,
1229
                 0x00000000);
1230
    /* XXX: not implemented */
1231
    spr_register(env, SPR_BAMR, "BAMR",
1232
                 SPR_NOACCESS, SPR_NOACCESS,
1233
                 &spr_read_generic, &spr_write_generic,
1234
                 0x00000000);
1235
    /* XXX : not implemented */
1236
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1237
                 SPR_NOACCESS, SPR_NOACCESS,
1238
                 &spr_read_generic, &spr_write_generic,
1239
                 0x00000000);
1240
    /* Hardware implementation registers */
1241
    /* XXX : not implemented */
1242
    spr_register(env, SPR_HID0, "HID0",
1243
                 SPR_NOACCESS, SPR_NOACCESS,
1244
                 &spr_read_generic, &spr_write_generic,
1245
                 0x00000000);
1246
    /* XXX : not implemented */
1247
    spr_register(env, SPR_HID1, "HID1",
1248
                 SPR_NOACCESS, SPR_NOACCESS,
1249
                 &spr_read_generic, &spr_write_generic,
1250
                 0x00000000);
1251
    /* Altivec */
1252
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1253
                 &spr_read_generic, &spr_write_generic,
1254
                 &spr_read_generic, &spr_write_generic,
1255
                 0x00000000);
1256
    /* XXX : not implemented */
1257
    spr_register(env, SPR_L2CR, "L2CR",
1258
                 SPR_NOACCESS, SPR_NOACCESS,
1259
                 &spr_read_generic, &spr_write_generic,
1260
                 0x00000000);
1261
    /* Not strictly an SPR */
1262
    vscr_init(env, 0x00010000);
1263
}
1264

    
1265
static void gen_l3_ctrl (CPUPPCState *env)
1266
{
1267
    /* L3CR */
1268
    /* XXX : not implemented */
1269
    spr_register(env, SPR_L3CR, "L3CR",
1270
                 SPR_NOACCESS, SPR_NOACCESS,
1271
                 &spr_read_generic, &spr_write_generic,
1272
                 0x00000000);
1273
    /* L3ITCR0 */
1274
    /* XXX : not implemented */
1275
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1276
                 SPR_NOACCESS, SPR_NOACCESS,
1277
                 &spr_read_generic, &spr_write_generic,
1278
                 0x00000000);
1279
    /* L3PM */
1280
    /* XXX : not implemented */
1281
    spr_register(env, SPR_L3PM, "L3PM",
1282
                 SPR_NOACCESS, SPR_NOACCESS,
1283
                 &spr_read_generic, &spr_write_generic,
1284
                 0x00000000);
1285
}
1286

    
1287
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1288
{
1289
#if !defined(CONFIG_USER_ONLY)
1290
    env->nb_tlb = nb_tlbs;
1291
    env->nb_ways = nb_ways;
1292
    env->id_tlbs = 1;
1293
    /* XXX : not implemented */
1294
    spr_register(env, SPR_PTEHI, "PTEHI",
1295
                 SPR_NOACCESS, SPR_NOACCESS,
1296
                 &spr_read_generic, &spr_write_generic,
1297
                 0x00000000);
1298
    /* XXX : not implemented */
1299
    spr_register(env, SPR_PTELO, "PTELO",
1300
                 SPR_NOACCESS, SPR_NOACCESS,
1301
                 &spr_read_generic, &spr_write_generic,
1302
                 0x00000000);
1303
    /* XXX : not implemented */
1304
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1305
                 SPR_NOACCESS, SPR_NOACCESS,
1306
                 &spr_read_generic, &spr_write_generic,
1307
                 0x00000000);
1308
#endif
1309
}
1310

    
1311
static void gen_spr_usprgh (CPUPPCState *env)
1312
{
1313
    spr_register(env, SPR_USPRG4, "USPRG4",
1314
                 &spr_read_ureg, SPR_NOACCESS,
1315
                 &spr_read_ureg, SPR_NOACCESS,
1316
                 0x00000000);
1317
    spr_register(env, SPR_USPRG5, "USPRG5",
1318
                 &spr_read_ureg, SPR_NOACCESS,
1319
                 &spr_read_ureg, SPR_NOACCESS,
1320
                 0x00000000);
1321
    spr_register(env, SPR_USPRG6, "USPRG6",
1322
                 &spr_read_ureg, SPR_NOACCESS,
1323
                 &spr_read_ureg, SPR_NOACCESS,
1324
                 0x00000000);
1325
    spr_register(env, SPR_USPRG7, "USPRG7",
1326
                 &spr_read_ureg, SPR_NOACCESS,
1327
                 &spr_read_ureg, SPR_NOACCESS,
1328
                 0x00000000);
1329
}
1330

    
1331
/* PowerPC BookE SPR */
1332
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1333
{
1334
    const char *ivor_names[64] = {
1335
        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1336
        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1337
        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1338
        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1339
        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1340
        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1341
        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1342
        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1343
        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1344
        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1345
        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1346
        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1347
        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1348
        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1349
        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1350
        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1351
    };
1352
#define SPR_BOOKE_IVORxx (-1)
1353
    int ivor_sprn[64] = {
1354
        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1355
        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1356
        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1357
        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1358
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1359
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1360
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1361
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1362
        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1363
        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1364
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1365
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1366
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1367
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1368
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1369
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1370
    };
1371
    int i;
1372

    
1373
    /* Interrupt processing */
1374
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1375
                 SPR_NOACCESS, SPR_NOACCESS,
1376
                 &spr_read_generic, &spr_write_generic,
1377
                 0x00000000);
1378
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1379
                 SPR_NOACCESS, SPR_NOACCESS,
1380
                 &spr_read_generic, &spr_write_generic,
1381
                 0x00000000);
1382
    /* Debug */
1383
    /* XXX : not implemented */
1384
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1385
                 SPR_NOACCESS, SPR_NOACCESS,
1386
                 &spr_read_generic, &spr_write_generic,
1387
                 0x00000000);
1388
    /* XXX : not implemented */
1389
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1390
                 SPR_NOACCESS, SPR_NOACCESS,
1391
                 &spr_read_generic, &spr_write_generic,
1392
                 0x00000000);
1393
    /* XXX : not implemented */
1394
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1395
                 SPR_NOACCESS, SPR_NOACCESS,
1396
                 &spr_read_generic, &spr_write_generic,
1397
                 0x00000000);
1398
    /* XXX : not implemented */
1399
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1400
                 SPR_NOACCESS, SPR_NOACCESS,
1401
                 &spr_read_generic, &spr_write_generic,
1402
                 0x00000000);
1403
    /* XXX : not implemented */
1404
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1405
                 SPR_NOACCESS, SPR_NOACCESS,
1406
                 &spr_read_generic, &spr_write_generic,
1407
                 0x00000000);
1408
    /* XXX : not implemented */
1409
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1410
                 SPR_NOACCESS, SPR_NOACCESS,
1411
                 &spr_read_generic, &spr_write_generic,
1412
                 0x00000000);
1413
    /* XXX : not implemented */
1414
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1415
                 SPR_NOACCESS, SPR_NOACCESS,
1416
                 &spr_read_generic, &spr_write_generic,
1417
                 0x00000000);
1418
    /* XXX : not implemented */
1419
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1420
                 SPR_NOACCESS, SPR_NOACCESS,
1421
                 &spr_read_generic, &spr_write_clear,
1422
                 0x00000000);
1423
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1424
                 SPR_NOACCESS, SPR_NOACCESS,
1425
                 &spr_read_generic, &spr_write_generic,
1426
                 0x00000000);
1427
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1428
                 SPR_NOACCESS, SPR_NOACCESS,
1429
                 &spr_read_generic, &spr_write_generic,
1430
                 0x00000000);
1431
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1432
                 SPR_NOACCESS, SPR_NOACCESS,
1433
                 &spr_read_generic, &spr_write_excp_prefix,
1434
                 0x00000000);
1435
    /* Exception vectors */
1436
    for (i = 0; i < 64; i++) {
1437
        if (ivor_mask & (1ULL << i)) {
1438
            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1439
                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1440
                exit(1);
1441
            }
1442
            spr_register(env, ivor_sprn[i], ivor_names[i],
1443
                         SPR_NOACCESS, SPR_NOACCESS,
1444
                         &spr_read_generic, &spr_write_excp_vector,
1445
                         0x00000000);
1446
        }
1447
    }
1448
    spr_register(env, SPR_BOOKE_PID, "PID",
1449
                 SPR_NOACCESS, SPR_NOACCESS,
1450
                 &spr_read_generic, &spr_write_generic,
1451
                 0x00000000);
1452
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1453
                 SPR_NOACCESS, SPR_NOACCESS,
1454
                 &spr_read_generic, &spr_write_booke_tcr,
1455
                 0x00000000);
1456
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1457
                 SPR_NOACCESS, SPR_NOACCESS,
1458
                 &spr_read_generic, &spr_write_booke_tsr,
1459
                 0x00000000);
1460
    /* Timer */
1461
    spr_register(env, SPR_DECR, "DECR",
1462
                 SPR_NOACCESS, SPR_NOACCESS,
1463
                 &spr_read_decr, &spr_write_decr,
1464
                 0x00000000);
1465
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1466
                 SPR_NOACCESS, SPR_NOACCESS,
1467
                 SPR_NOACCESS, &spr_write_generic,
1468
                 0x00000000);
1469
    /* SPRGs */
1470
    spr_register(env, SPR_USPRG0, "USPRG0",
1471
                 &spr_read_generic, &spr_write_generic,
1472
                 &spr_read_generic, &spr_write_generic,
1473
                 0x00000000);
1474
    spr_register(env, SPR_SPRG4, "SPRG4",
1475
                 SPR_NOACCESS, SPR_NOACCESS,
1476
                 &spr_read_generic, &spr_write_generic,
1477
                 0x00000000);
1478
    spr_register(env, SPR_SPRG5, "SPRG5",
1479
                 SPR_NOACCESS, SPR_NOACCESS,
1480
                 &spr_read_generic, &spr_write_generic,
1481
                 0x00000000);
1482
    spr_register(env, SPR_SPRG6, "SPRG6",
1483
                 SPR_NOACCESS, SPR_NOACCESS,
1484
                 &spr_read_generic, &spr_write_generic,
1485
                 0x00000000);
1486
    spr_register(env, SPR_SPRG7, "SPRG7",
1487
                 SPR_NOACCESS, SPR_NOACCESS,
1488
                 &spr_read_generic, &spr_write_generic,
1489
                 0x00000000);
1490
}
1491

    
1492
/* FSL storage control registers */
1493
static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1494
{
1495
#if !defined(CONFIG_USER_ONLY)
1496
    const char *mas_names[8] = {
1497
        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1498
    };
1499
    int mas_sprn[8] = {
1500
        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1501
        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1502
    };
1503
    int i;
1504

    
1505
    /* TLB assist registers */
1506
    /* XXX : not implemented */
1507
    for (i = 0; i < 8; i++) {
1508
        if (mas_mask & (1 << i)) {
1509
            spr_register(env, mas_sprn[i], mas_names[i],
1510
                         SPR_NOACCESS, SPR_NOACCESS,
1511
                         &spr_read_generic, &spr_write_generic,
1512
                         0x00000000);
1513
        }
1514
    }
1515
    if (env->nb_pids > 1) {
1516
        /* XXX : not implemented */
1517
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1518
                     SPR_NOACCESS, SPR_NOACCESS,
1519
                     &spr_read_generic, &spr_write_generic,
1520
                     0x00000000);
1521
    }
1522
    if (env->nb_pids > 2) {
1523
        /* XXX : not implemented */
1524
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1525
                     SPR_NOACCESS, SPR_NOACCESS,
1526
                     &spr_read_generic, &spr_write_generic,
1527
                     0x00000000);
1528
    }
1529
    /* XXX : not implemented */
1530
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1531
                 SPR_NOACCESS, SPR_NOACCESS,
1532
                 &spr_read_generic, SPR_NOACCESS,
1533
                 0x00000000); /* TOFIX */
1534
    /* XXX : not implemented */
1535
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1536
                 SPR_NOACCESS, SPR_NOACCESS,
1537
                 &spr_read_generic, &spr_write_generic,
1538
                 0x00000000); /* TOFIX */
1539
    switch (env->nb_ways) {
1540
    case 4:
1541
        /* XXX : not implemented */
1542
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1543
                     SPR_NOACCESS, SPR_NOACCESS,
1544
                     &spr_read_generic, SPR_NOACCESS,
1545
                     0x00000000); /* TOFIX */
1546
        /* Fallthru */
1547
    case 3:
1548
        /* XXX : not implemented */
1549
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1550
                     SPR_NOACCESS, SPR_NOACCESS,
1551
                     &spr_read_generic, SPR_NOACCESS,
1552
                     0x00000000); /* TOFIX */
1553
        /* Fallthru */
1554
    case 2:
1555
        /* XXX : not implemented */
1556
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1557
                     SPR_NOACCESS, SPR_NOACCESS,
1558
                     &spr_read_generic, SPR_NOACCESS,
1559
                     0x00000000); /* TOFIX */
1560
        /* Fallthru */
1561
    case 1:
1562
        /* XXX : not implemented */
1563
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1564
                     SPR_NOACCESS, SPR_NOACCESS,
1565
                     &spr_read_generic, SPR_NOACCESS,
1566
                     0x00000000); /* TOFIX */
1567
        /* Fallthru */
1568
    case 0:
1569
    default:
1570
        break;
1571
    }
1572
#endif
1573
}
1574

    
1575
/* SPR specific to PowerPC 440 implementation */
1576
static void gen_spr_440 (CPUPPCState *env)
1577
{
1578
    /* Cache control */
1579
    /* XXX : not implemented */
1580
    spr_register(env, SPR_440_DNV0, "DNV0",
1581
                 SPR_NOACCESS, SPR_NOACCESS,
1582
                 &spr_read_generic, &spr_write_generic,
1583
                 0x00000000);
1584
    /* XXX : not implemented */
1585
    spr_register(env, SPR_440_DNV1, "DNV1",
1586
                 SPR_NOACCESS, SPR_NOACCESS,
1587
                 &spr_read_generic, &spr_write_generic,
1588
                 0x00000000);
1589
    /* XXX : not implemented */
1590
    spr_register(env, SPR_440_DNV2, "DNV2",
1591
                 SPR_NOACCESS, SPR_NOACCESS,
1592
                 &spr_read_generic, &spr_write_generic,
1593
                 0x00000000);
1594
    /* XXX : not implemented */
1595
    spr_register(env, SPR_440_DNV3, "DNV3",
1596
                 SPR_NOACCESS, SPR_NOACCESS,
1597
                 &spr_read_generic, &spr_write_generic,
1598
                 0x00000000);
1599
    /* XXX : not implemented */
1600
    spr_register(env, SPR_440_DTV0, "DTV0",
1601
                 SPR_NOACCESS, SPR_NOACCESS,
1602
                 &spr_read_generic, &spr_write_generic,
1603
                 0x00000000);
1604
    /* XXX : not implemented */
1605
    spr_register(env, SPR_440_DTV1, "DTV1",
1606
                 SPR_NOACCESS, SPR_NOACCESS,
1607
                 &spr_read_generic, &spr_write_generic,
1608
                 0x00000000);
1609
    /* XXX : not implemented */
1610
    spr_register(env, SPR_440_DTV2, "DTV2",
1611
                 SPR_NOACCESS, SPR_NOACCESS,
1612
                 &spr_read_generic, &spr_write_generic,
1613
                 0x00000000);
1614
    /* XXX : not implemented */
1615
    spr_register(env, SPR_440_DTV3, "DTV3",
1616
                 SPR_NOACCESS, SPR_NOACCESS,
1617
                 &spr_read_generic, &spr_write_generic,
1618
                 0x00000000);
1619
    /* XXX : not implemented */
1620
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1621
                 SPR_NOACCESS, SPR_NOACCESS,
1622
                 &spr_read_generic, &spr_write_generic,
1623
                 0x00000000);
1624
    /* XXX : not implemented */
1625
    spr_register(env, SPR_440_INV0, "INV0",
1626
                 SPR_NOACCESS, SPR_NOACCESS,
1627
                 &spr_read_generic, &spr_write_generic,
1628
                 0x00000000);
1629
    /* XXX : not implemented */
1630
    spr_register(env, SPR_440_INV1, "INV1",
1631
                 SPR_NOACCESS, SPR_NOACCESS,
1632
                 &spr_read_generic, &spr_write_generic,
1633
                 0x00000000);
1634
    /* XXX : not implemented */
1635
    spr_register(env, SPR_440_INV2, "INV2",
1636
                 SPR_NOACCESS, SPR_NOACCESS,
1637
                 &spr_read_generic, &spr_write_generic,
1638
                 0x00000000);
1639
    /* XXX : not implemented */
1640
    spr_register(env, SPR_440_INV3, "INV3",
1641
                 SPR_NOACCESS, SPR_NOACCESS,
1642
                 &spr_read_generic, &spr_write_generic,
1643
                 0x00000000);
1644
    /* XXX : not implemented */
1645
    spr_register(env, SPR_440_ITV0, "ITV0",
1646
                 SPR_NOACCESS, SPR_NOACCESS,
1647
                 &spr_read_generic, &spr_write_generic,
1648
                 0x00000000);
1649
    /* XXX : not implemented */
1650
    spr_register(env, SPR_440_ITV1, "ITV1",
1651
                 SPR_NOACCESS, SPR_NOACCESS,
1652
                 &spr_read_generic, &spr_write_generic,
1653
                 0x00000000);
1654
    /* XXX : not implemented */
1655
    spr_register(env, SPR_440_ITV2, "ITV2",
1656
                 SPR_NOACCESS, SPR_NOACCESS,
1657
                 &spr_read_generic, &spr_write_generic,
1658
                 0x00000000);
1659
    /* XXX : not implemented */
1660
    spr_register(env, SPR_440_ITV3, "ITV3",
1661
                 SPR_NOACCESS, SPR_NOACCESS,
1662
                 &spr_read_generic, &spr_write_generic,
1663
                 0x00000000);
1664
    /* XXX : not implemented */
1665
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1666
                 SPR_NOACCESS, SPR_NOACCESS,
1667
                 &spr_read_generic, &spr_write_generic,
1668
                 0x00000000);
1669
    /* Cache debug */
1670
    /* XXX : not implemented */
1671
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1672
                 SPR_NOACCESS, SPR_NOACCESS,
1673
                 &spr_read_generic, SPR_NOACCESS,
1674
                 0x00000000);
1675
    /* XXX : not implemented */
1676
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1677
                 SPR_NOACCESS, SPR_NOACCESS,
1678
                 &spr_read_generic, SPR_NOACCESS,
1679
                 0x00000000);
1680
    /* XXX : not implemented */
1681
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1682
                 SPR_NOACCESS, SPR_NOACCESS,
1683
                 &spr_read_generic, SPR_NOACCESS,
1684
                 0x00000000);
1685
    /* XXX : not implemented */
1686
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1687
                 SPR_NOACCESS, SPR_NOACCESS,
1688
                 &spr_read_generic, SPR_NOACCESS,
1689
                 0x00000000);
1690
    /* XXX : not implemented */
1691
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1692
                 SPR_NOACCESS, SPR_NOACCESS,
1693
                 &spr_read_generic, SPR_NOACCESS,
1694
                 0x00000000);
1695
    /* XXX : not implemented */
1696
    spr_register(env, SPR_440_DBDR, "DBDR",
1697
                 SPR_NOACCESS, SPR_NOACCESS,
1698
                 &spr_read_generic, &spr_write_generic,
1699
                 0x00000000);
1700
    /* Processor control */
1701
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1702
                 SPR_NOACCESS, SPR_NOACCESS,
1703
                 &spr_read_generic, &spr_write_generic,
1704
                 0x00000000);
1705
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1706
                 SPR_NOACCESS, SPR_NOACCESS,
1707
                 &spr_read_generic, SPR_NOACCESS,
1708
                 0x00000000);
1709
    /* Storage control */
1710
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1711
                 SPR_NOACCESS, SPR_NOACCESS,
1712
                 &spr_read_generic, &spr_write_generic,
1713
                 0x00000000);
1714
}
1715

    
1716
/* SPR shared between PowerPC 40x implementations */
1717
static void gen_spr_40x (CPUPPCState *env)
1718
{
1719
    /* Cache */
1720
    /* not emulated, as Qemu do not emulate caches */
1721
    spr_register(env, SPR_40x_DCCR, "DCCR",
1722
                 SPR_NOACCESS, SPR_NOACCESS,
1723
                 &spr_read_generic, &spr_write_generic,
1724
                 0x00000000);
1725
    /* not emulated, as Qemu do not emulate caches */
1726
    spr_register(env, SPR_40x_ICCR, "ICCR",
1727
                 SPR_NOACCESS, SPR_NOACCESS,
1728
                 &spr_read_generic, &spr_write_generic,
1729
                 0x00000000);
1730
    /* not emulated, as Qemu do not emulate caches */
1731
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1732
                 SPR_NOACCESS, SPR_NOACCESS,
1733
                 &spr_read_generic, SPR_NOACCESS,
1734
                 0x00000000);
1735
    /* Exception */
1736
    spr_register(env, SPR_40x_DEAR, "DEAR",
1737
                 SPR_NOACCESS, SPR_NOACCESS,
1738
                 &spr_read_generic, &spr_write_generic,
1739
                 0x00000000);
1740
    spr_register(env, SPR_40x_ESR, "ESR",
1741
                 SPR_NOACCESS, SPR_NOACCESS,
1742
                 &spr_read_generic, &spr_write_generic,
1743
                 0x00000000);
1744
    spr_register(env, SPR_40x_EVPR, "EVPR",
1745
                 SPR_NOACCESS, SPR_NOACCESS,
1746
                 &spr_read_generic, &spr_write_excp_prefix,
1747
                 0x00000000);
1748
    spr_register(env, SPR_40x_SRR2, "SRR2",
1749
                 &spr_read_generic, &spr_write_generic,
1750
                 &spr_read_generic, &spr_write_generic,
1751
                 0x00000000);
1752
    spr_register(env, SPR_40x_SRR3, "SRR3",
1753
                 &spr_read_generic, &spr_write_generic,
1754
                 &spr_read_generic, &spr_write_generic,
1755
                 0x00000000);
1756
    /* Timers */
1757
    spr_register(env, SPR_40x_PIT, "PIT",
1758
                 SPR_NOACCESS, SPR_NOACCESS,
1759
                 &spr_read_40x_pit, &spr_write_40x_pit,
1760
                 0x00000000);
1761
    spr_register(env, SPR_40x_TCR, "TCR",
1762
                 SPR_NOACCESS, SPR_NOACCESS,
1763
                 &spr_read_generic, &spr_write_booke_tcr,
1764
                 0x00000000);
1765
    spr_register(env, SPR_40x_TSR, "TSR",
1766
                 SPR_NOACCESS, SPR_NOACCESS,
1767
                 &spr_read_generic, &spr_write_booke_tsr,
1768
                 0x00000000);
1769
}
1770

    
1771
/* SPR specific to PowerPC 405 implementation */
1772
static void gen_spr_405 (CPUPPCState *env)
1773
{
1774
    /* MMU */
1775
    spr_register(env, SPR_40x_PID, "PID",
1776
                 SPR_NOACCESS, SPR_NOACCESS,
1777
                 &spr_read_generic, &spr_write_generic,
1778
                 0x00000000);
1779
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1780
                 SPR_NOACCESS, SPR_NOACCESS,
1781
                 &spr_read_generic, &spr_write_generic,
1782
                 0x00700000);
1783
    /* Debug interface */
1784
    /* XXX : not implemented */
1785
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1786
                 SPR_NOACCESS, SPR_NOACCESS,
1787
                 &spr_read_generic, &spr_write_40x_dbcr0,
1788
                 0x00000000);
1789
    /* XXX : not implemented */
1790
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1791
                 SPR_NOACCESS, SPR_NOACCESS,
1792
                 &spr_read_generic, &spr_write_generic,
1793
                 0x00000000);
1794
    /* XXX : not implemented */
1795
    spr_register(env, SPR_40x_DBSR, "DBSR",
1796
                 SPR_NOACCESS, SPR_NOACCESS,
1797
                 &spr_read_generic, &spr_write_clear,
1798
                 /* Last reset was system reset */
1799
                 0x00000300);
1800
    /* XXX : not implemented */
1801
    spr_register(env, SPR_40x_DAC1, "DAC1",
1802
                 SPR_NOACCESS, SPR_NOACCESS,
1803
                 &spr_read_generic, &spr_write_generic,
1804
                 0x00000000);
1805
    spr_register(env, SPR_40x_DAC2, "DAC2",
1806
                 SPR_NOACCESS, SPR_NOACCESS,
1807
                 &spr_read_generic, &spr_write_generic,
1808
                 0x00000000);
1809
    /* XXX : not implemented */
1810
    spr_register(env, SPR_405_DVC1, "DVC1",
1811
                 SPR_NOACCESS, SPR_NOACCESS,
1812
                 &spr_read_generic, &spr_write_generic,
1813
                 0x00000000);
1814
    /* XXX : not implemented */
1815
    spr_register(env, SPR_405_DVC2, "DVC2",
1816
                 SPR_NOACCESS, SPR_NOACCESS,
1817
                 &spr_read_generic, &spr_write_generic,
1818
                 0x00000000);
1819
    /* XXX : not implemented */
1820
    spr_register(env, SPR_40x_IAC1, "IAC1",
1821
                 SPR_NOACCESS, SPR_NOACCESS,
1822
                 &spr_read_generic, &spr_write_generic,
1823
                 0x00000000);
1824
    spr_register(env, SPR_40x_IAC2, "IAC2",
1825
                 SPR_NOACCESS, SPR_NOACCESS,
1826
                 &spr_read_generic, &spr_write_generic,
1827
                 0x00000000);
1828
    /* XXX : not implemented */
1829
    spr_register(env, SPR_405_IAC3, "IAC3",
1830
                 SPR_NOACCESS, SPR_NOACCESS,
1831
                 &spr_read_generic, &spr_write_generic,
1832
                 0x00000000);
1833
    /* XXX : not implemented */
1834
    spr_register(env, SPR_405_IAC4, "IAC4",
1835
                 SPR_NOACCESS, SPR_NOACCESS,
1836
                 &spr_read_generic, &spr_write_generic,
1837
                 0x00000000);
1838
    /* Storage control */
1839
    /* XXX: TODO: not implemented */
1840
    spr_register(env, SPR_405_SLER, "SLER",
1841
                 SPR_NOACCESS, SPR_NOACCESS,
1842
                 &spr_read_generic, &spr_write_40x_sler,
1843
                 0x00000000);
1844
    spr_register(env, SPR_40x_ZPR, "ZPR",
1845
                 SPR_NOACCESS, SPR_NOACCESS,
1846
                 &spr_read_generic, &spr_write_generic,
1847
                 0x00000000);
1848
    /* XXX : not implemented */
1849
    spr_register(env, SPR_405_SU0R, "SU0R",
1850
                 SPR_NOACCESS, SPR_NOACCESS,
1851
                 &spr_read_generic, &spr_write_generic,
1852
                 0x00000000);
1853
    /* SPRG */
1854
    spr_register(env, SPR_USPRG0, "USPRG0",
1855
                 &spr_read_ureg, SPR_NOACCESS,
1856
                 &spr_read_ureg, SPR_NOACCESS,
1857
                 0x00000000);
1858
    spr_register(env, SPR_SPRG4, "SPRG4",
1859
                 SPR_NOACCESS, SPR_NOACCESS,
1860
                 &spr_read_generic, &spr_write_generic,
1861
                 0x00000000);
1862
    spr_register(env, SPR_SPRG5, "SPRG5",
1863
                 SPR_NOACCESS, SPR_NOACCESS,
1864
                 spr_read_generic, &spr_write_generic,
1865
                 0x00000000);
1866
    spr_register(env, SPR_SPRG6, "SPRG6",
1867
                 SPR_NOACCESS, SPR_NOACCESS,
1868
                 spr_read_generic, &spr_write_generic,
1869
                 0x00000000);
1870
    spr_register(env, SPR_SPRG7, "SPRG7",
1871
                 SPR_NOACCESS, SPR_NOACCESS,
1872
                 spr_read_generic, &spr_write_generic,
1873
                 0x00000000);
1874
    gen_spr_usprgh(env);
1875
}
1876

    
1877
/* SPR shared between PowerPC 401 & 403 implementations */
1878
static void gen_spr_401_403 (CPUPPCState *env)
1879
{
1880
    /* Time base */
1881
    spr_register(env, SPR_403_VTBL,  "TBL",
1882
                 &spr_read_tbl, SPR_NOACCESS,
1883
                 &spr_read_tbl, SPR_NOACCESS,
1884
                 0x00000000);
1885
    spr_register(env, SPR_403_TBL,   "TBL",
1886
                 SPR_NOACCESS, SPR_NOACCESS,
1887
                 SPR_NOACCESS, &spr_write_tbl,
1888
                 0x00000000);
1889
    spr_register(env, SPR_403_VTBU,  "TBU",
1890
                 &spr_read_tbu, SPR_NOACCESS,
1891
                 &spr_read_tbu, SPR_NOACCESS,
1892
                 0x00000000);
1893
    spr_register(env, SPR_403_TBU,   "TBU",
1894
                 SPR_NOACCESS, SPR_NOACCESS,
1895
                 SPR_NOACCESS, &spr_write_tbu,
1896
                 0x00000000);
1897
    /* Debug */
1898
    /* not emulated, as Qemu do not emulate caches */
1899
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1900
                 SPR_NOACCESS, SPR_NOACCESS,
1901
                 &spr_read_generic, &spr_write_generic,
1902
                 0x00000000);
1903
}
1904

    
1905
/* SPR specific to PowerPC 401 implementation */
1906
static void gen_spr_401 (CPUPPCState *env)
1907
{
1908
    /* Debug interface */
1909
    /* XXX : not implemented */
1910
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1911
                 SPR_NOACCESS, SPR_NOACCESS,
1912
                 &spr_read_generic, &spr_write_40x_dbcr0,
1913
                 0x00000000);
1914
    /* XXX : not implemented */
1915
    spr_register(env, SPR_40x_DBSR, "DBSR",
1916
                 SPR_NOACCESS, SPR_NOACCESS,
1917
                 &spr_read_generic, &spr_write_clear,
1918
                 /* Last reset was system reset */
1919
                 0x00000300);
1920
    /* XXX : not implemented */
1921
    spr_register(env, SPR_40x_DAC1, "DAC",
1922
                 SPR_NOACCESS, SPR_NOACCESS,
1923
                 &spr_read_generic, &spr_write_generic,
1924
                 0x00000000);
1925
    /* XXX : not implemented */
1926
    spr_register(env, SPR_40x_IAC1, "IAC",
1927
                 SPR_NOACCESS, SPR_NOACCESS,
1928
                 &spr_read_generic, &spr_write_generic,
1929
                 0x00000000);
1930
    /* Storage control */
1931
    /* XXX: TODO: not implemented */
1932
    spr_register(env, SPR_405_SLER, "SLER",
1933
                 SPR_NOACCESS, SPR_NOACCESS,
1934
                 &spr_read_generic, &spr_write_40x_sler,
1935
                 0x00000000);
1936
    /* not emulated, as Qemu never does speculative access */
1937
    spr_register(env, SPR_40x_SGR, "SGR",
1938
                 SPR_NOACCESS, SPR_NOACCESS,
1939
                 &spr_read_generic, &spr_write_generic,
1940
                 0xFFFFFFFF);
1941
    /* not emulated, as Qemu do not emulate caches */
1942
    spr_register(env, SPR_40x_DCWR, "DCWR",
1943
                 SPR_NOACCESS, SPR_NOACCESS,
1944
                 &spr_read_generic, &spr_write_generic,
1945
                 0x00000000);
1946
}
1947

    
1948
static void gen_spr_401x2 (CPUPPCState *env)
1949
{
1950
    gen_spr_401(env);
1951
    spr_register(env, SPR_40x_PID, "PID",
1952
                 SPR_NOACCESS, SPR_NOACCESS,
1953
                 &spr_read_generic, &spr_write_generic,
1954
                 0x00000000);
1955
    spr_register(env, SPR_40x_ZPR, "ZPR",
1956
                 SPR_NOACCESS, SPR_NOACCESS,
1957
                 &spr_read_generic, &spr_write_generic,
1958
                 0x00000000);
1959
}
1960

    
1961
/* SPR specific to PowerPC 403 implementation */
1962
static void gen_spr_403 (CPUPPCState *env)
1963
{
1964
    /* Debug interface */
1965
    /* XXX : not implemented */
1966
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1967
                 SPR_NOACCESS, SPR_NOACCESS,
1968
                 &spr_read_generic, &spr_write_40x_dbcr0,
1969
                 0x00000000);
1970
    /* XXX : not implemented */
1971
    spr_register(env, SPR_40x_DBSR, "DBSR",
1972
                 SPR_NOACCESS, SPR_NOACCESS,
1973
                 &spr_read_generic, &spr_write_clear,
1974
                 /* Last reset was system reset */
1975
                 0x00000300);
1976
    /* XXX : not implemented */
1977
    spr_register(env, SPR_40x_DAC1, "DAC1",
1978
                 SPR_NOACCESS, SPR_NOACCESS,
1979
                 &spr_read_generic, &spr_write_generic,
1980
                 0x00000000);
1981
    /* XXX : not implemented */
1982
    spr_register(env, SPR_40x_DAC2, "DAC2",
1983
                 SPR_NOACCESS, SPR_NOACCESS,
1984
                 &spr_read_generic, &spr_write_generic,
1985
                 0x00000000);
1986
    /* XXX : not implemented */
1987
    spr_register(env, SPR_40x_IAC1, "IAC1",
1988
                 SPR_NOACCESS, SPR_NOACCESS,
1989
                 &spr_read_generic, &spr_write_generic,
1990
                 0x00000000);
1991
    /* XXX : not implemented */
1992
    spr_register(env, SPR_40x_IAC2, "IAC2",
1993
                 SPR_NOACCESS, SPR_NOACCESS,
1994
                 &spr_read_generic, &spr_write_generic,
1995
                 0x00000000);
1996
}
1997

    
1998
static void gen_spr_403_real (CPUPPCState *env)
1999
{
2000
    spr_register(env, SPR_403_PBL1,  "PBL1",
2001
                 SPR_NOACCESS, SPR_NOACCESS,
2002
                 &spr_read_403_pbr, &spr_write_403_pbr,
2003
                 0x00000000);
2004
    spr_register(env, SPR_403_PBU1,  "PBU1",
2005
                 SPR_NOACCESS, SPR_NOACCESS,
2006
                 &spr_read_403_pbr, &spr_write_403_pbr,
2007
                 0x00000000);
2008
    spr_register(env, SPR_403_PBL2,  "PBL2",
2009
                 SPR_NOACCESS, SPR_NOACCESS,
2010
                 &spr_read_403_pbr, &spr_write_403_pbr,
2011
                 0x00000000);
2012
    spr_register(env, SPR_403_PBU2,  "PBU2",
2013
                 SPR_NOACCESS, SPR_NOACCESS,
2014
                 &spr_read_403_pbr, &spr_write_403_pbr,
2015
                 0x00000000);
2016
}
2017

    
2018
static void gen_spr_403_mmu (CPUPPCState *env)
2019
{
2020
    /* MMU */
2021
    spr_register(env, SPR_40x_PID, "PID",
2022
                 SPR_NOACCESS, SPR_NOACCESS,
2023
                 &spr_read_generic, &spr_write_generic,
2024
                 0x00000000);
2025
    spr_register(env, SPR_40x_ZPR, "ZPR",
2026
                 SPR_NOACCESS, SPR_NOACCESS,
2027
                 &spr_read_generic, &spr_write_generic,
2028
                 0x00000000);
2029
}
2030

    
2031
/* SPR specific to PowerPC compression coprocessor extension */
2032
static void gen_spr_compress (CPUPPCState *env)
2033
{
2034
    /* XXX : not implemented */
2035
    spr_register(env, SPR_401_SKR, "SKR",
2036
                 SPR_NOACCESS, SPR_NOACCESS,
2037
                 &spr_read_generic, &spr_write_generic,
2038
                 0x00000000);
2039
}
2040

    
2041
#if defined (TARGET_PPC64)
2042
/* SPR specific to PowerPC 620 */
2043
static void gen_spr_620 (CPUPPCState *env)
2044
{
2045
    /* Processor identification */
2046
    spr_register(env, SPR_PIR, "PIR",
2047
                 SPR_NOACCESS, SPR_NOACCESS,
2048
                 &spr_read_generic, &spr_write_pir,
2049
                 0x00000000);
2050
    spr_register(env, SPR_ASR, "ASR",
2051
                 SPR_NOACCESS, SPR_NOACCESS,
2052
                 &spr_read_asr, &spr_write_asr,
2053
                 0x00000000);
2054
    /* Breakpoints */
2055
    /* XXX : not implemented */
2056
    spr_register(env, SPR_IABR, "IABR",
2057
                 SPR_NOACCESS, SPR_NOACCESS,
2058
                 &spr_read_generic, &spr_write_generic,
2059
                 0x00000000);
2060
    /* XXX : not implemented */
2061
    spr_register(env, SPR_DABR, "DABR",
2062
                 SPR_NOACCESS, SPR_NOACCESS,
2063
                 &spr_read_generic, &spr_write_generic,
2064
                 0x00000000);
2065
    /* XXX : not implemented */
2066
    spr_register(env, SPR_SIAR, "SIAR",
2067
                 SPR_NOACCESS, SPR_NOACCESS,
2068
                 &spr_read_generic, SPR_NOACCESS,
2069
                 0x00000000);
2070
    /* XXX : not implemented */
2071
    spr_register(env, SPR_SDA, "SDA",
2072
                 SPR_NOACCESS, SPR_NOACCESS,
2073
                 &spr_read_generic, SPR_NOACCESS,
2074
                 0x00000000);
2075
    /* XXX : not implemented */
2076
    spr_register(env, SPR_620_PMC1R, "PMC1",
2077
                 SPR_NOACCESS, SPR_NOACCESS,
2078
                 &spr_read_generic, SPR_NOACCESS,
2079
                 0x00000000);
2080
    spr_register(env, SPR_620_PMC1W, "PMC1",
2081
                 SPR_NOACCESS, SPR_NOACCESS,
2082
                  SPR_NOACCESS, &spr_write_generic,
2083
                 0x00000000);
2084
    /* XXX : not implemented */
2085
    spr_register(env, SPR_620_PMC2R, "PMC2",
2086
                 SPR_NOACCESS, SPR_NOACCESS,
2087
                 &spr_read_generic, SPR_NOACCESS,
2088
                 0x00000000);
2089
    spr_register(env, SPR_620_PMC2W, "PMC2",
2090
                 SPR_NOACCESS, SPR_NOACCESS,
2091
                  SPR_NOACCESS, &spr_write_generic,
2092
                 0x00000000);
2093
    /* XXX : not implemented */
2094
    spr_register(env, SPR_620_MMCR0R, "MMCR0",
2095
                 SPR_NOACCESS, SPR_NOACCESS,
2096
                 &spr_read_generic, SPR_NOACCESS,
2097
                 0x00000000);
2098
    spr_register(env, SPR_620_MMCR0W, "MMCR0",
2099
                 SPR_NOACCESS, SPR_NOACCESS,
2100
                  SPR_NOACCESS, &spr_write_generic,
2101
                 0x00000000);
2102
    /* External access control */
2103
    /* XXX : not implemented */
2104
    spr_register(env, SPR_EAR, "EAR",
2105
                 SPR_NOACCESS, SPR_NOACCESS,
2106
                 &spr_read_generic, &spr_write_generic,
2107
                 0x00000000);
2108
#if 0 // XXX: check this
2109
    /* XXX : not implemented */
2110
    spr_register(env, SPR_620_PMR0, "PMR0",
2111
                 SPR_NOACCESS, SPR_NOACCESS,
2112
                 &spr_read_generic, &spr_write_generic,
2113
                 0x00000000);
2114
    /* XXX : not implemented */
2115
    spr_register(env, SPR_620_PMR1, "PMR1",
2116
                 SPR_NOACCESS, SPR_NOACCESS,
2117
                 &spr_read_generic, &spr_write_generic,
2118
                 0x00000000);
2119
    /* XXX : not implemented */
2120
    spr_register(env, SPR_620_PMR2, "PMR2",
2121
                 SPR_NOACCESS, SPR_NOACCESS,
2122
                 &spr_read_generic, &spr_write_generic,
2123
                 0x00000000);
2124
    /* XXX : not implemented */
2125
    spr_register(env, SPR_620_PMR3, "PMR3",
2126
                 SPR_NOACCESS, SPR_NOACCESS,
2127
                 &spr_read_generic, &spr_write_generic,
2128
                 0x00000000);
2129
    /* XXX : not implemented */
2130
    spr_register(env, SPR_620_PMR4, "PMR4",
2131
                 SPR_NOACCESS, SPR_NOACCESS,
2132
                 &spr_read_generic, &spr_write_generic,
2133
                 0x00000000);
2134
    /* XXX : not implemented */
2135
    spr_register(env, SPR_620_PMR5, "PMR5",
2136
                 SPR_NOACCESS, SPR_NOACCESS,
2137
                 &spr_read_generic, &spr_write_generic,
2138
                 0x00000000);
2139
    /* XXX : not implemented */
2140
    spr_register(env, SPR_620_PMR6, "PMR6",
2141
                 SPR_NOACCESS, SPR_NOACCESS,
2142
                 &spr_read_generic, &spr_write_generic,
2143
                 0x00000000);
2144
    /* XXX : not implemented */
2145
    spr_register(env, SPR_620_PMR7, "PMR7",
2146
                 SPR_NOACCESS, SPR_NOACCESS,
2147
                 &spr_read_generic, &spr_write_generic,
2148
                 0x00000000);
2149
    /* XXX : not implemented */
2150
    spr_register(env, SPR_620_PMR8, "PMR8",
2151
                 SPR_NOACCESS, SPR_NOACCESS,
2152
                 &spr_read_generic, &spr_write_generic,
2153
                 0x00000000);
2154
    /* XXX : not implemented */
2155
    spr_register(env, SPR_620_PMR9, "PMR9",
2156
                 SPR_NOACCESS, SPR_NOACCESS,
2157
                 &spr_read_generic, &spr_write_generic,
2158
                 0x00000000);
2159
    /* XXX : not implemented */
2160
    spr_register(env, SPR_620_PMRA, "PMR10",
2161
                 SPR_NOACCESS, SPR_NOACCESS,
2162
                 &spr_read_generic, &spr_write_generic,
2163
                 0x00000000);
2164
    /* XXX : not implemented */
2165
    spr_register(env, SPR_620_PMRB, "PMR11",
2166
                 SPR_NOACCESS, SPR_NOACCESS,
2167
                 &spr_read_generic, &spr_write_generic,
2168
                 0x00000000);
2169
    /* XXX : not implemented */
2170
    spr_register(env, SPR_620_PMRC, "PMR12",
2171
                 SPR_NOACCESS, SPR_NOACCESS,
2172
                 &spr_read_generic, &spr_write_generic,
2173
                 0x00000000);
2174
    /* XXX : not implemented */
2175
    spr_register(env, SPR_620_PMRD, "PMR13",
2176
                 SPR_NOACCESS, SPR_NOACCESS,
2177
                 &spr_read_generic, &spr_write_generic,
2178
                 0x00000000);
2179
    /* XXX : not implemented */
2180
    spr_register(env, SPR_620_PMRE, "PMR14",
2181
                 SPR_NOACCESS, SPR_NOACCESS,
2182
                 &spr_read_generic, &spr_write_generic,
2183
                 0x00000000);
2184
    /* XXX : not implemented */
2185
    spr_register(env, SPR_620_PMRF, "PMR15",
2186
                 SPR_NOACCESS, SPR_NOACCESS,
2187
                 &spr_read_generic, &spr_write_generic,
2188
                 0x00000000);
2189
#endif
2190
    /* XXX : not implemented */
2191
    spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2192
                 SPR_NOACCESS, SPR_NOACCESS,
2193
                 &spr_read_generic, &spr_write_generic,
2194
                 0x00000000);
2195
    /* XXX : not implemented */
2196
    spr_register(env, SPR_620_L2CR, "L2CR",
2197
                 SPR_NOACCESS, SPR_NOACCESS,
2198
                 &spr_read_generic, &spr_write_generic,
2199
                 0x00000000);
2200
    /* XXX : not implemented */
2201
    spr_register(env, SPR_620_L2SR, "L2SR",
2202
                 SPR_NOACCESS, SPR_NOACCESS,
2203
                 &spr_read_generic, &spr_write_generic,
2204
                 0x00000000);
2205
}
2206
#endif /* defined (TARGET_PPC64) */
2207

    
2208
static void gen_spr_5xx_8xx (CPUPPCState *env)
2209
{
2210
    /* Exception processing */
2211
    spr_register(env, SPR_DSISR, "DSISR",
2212
                 SPR_NOACCESS, SPR_NOACCESS,
2213
                 &spr_read_generic, &spr_write_generic,
2214
                 0x00000000);
2215
    spr_register(env, SPR_DAR, "DAR",
2216
                 SPR_NOACCESS, SPR_NOACCESS,
2217
                 &spr_read_generic, &spr_write_generic,
2218
                 0x00000000);
2219
    /* Timer */
2220
    spr_register(env, SPR_DECR, "DECR",
2221
                 SPR_NOACCESS, SPR_NOACCESS,
2222
                 &spr_read_decr, &spr_write_decr,
2223
                 0x00000000);
2224
    /* XXX : not implemented */
2225
    spr_register(env, SPR_MPC_EIE, "EIE",
2226
                 SPR_NOACCESS, SPR_NOACCESS,
2227
                 &spr_read_generic, &spr_write_generic,
2228
                 0x00000000);
2229
    /* XXX : not implemented */
2230
    spr_register(env, SPR_MPC_EID, "EID",
2231
                 SPR_NOACCESS, SPR_NOACCESS,
2232
                 &spr_read_generic, &spr_write_generic,
2233
                 0x00000000);
2234
    /* XXX : not implemented */
2235
    spr_register(env, SPR_MPC_NRI, "NRI",
2236
                 SPR_NOACCESS, SPR_NOACCESS,
2237
                 &spr_read_generic, &spr_write_generic,
2238
                 0x00000000);
2239
    /* XXX : not implemented */
2240
    spr_register(env, SPR_MPC_CMPA, "CMPA",
2241
                 SPR_NOACCESS, SPR_NOACCESS,
2242
                 &spr_read_generic, &spr_write_generic,
2243
                 0x00000000);
2244
    /* XXX : not implemented */
2245
    spr_register(env, SPR_MPC_CMPB, "CMPB",
2246
                 SPR_NOACCESS, SPR_NOACCESS,
2247
                 &spr_read_generic, &spr_write_generic,
2248
                 0x00000000);
2249
    /* XXX : not implemented */
2250
    spr_register(env, SPR_MPC_CMPC, "CMPC",
2251
                 SPR_NOACCESS, SPR_NOACCESS,
2252
                 &spr_read_generic, &spr_write_generic,
2253
                 0x00000000);
2254
    /* XXX : not implemented */
2255
    spr_register(env, SPR_MPC_CMPD, "CMPD",
2256
                 SPR_NOACCESS, SPR_NOACCESS,
2257
                 &spr_read_generic, &spr_write_generic,
2258
                 0x00000000);
2259
    /* XXX : not implemented */
2260
    spr_register(env, SPR_MPC_ECR, "ECR",
2261
                 SPR_NOACCESS, SPR_NOACCESS,
2262
                 &spr_read_generic, &spr_write_generic,
2263
                 0x00000000);
2264
    /* XXX : not implemented */
2265
    spr_register(env, SPR_MPC_DER, "DER",
2266
                 SPR_NOACCESS, SPR_NOACCESS,
2267
                 &spr_read_generic, &spr_write_generic,
2268
                 0x00000000);
2269
    /* XXX : not implemented */
2270
    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2271
                 SPR_NOACCESS, SPR_NOACCESS,
2272
                 &spr_read_generic, &spr_write_generic,
2273
                 0x00000000);
2274
    /* XXX : not implemented */
2275
    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2276
                 SPR_NOACCESS, SPR_NOACCESS,
2277
                 &spr_read_generic, &spr_write_generic,
2278
                 0x00000000);
2279
    /* XXX : not implemented */
2280
    spr_register(env, SPR_MPC_CMPE, "CMPE",
2281
                 SPR_NOACCESS, SPR_NOACCESS,
2282
                 &spr_read_generic, &spr_write_generic,
2283
                 0x00000000);
2284
    /* XXX : not implemented */
2285
    spr_register(env, SPR_MPC_CMPF, "CMPF",
2286
                 SPR_NOACCESS, SPR_NOACCESS,
2287
                 &spr_read_generic, &spr_write_generic,
2288
                 0x00000000);
2289
    /* XXX : not implemented */
2290
    spr_register(env, SPR_MPC_CMPG, "CMPG",
2291
                 SPR_NOACCESS, SPR_NOACCESS,
2292
                 &spr_read_generic, &spr_write_generic,
2293
                 0x00000000);
2294
    /* XXX : not implemented */
2295
    spr_register(env, SPR_MPC_CMPH, "CMPH",
2296
                 SPR_NOACCESS, SPR_NOACCESS,
2297
                 &spr_read_generic, &spr_write_generic,
2298
                 0x00000000);
2299
    /* XXX : not implemented */
2300
    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2301
                 SPR_NOACCESS, SPR_NOACCESS,
2302
                 &spr_read_generic, &spr_write_generic,
2303
                 0x00000000);
2304
    /* XXX : not implemented */
2305
    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2306
                 SPR_NOACCESS, SPR_NOACCESS,
2307
                 &spr_read_generic, &spr_write_generic,
2308
                 0x00000000);
2309
    /* XXX : not implemented */
2310
    spr_register(env, SPR_MPC_BAR, "BAR",
2311
                 SPR_NOACCESS, SPR_NOACCESS,
2312
                 &spr_read_generic, &spr_write_generic,
2313
                 0x00000000);
2314
    /* XXX : not implemented */
2315
    spr_register(env, SPR_MPC_DPDR, "DPDR",
2316
                 SPR_NOACCESS, SPR_NOACCESS,
2317
                 &spr_read_generic, &spr_write_generic,
2318
                 0x00000000);
2319
    /* XXX : not implemented */
2320
    spr_register(env, SPR_MPC_IMMR, "IMMR",
2321
                 SPR_NOACCESS, SPR_NOACCESS,
2322
                 &spr_read_generic, &spr_write_generic,
2323
                 0x00000000);
2324
}
2325

    
2326
static void gen_spr_5xx (CPUPPCState *env)
2327
{
2328
    /* XXX : not implemented */
2329
    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2330
                 SPR_NOACCESS, SPR_NOACCESS,
2331
                 &spr_read_generic, &spr_write_generic,
2332
                 0x00000000);
2333
    /* XXX : not implemented */
2334
    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2335
                 SPR_NOACCESS, SPR_NOACCESS,
2336
                 &spr_read_generic, &spr_write_generic,
2337
                 0x00000000);
2338
    /* XXX : not implemented */
2339
    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2340
                 SPR_NOACCESS, SPR_NOACCESS,
2341
                 &spr_read_generic, &spr_write_generic,
2342
                 0x00000000);
2343
    /* XXX : not implemented */
2344
    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2345
                 SPR_NOACCESS, SPR_NOACCESS,
2346
                 &spr_read_generic, &spr_write_generic,
2347
                 0x00000000);
2348
    /* XXX : not implemented */
2349
    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2350
                 SPR_NOACCESS, SPR_NOACCESS,
2351
                 &spr_read_generic, &spr_write_generic,
2352
                 0x00000000);
2353
    /* XXX : not implemented */
2354
    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2355
                 SPR_NOACCESS, SPR_NOACCESS,
2356
                 &spr_read_generic, &spr_write_generic,
2357
                 0x00000000);
2358
    /* XXX : not implemented */
2359
    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2360
                 SPR_NOACCESS, SPR_NOACCESS,
2361
                 &spr_read_generic, &spr_write_generic,
2362
                 0x00000000);
2363
    /* XXX : not implemented */
2364
    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2365
                 SPR_NOACCESS, SPR_NOACCESS,
2366
                 &spr_read_generic, &spr_write_generic,
2367
                 0x00000000);
2368
    /* XXX : not implemented */
2369
    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2370
                 SPR_NOACCESS, SPR_NOACCESS,
2371
                 &spr_read_generic, &spr_write_generic,
2372
                 0x00000000);
2373
    /* XXX : not implemented */
2374
    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2375
                 SPR_NOACCESS, SPR_NOACCESS,
2376
                 &spr_read_generic, &spr_write_generic,
2377
                 0x00000000);
2378
    /* XXX : not implemented */
2379
    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2380
                 SPR_NOACCESS, SPR_NOACCESS,
2381
                 &spr_read_generic, &spr_write_generic,
2382
                 0x00000000);
2383
    /* XXX : not implemented */
2384
    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2385
                 SPR_NOACCESS, SPR_NOACCESS,
2386
                 &spr_read_generic, &spr_write_generic,
2387
                 0x00000000);
2388
    /* XXX : not implemented */
2389
    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2390
                 SPR_NOACCESS, SPR_NOACCESS,
2391
                 &spr_read_generic, &spr_write_generic,
2392
                 0x00000000);
2393
    /* XXX : not implemented */
2394
    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2395
                 SPR_NOACCESS, SPR_NOACCESS,
2396
                 &spr_read_generic, &spr_write_generic,
2397
                 0x00000000);
2398
    /* XXX : not implemented */
2399
    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2400
                 SPR_NOACCESS, SPR_NOACCESS,
2401
                 &spr_read_generic, &spr_write_generic,
2402
                 0x00000000);
2403
    /* XXX : not implemented */
2404
    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2405
                 SPR_NOACCESS, SPR_NOACCESS,
2406
                 &spr_read_generic, &spr_write_generic,
2407
                 0x00000000);
2408
    /* XXX : not implemented */
2409
    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2410
                 SPR_NOACCESS, SPR_NOACCESS,
2411
                 &spr_read_generic, &spr_write_generic,
2412
                 0x00000000);
2413
    /* XXX : not implemented */
2414
    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2415
                 SPR_NOACCESS, SPR_NOACCESS,
2416
                 &spr_read_generic, &spr_write_generic,
2417
                 0x00000000);
2418
    /* XXX : not implemented */
2419
    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2420
                 SPR_NOACCESS, SPR_NOACCESS,
2421
                 &spr_read_generic, &spr_write_generic,
2422
                 0x00000000);
2423
    /* XXX : not implemented */
2424
    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2425
                 SPR_NOACCESS, SPR_NOACCESS,
2426
                 &spr_read_generic, &spr_write_generic,
2427
                 0x00000000);
2428
    /* XXX : not implemented */
2429
    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2430
                 SPR_NOACCESS, SPR_NOACCESS,
2431
                 &spr_read_generic, &spr_write_generic,
2432
                 0x00000000);
2433
}
2434

    
2435
static void gen_spr_8xx (CPUPPCState *env)
2436
{
2437
    /* XXX : not implemented */
2438
    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2439
                 SPR_NOACCESS, SPR_NOACCESS,
2440
                 &spr_read_generic, &spr_write_generic,
2441
                 0x00000000);
2442
    /* XXX : not implemented */
2443
    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2444
                 SPR_NOACCESS, SPR_NOACCESS,
2445
                 &spr_read_generic, &spr_write_generic,
2446
                 0x00000000);
2447
    /* XXX : not implemented */
2448
    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2449
                 SPR_NOACCESS, SPR_NOACCESS,
2450
                 &spr_read_generic, &spr_write_generic,
2451
                 0x00000000);
2452
    /* XXX : not implemented */
2453
    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2454
                 SPR_NOACCESS, SPR_NOACCESS,
2455
                 &spr_read_generic, &spr_write_generic,
2456
                 0x00000000);
2457
    /* XXX : not implemented */
2458
    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2459
                 SPR_NOACCESS, SPR_NOACCESS,
2460
                 &spr_read_generic, &spr_write_generic,
2461
                 0x00000000);
2462
    /* XXX : not implemented */
2463
    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2464
                 SPR_NOACCESS, SPR_NOACCESS,
2465
                 &spr_read_generic, &spr_write_generic,
2466
                 0x00000000);
2467
    /* XXX : not implemented */
2468
    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2469
                 SPR_NOACCESS, SPR_NOACCESS,
2470
                 &spr_read_generic, &spr_write_generic,
2471
                 0x00000000);
2472
    /* XXX : not implemented */
2473
    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2474
                 SPR_NOACCESS, SPR_NOACCESS,
2475
                 &spr_read_generic, &spr_write_generic,
2476
                 0x00000000);
2477
    /* XXX : not implemented */
2478
    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2479
                 SPR_NOACCESS, SPR_NOACCESS,
2480
                 &spr_read_generic, &spr_write_generic,
2481
                 0x00000000);
2482
    /* XXX : not implemented */
2483
    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2484
                 SPR_NOACCESS, SPR_NOACCESS,
2485
                 &spr_read_generic, &spr_write_generic,
2486
                 0x00000000);
2487
    /* XXX : not implemented */
2488
    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2489
                 SPR_NOACCESS, SPR_NOACCESS,
2490
                 &spr_read_generic, &spr_write_generic,
2491
                 0x00000000);
2492
    /* XXX : not implemented */
2493
    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2494
                 SPR_NOACCESS, SPR_NOACCESS,
2495
                 &spr_read_generic, &spr_write_generic,
2496
                 0x00000000);
2497
    /* XXX : not implemented */
2498
    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2499
                 SPR_NOACCESS, SPR_NOACCESS,
2500
                 &spr_read_generic, &spr_write_generic,
2501
                 0x00000000);
2502
    /* XXX : not implemented */
2503
    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2504
                 SPR_NOACCESS, SPR_NOACCESS,
2505
                 &spr_read_generic, &spr_write_generic,
2506
                 0x00000000);
2507
    /* XXX : not implemented */
2508
    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2509
                 SPR_NOACCESS, SPR_NOACCESS,
2510
                 &spr_read_generic, &spr_write_generic,
2511
                 0x00000000);
2512
    /* XXX : not implemented */
2513
    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2514
                 SPR_NOACCESS, SPR_NOACCESS,
2515
                 &spr_read_generic, &spr_write_generic,
2516
                 0x00000000);
2517
    /* XXX : not implemented */
2518
    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2519
                 SPR_NOACCESS, SPR_NOACCESS,
2520
                 &spr_read_generic, &spr_write_generic,
2521
                 0x00000000);
2522
    /* XXX : not implemented */
2523
    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2524
                 SPR_NOACCESS, SPR_NOACCESS,
2525
                 &spr_read_generic, &spr_write_generic,
2526
                 0x00000000);
2527
    /* XXX : not implemented */
2528
    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2529
                 SPR_NOACCESS, SPR_NOACCESS,
2530
                 &spr_read_generic, &spr_write_generic,
2531
                 0x00000000);
2532
    /* XXX : not implemented */
2533
    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2534
                 SPR_NOACCESS, SPR_NOACCESS,
2535
                 &spr_read_generic, &spr_write_generic,
2536
                 0x00000000);
2537
    /* XXX : not implemented */
2538
    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2539
                 SPR_NOACCESS, SPR_NOACCESS,
2540
                 &spr_read_generic, &spr_write_generic,
2541
                 0x00000000);
2542
    /* XXX : not implemented */
2543
    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2544
                 SPR_NOACCESS, SPR_NOACCESS,
2545
                 &spr_read_generic, &spr_write_generic,
2546
                 0x00000000);
2547
    /* XXX : not implemented */
2548
    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2549
                 SPR_NOACCESS, SPR_NOACCESS,
2550
                 &spr_read_generic, &spr_write_generic,
2551
                 0x00000000);
2552
    /* XXX : not implemented */
2553
    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2554
                 SPR_NOACCESS, SPR_NOACCESS,
2555
                 &spr_read_generic, &spr_write_generic,
2556
                 0x00000000);
2557
    /* XXX : not implemented */
2558
    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2559
                 SPR_NOACCESS, SPR_NOACCESS,
2560
                 &spr_read_generic, &spr_write_generic,
2561
                 0x00000000);
2562
}
2563

    
2564
// XXX: TODO
2565
/*
2566
 * AMR     => SPR 29 (Power 2.04)
2567
 * CTRL    => SPR 136 (Power 2.04)
2568
 * CTRL    => SPR 152 (Power 2.04)
2569
 * SCOMC   => SPR 276 (64 bits ?)
2570
 * SCOMD   => SPR 277 (64 bits ?)
2571
 * TBU40   => SPR 286 (Power 2.04 hypv)
2572
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2573
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2574
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2575
 * HDAR    => SPR 307 (Power 2.04 hypv)
2576
 * PURR    => SPR 309 (Power 2.04 hypv)
2577
 * HDEC    => SPR 310 (Power 2.04 hypv)
2578
 * HIOR    => SPR 311 (hypv)
2579
 * RMOR    => SPR 312 (970)
2580
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2581
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2582
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2583
 * LPCR    => SPR 316 (970)
2584
 * LPIDR   => SPR 317 (970)
2585
 * EPR     => SPR 702 (Power 2.04 emb)
2586
 * perf    => 768-783 (Power 2.04)
2587
 * perf    => 784-799 (Power 2.04)
2588
 * PPR     => SPR 896 (Power 2.04)
2589
 * EPLC    => SPR 947 (Power 2.04 emb)
2590
 * EPSC    => SPR 948 (Power 2.04 emb)
2591
 * DABRX   => 1015    (Power 2.04 hypv)
2592
 * FPECR   => SPR 1022 (?)
2593
 * ... and more (thermal management, performance counters, ...)
2594
 */
2595

    
2596
/*****************************************************************************/
2597
/* Exception vectors models                                                  */
2598
static void init_excp_4xx_real (CPUPPCState *env)
2599
{
2600
#if !defined(CONFIG_USER_ONLY)
2601
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2603
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2605
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2606
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2607
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2608
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2609
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2610
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2611
    env->hreset_excp_prefix = 0x00000000UL;
2612
    env->ivor_mask = 0x0000FFF0UL;
2613
    env->ivpr_mask = 0xFFFF0000UL;
2614
    /* Hardware reset vector */
2615
    env->hreset_vector = 0xFFFFFFFCUL;
2616
#endif
2617
}
2618

    
2619
static void init_excp_4xx_softmmu (CPUPPCState *env)
2620
{
2621
#if !defined(CONFIG_USER_ONLY)
2622
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2623
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2624
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2625
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2626
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2627
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2628
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2629
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2630
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2631
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2632
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2633
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2634
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2635
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2636
    env->hreset_excp_prefix = 0x00000000UL;
2637
    env->ivor_mask = 0x0000FFF0UL;
2638
    env->ivpr_mask = 0xFFFF0000UL;
2639
    /* Hardware reset vector */
2640
    env->hreset_vector = 0xFFFFFFFCUL;
2641
#endif
2642
}
2643

    
2644
static void init_excp_MPC5xx (CPUPPCState *env)
2645
{
2646
#if !defined(CONFIG_USER_ONLY)
2647
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2648
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2649
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2650
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2651
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2652
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2653
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2654
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2655
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2656
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2657
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2658
    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2659
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2660
    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2661
    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2662
    env->hreset_excp_prefix = 0x00000000UL;
2663
    env->ivor_mask = 0x0000FFF0UL;
2664
    env->ivpr_mask = 0xFFFF0000UL;
2665
    /* Hardware reset vector */
2666
    env->hreset_vector = 0xFFFFFFFCUL;
2667
#endif
2668
}
2669

    
2670
static void init_excp_MPC8xx (CPUPPCState *env)
2671
{
2672
#if !defined(CONFIG_USER_ONLY)
2673
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2674
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2675
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2676
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2677
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2678
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2679
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2680
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2681
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2682
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2683
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2684
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2685
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2686
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2687
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2688
    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2689
    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2690
    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2691
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2692
    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2693
    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2694
    env->hreset_excp_prefix = 0x00000000UL;
2695
    env->ivor_mask = 0x0000FFF0UL;
2696
    env->ivpr_mask = 0xFFFF0000UL;
2697
    /* Hardware reset vector */
2698
    env->hreset_vector = 0xFFFFFFFCUL;
2699
#endif
2700
}
2701

    
2702
static void init_excp_G2 (CPUPPCState *env)
2703
{
2704
#if !defined(CONFIG_USER_ONLY)
2705
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2706
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2707
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2708
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2709
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2710
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2711
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2712
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2713
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2714
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2715
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2716
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2717
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2718
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2719
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2720
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2721
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2722
    env->hreset_excp_prefix = 0x00000000UL;
2723
    /* Hardware reset vector */
2724
    env->hreset_vector = 0xFFFFFFFCUL;
2725
#endif
2726
}
2727

    
2728
static void init_excp_e200 (CPUPPCState *env)
2729
{
2730
#if !defined(CONFIG_USER_ONLY)
2731
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2732
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2733
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2734
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2735
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2736
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2737
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2738
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2739
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2740
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2741
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2742
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2743
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2744
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2745
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2746
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2747
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2748
    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2749
    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2750
    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2751
    env->hreset_excp_prefix = 0x00000000UL;
2752
    env->ivor_mask = 0x0000FFF7UL;
2753
    env->ivpr_mask = 0xFFFF0000UL;
2754
    /* Hardware reset vector */
2755
    env->hreset_vector = 0xFFFFFFFCUL;
2756
#endif
2757
}
2758

    
2759
static void init_excp_BookE (CPUPPCState *env)
2760
{
2761
#if !defined(CONFIG_USER_ONLY)
2762
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2763
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2764
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2765
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2766
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2767
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2768
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2769
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2770
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2771
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2772
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2773
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2774
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2775
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2776
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2777
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2778
    env->hreset_excp_prefix = 0x00000000UL;
2779
    env->ivor_mask = 0x0000FFE0UL;
2780
    env->ivpr_mask = 0xFFFF0000UL;
2781
    /* Hardware reset vector */
2782
    env->hreset_vector = 0xFFFFFFFCUL;
2783
#endif
2784
}
2785

    
2786
static void init_excp_601 (CPUPPCState *env)
2787
{
2788
#if !defined(CONFIG_USER_ONLY)
2789
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2790
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2791
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2792
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2793
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2794
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2795
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2796
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2797
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2798
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2799
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2800
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2801
    env->hreset_excp_prefix = 0xFFF00000UL;
2802
    /* Hardware reset vector */
2803
    env->hreset_vector = 0x00000100UL;
2804
#endif
2805
}
2806

    
2807
static void init_excp_602 (CPUPPCState *env)
2808
{
2809
#if !defined(CONFIG_USER_ONLY)
2810
    /* XXX: exception prefix has a special behavior on 602 */
2811
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2812
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2813
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2814
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2815
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2817
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2818
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2819
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2820
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2821
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2822
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2823
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2824
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2825
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2826
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2827
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2828
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2829
    env->hreset_excp_prefix = 0xFFF00000UL;
2830
    /* Hardware reset vector */
2831
    env->hreset_vector = 0xFFFFFFFCUL;
2832
#endif
2833
}
2834

    
2835
static void init_excp_603 (CPUPPCState *env)
2836
{
2837
#if !defined(CONFIG_USER_ONLY)
2838
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2839
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2840
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2841
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2842
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2844
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2845
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2846
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2847
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2848
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2849
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2850
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2851
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2852
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2853
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2854
    env->hreset_excp_prefix = 0x00000000UL;
2855
    /* Hardware reset vector */
2856
    env->hreset_vector = 0xFFFFFFFCUL;
2857
#endif
2858
}
2859

    
2860
static void init_excp_604 (CPUPPCState *env)
2861
{
2862
#if !defined(CONFIG_USER_ONLY)
2863
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2864
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2865
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2866
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2867
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2868
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2869
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2870
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2871
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2872
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2873
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2874
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2875
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2876
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2877
    env->hreset_excp_prefix = 0xFFF00000UL;
2878
    /* Hardware reset vector */
2879
    env->hreset_vector = 0x00000100UL;
2880
#endif
2881
}
2882

    
2883
#if defined(TARGET_PPC64)
2884
static void init_excp_620 (CPUPPCState *env)
2885
{
2886
#if !defined(CONFIG_USER_ONLY)
2887
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2888
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2889
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2890
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2891
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2892
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2893
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2894
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2895
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2896
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2897
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2898
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2899
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2900
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2901
    env->hreset_excp_prefix = 0xFFF00000UL;
2902
    /* Hardware reset vector */
2903
    env->hreset_vector = 0x0000000000000100ULL;
2904
#endif
2905
}
2906
#endif /* defined(TARGET_PPC64) */
2907

    
2908
static void init_excp_7x0 (CPUPPCState *env)
2909
{
2910
#if !defined(CONFIG_USER_ONLY)
2911
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2912
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2913
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2914
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2915
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2917
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2918
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2919
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2920
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2921
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2922
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2923
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2924
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2925
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2926
    env->hreset_excp_prefix = 0x00000000UL;
2927
    /* Hardware reset vector */
2928
    env->hreset_vector = 0xFFFFFFFCUL;
2929
#endif
2930
}
2931

    
2932
static void init_excp_750cl (CPUPPCState *env)
2933
{
2934
#if !defined(CONFIG_USER_ONLY)
2935
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2936
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2937
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2938
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2939
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2941
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2942
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2943
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2944
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2945
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2946
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2947
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2948
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2949
    env->hreset_excp_prefix = 0x00000000UL;
2950
    /* Hardware reset vector */
2951
    env->hreset_vector = 0xFFFFFFFCUL;
2952
#endif
2953
}
2954

    
2955
static void init_excp_750cx (CPUPPCState *env)
2956
{
2957
#if !defined(CONFIG_USER_ONLY)
2958
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2959
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2960
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2961
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2962
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2963
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2964
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2965
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2966
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2967
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2968
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2969
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2970
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2971
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2972
    env->hreset_excp_prefix = 0x00000000UL;
2973
    /* Hardware reset vector */
2974
    env->hreset_vector = 0xFFFFFFFCUL;
2975
#endif
2976
}
2977

    
2978
/* XXX: Check if this is correct */
2979
static void init_excp_7x5 (CPUPPCState *env)
2980
{
2981
#if !defined(CONFIG_USER_ONLY)
2982
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2983
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2984
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2985
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2986
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2987
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2988
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2989
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2990
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2991
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2992
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2993
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2994
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2995
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2996
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2997
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2998
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2999
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3000
    env->hreset_excp_prefix = 0x00000000UL;
3001
    /* Hardware reset vector */
3002
    env->hreset_vector = 0xFFFFFFFCUL;
3003
#endif
3004
}
3005

    
3006
static void init_excp_7400 (CPUPPCState *env)
3007
{
3008
#if !defined(CONFIG_USER_ONLY)
3009
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3010
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3011
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3012
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3013
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3014
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3015
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3016
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3017
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3018
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3019
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3020
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3021
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3022
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3023
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3024
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3025
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3026
    env->hreset_excp_prefix = 0x00000000UL;
3027
    /* Hardware reset vector */
3028
    env->hreset_vector = 0xFFFFFFFCUL;
3029
#endif
3030
}
3031

    
3032
static void init_excp_7450 (CPUPPCState *env)
3033
{
3034
#if !defined(CONFIG_USER_ONLY)
3035
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3036
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3037
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3038
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3039
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3040
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3041
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3042
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3043
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3044
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3045
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3046
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3047
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3048
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3049
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3050
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3051
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3052
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3053
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3054
    env->hreset_excp_prefix = 0x00000000UL;
3055
    /* Hardware reset vector */
3056
    env->hreset_vector = 0xFFFFFFFCUL;
3057
#endif
3058
}
3059

    
3060
#if defined (TARGET_PPC64)
3061
static void init_excp_970 (CPUPPCState *env)
3062
{
3063
#if !defined(CONFIG_USER_ONLY)
3064
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3065
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3066
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3067
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3068
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3069
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3070
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3071
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3072
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3073
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3074
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3075
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3076
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3077
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3078
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3079
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3080
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3081
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3082
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3083
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3084
    env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3085
    /* Hardware reset vector */
3086
    env->hreset_vector = 0x0000000000000100ULL;
3087
#endif
3088
}
3089
#endif
3090

    
3091
/*****************************************************************************/
3092
/* Power management enable checks                                            */
3093
static int check_pow_none (CPUPPCState *env)
3094
{
3095
    return 0;
3096
}
3097

    
3098
static int check_pow_nocheck (CPUPPCState *env)
3099
{
3100
    return 1;
3101
}
3102

    
3103
static int check_pow_hid0 (CPUPPCState *env)
3104
{
3105
    if (env->spr[SPR_HID0] & 0x00E00000)
3106
        return 1;
3107

    
3108
    return 0;
3109
}
3110

    
3111
static int check_pow_hid0_74xx (CPUPPCState *env)
3112
{
3113
    if (env->spr[SPR_HID0] & 0x00600000)
3114
        return 1;
3115

    
3116
    return 0;
3117
}
3118

    
3119
/*****************************************************************************/
3120
/* PowerPC implementations definitions                                       */
3121

    
3122
/* PowerPC 401                                                               */
3123
#define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3124
                              PPC_WRTEE | PPC_DCR |                           \
3125
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3126
                              PPC_CACHE_DCBZ |                                \
3127
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3128
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3129
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3130
#define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3131
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3132
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3133
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3134
#define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3135
                              POWERPC_FLAG_BUS_CLK)
3136
#define check_pow_401        check_pow_nocheck
3137

    
3138
static void init_proc_401 (CPUPPCState *env)
3139
{
3140
    gen_spr_40x(env);
3141
    gen_spr_401_403(env);
3142
    gen_spr_401(env);
3143
    init_excp_4xx_real(env);
3144
    env->dcache_line_size = 32;
3145
    env->icache_line_size = 32;
3146
    /* Allocate hardware IRQ controller */
3147
    ppc40x_irq_init(env);
3148
}
3149

    
3150
/* PowerPC 401x2                                                             */
3151
#define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3152
                              PPC_DCR | PPC_WRTEE |                           \
3153
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3154
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3155
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3156
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3157
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3158
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3159
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3160
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3161
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3162
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3163
#define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3164
                              POWERPC_FLAG_BUS_CLK)
3165
#define check_pow_401x2      check_pow_nocheck
3166

    
3167
static void init_proc_401x2 (CPUPPCState *env)
3168
{
3169
    gen_spr_40x(env);
3170
    gen_spr_401_403(env);
3171
    gen_spr_401x2(env);
3172
    gen_spr_compress(env);
3173
    /* Memory management */
3174
#if !defined(CONFIG_USER_ONLY)
3175
    env->nb_tlb = 64;
3176
    env->nb_ways = 1;
3177
    env->id_tlbs = 0;
3178
#endif
3179
    init_excp_4xx_softmmu(env);
3180
    env->dcache_line_size = 32;
3181
    env->icache_line_size = 32;
3182
    /* Allocate hardware IRQ controller */
3183
    ppc40x_irq_init(env);
3184
}
3185

    
3186
/* PowerPC 401x3                                                             */
3187
#define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3188
                              PPC_DCR | PPC_WRTEE |                           \
3189
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3190
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3191
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3192
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3193
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3194
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3195
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3196
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3197
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3198
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3199
#define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3200
                              POWERPC_FLAG_BUS_CLK)
3201
#define check_pow_401x3      check_pow_nocheck
3202

    
3203
__attribute__ (( unused ))
3204
static void init_proc_401x3 (CPUPPCState *env)
3205
{
3206
    gen_spr_40x(env);
3207
    gen_spr_401_403(env);
3208
    gen_spr_401(env);
3209
    gen_spr_401x2(env);
3210
    gen_spr_compress(env);
3211
    init_excp_4xx_softmmu(env);
3212
    env->dcache_line_size = 32;
3213
    env->icache_line_size = 32;
3214
    /* Allocate hardware IRQ controller */
3215
    ppc40x_irq_init(env);
3216
}
3217

    
3218
/* IOP480                                                                    */
3219
#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3220
                              PPC_DCR | PPC_WRTEE |                           \
3221
                              PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3222
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3223
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3224
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3225
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3226
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3227
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3228
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3229
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3230
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3231
#define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3232
                              POWERPC_FLAG_BUS_CLK)
3233
#define check_pow_IOP480     check_pow_nocheck
3234

    
3235
static void init_proc_IOP480 (CPUPPCState *env)
3236
{
3237
    gen_spr_40x(env);
3238
    gen_spr_401_403(env);
3239
    gen_spr_401x2(env);
3240
    gen_spr_compress(env);
3241
    /* Memory management */
3242
#if !defined(CONFIG_USER_ONLY)
3243
    env->nb_tlb = 64;
3244
    env->nb_ways = 1;
3245
    env->id_tlbs = 0;
3246
#endif
3247
    init_excp_4xx_softmmu(env);
3248
    env->dcache_line_size = 32;
3249
    env->icache_line_size = 32;
3250
    /* Allocate hardware IRQ controller */
3251
    ppc40x_irq_init(env);
3252
}
3253

    
3254
/* PowerPC 403                                                               */
3255
#define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3256
                              PPC_DCR | PPC_WRTEE |                           \
3257
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3258
                              PPC_CACHE_DCBZ |                                \
3259
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3260
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3261
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
3262
#define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3263
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3264
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3265
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3266
#define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3267
                              POWERPC_FLAG_BUS_CLK)
3268
#define check_pow_403        check_pow_nocheck
3269

    
3270
static void init_proc_403 (CPUPPCState *env)
3271
{
3272
    gen_spr_40x(env);
3273
    gen_spr_401_403(env);
3274
    gen_spr_403(env);
3275
    gen_spr_403_real(env);
3276
    init_excp_4xx_real(env);
3277
    env->dcache_line_size = 32;
3278
    env->icache_line_size = 32;
3279
    /* Allocate hardware IRQ controller */
3280
    ppc40x_irq_init(env);
3281
}
3282

    
3283
/* PowerPC 403 GCX                                                           */
3284
#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3285
                              PPC_DCR | PPC_WRTEE |                           \
3286
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3287
                              PPC_CACHE_DCBZ |                                \
3288
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3289
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3290
                              PPC_4xx_COMMON | PPC_40x_EXCP)
3291
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3292
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3293
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3294
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3295
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3296
#define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3297
                              POWERPC_FLAG_BUS_CLK)
3298
#define check_pow_403GCX     check_pow_nocheck
3299

    
3300
static void init_proc_403GCX (CPUPPCState *env)
3301
{
3302
    gen_spr_40x(env);
3303
    gen_spr_401_403(env);
3304
    gen_spr_403(env);
3305
    gen_spr_403_real(env);
3306
    gen_spr_403_mmu(env);
3307
    /* Bus access control */
3308
    /* not emulated, as Qemu never does speculative access */
3309
    spr_register(env, SPR_40x_SGR, "SGR",
3310
                 SPR_NOACCESS, SPR_NOACCESS,
3311
                 &spr_read_generic, &spr_write_generic,
3312
                 0xFFFFFFFF);
3313
    /* not emulated, as Qemu do not emulate caches */
3314
    spr_register(env, SPR_40x_DCWR, "DCWR",
3315
                 SPR_NOACCESS, SPR_NOACCESS,
3316
                 &spr_read_generic, &spr_write_generic,
3317
                 0x00000000);
3318
    /* Memory management */
3319
#if !defined(CONFIG_USER_ONLY)
3320
    env->nb_tlb = 64;
3321
    env->nb_ways = 1;
3322
    env->id_tlbs = 0;
3323
#endif
3324
    init_excp_4xx_softmmu(env);
3325
    env->dcache_line_size = 32;
3326
    env->icache_line_size = 32;
3327
    /* Allocate hardware IRQ controller */
3328
    ppc40x_irq_init(env);
3329
}
3330

    
3331
/* PowerPC 405                                                               */
3332
#define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3333
                              PPC_DCR | PPC_WRTEE |                           \
3334
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3335
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3336
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3337
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3338
                              PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3339
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
3340
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3341
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3342
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3343
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3344
#define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3345
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3346
#define check_pow_405        check_pow_nocheck
3347

    
3348
static void init_proc_405 (CPUPPCState *env)
3349
{
3350
    /* Time base */
3351
    gen_tbl(env);
3352
    gen_spr_40x(env);
3353
    gen_spr_405(env);
3354
    /* Bus access control */
3355
    /* not emulated, as Qemu never does speculative access */
3356
    spr_register(env, SPR_40x_SGR, "SGR",
3357
                 SPR_NOACCESS, SPR_NOACCESS,
3358
                 &spr_read_generic, &spr_write_generic,
3359
                 0xFFFFFFFF);
3360
    /* not emulated, as Qemu do not emulate caches */
3361
    spr_register(env, SPR_40x_DCWR, "DCWR",
3362
                 SPR_NOACCESS, SPR_NOACCESS,
3363
                 &spr_read_generic, &spr_write_generic,
3364
                 0x00000000);
3365
    /* Memory management */
3366
#if !defined(CONFIG_USER_ONLY)
3367
    env->nb_tlb = 64;
3368
    env->nb_ways = 1;
3369
    env->id_tlbs = 0;
3370
#endif
3371
    init_excp_4xx_softmmu(env);
3372
    env->dcache_line_size = 32;
3373
    env->icache_line_size = 32;
3374
    /* Allocate hardware IRQ controller */
3375
    ppc40x_irq_init(env);
3376
}
3377

    
3378
/* PowerPC 440 EP                                                            */
3379
#define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3380
                              PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3381
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3382
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3383
                              PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3384
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3385
                              PPC_440_SPEC)
3386
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3387
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3388
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3389
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3390
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3391
#define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3392
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3393
#define check_pow_440EP      check_pow_nocheck
3394

    
3395
__attribute__ (( unused ))
3396
static void init_proc_440EP (CPUPPCState *env)
3397
{
3398
    /* Time base */
3399
    gen_tbl(env);
3400
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3401
    gen_spr_440(env);
3402
    gen_spr_usprgh(env);
3403
    /* Processor identification */
3404
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3405
                 SPR_NOACCESS, SPR_NOACCESS,
3406
                 &spr_read_generic, &spr_write_pir,
3407
                 0x00000000);
3408
    /* XXX : not implemented */
3409
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3410
                 SPR_NOACCESS, SPR_NOACCESS,
3411
                 &spr_read_generic, &spr_write_generic,
3412
                 0x00000000);
3413
    /* XXX : not implemented */
3414
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3415
                 SPR_NOACCESS, SPR_NOACCESS,
3416
                 &spr_read_generic, &spr_write_generic,
3417
                 0x00000000);
3418
    /* XXX : not implemented */
3419
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3420
                 SPR_NOACCESS, SPR_NOACCESS,
3421
                 &spr_read_generic, &spr_write_generic,
3422
                 0x00000000);
3423
    /* XXX : not implemented */
3424
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3425
                 SPR_NOACCESS, SPR_NOACCESS,
3426
                 &spr_read_generic, &spr_write_generic,
3427
                 0x00000000);
3428
    /* XXX : not implemented */
3429
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3430
                 SPR_NOACCESS, SPR_NOACCESS,
3431
                 &spr_read_generic, &spr_write_generic,
3432
                 0x00000000);
3433
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3434
                 SPR_NOACCESS, SPR_NOACCESS,
3435
                 &spr_read_generic, &spr_write_generic,
3436
                 0x00000000);
3437
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3438
                 SPR_NOACCESS, SPR_NOACCESS,
3439
                 &spr_read_generic, &spr_write_generic,
3440
                 0x00000000);
3441
    /* XXX : not implemented */
3442
    spr_register(env, SPR_440_CCR1, "CCR1",
3443
                 SPR_NOACCESS, SPR_NOACCESS,
3444
                 &spr_read_generic, &spr_write_generic,
3445
                 0x00000000);
3446
    /* Memory management */
3447
#if !defined(CONFIG_USER_ONLY)
3448
    env->nb_tlb = 64;
3449
    env->nb_ways = 1;
3450
    env->id_tlbs = 0;
3451
#endif
3452
    init_excp_BookE(env);
3453
    env->dcache_line_size = 32;
3454
    env->icache_line_size = 32;
3455
    /* XXX: TODO: allocate internal IRQ controller */
3456
}
3457

    
3458
/* PowerPC 440 GP                                                            */
3459
#define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3460
                              PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3461
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3462
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3463
                              PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |       \
3464
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3465
                              PPC_440_SPEC)
3466
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3467
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3468
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3469
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3470
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3471
#define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3472
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3473
#define check_pow_440GP      check_pow_nocheck
3474

    
3475
__attribute__ (( unused ))
3476
static void init_proc_440GP (CPUPPCState *env)
3477
{
3478
    /* Time base */
3479
    gen_tbl(env);
3480
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3481
    gen_spr_440(env);
3482
    gen_spr_usprgh(env);
3483
    /* Processor identification */
3484
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3485
                 SPR_NOACCESS, SPR_NOACCESS,
3486
                 &spr_read_generic, &spr_write_pir,
3487
                 0x00000000);
3488
    /* XXX : not implemented */
3489
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3490
                 SPR_NOACCESS, SPR_NOACCESS,
3491
                 &spr_read_generic, &spr_write_generic,
3492
                 0x00000000);
3493
    /* XXX : not implemented */
3494
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3495
                 SPR_NOACCESS, SPR_NOACCESS,
3496
                 &spr_read_generic, &spr_write_generic,
3497
                 0x00000000);
3498
    /* XXX : not implemented */
3499
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3500
                 SPR_NOACCESS, SPR_NOACCESS,
3501
                 &spr_read_generic, &spr_write_generic,
3502
                 0x00000000);
3503
    /* XXX : not implemented */
3504
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3505
                 SPR_NOACCESS, SPR_NOACCESS,
3506
                 &spr_read_generic, &spr_write_generic,
3507
                 0x00000000);
3508
    /* Memory management */
3509
#if !defined(CONFIG_USER_ONLY)
3510
    env->nb_tlb = 64;
3511
    env->nb_ways = 1;
3512
    env->id_tlbs = 0;
3513
#endif
3514
    init_excp_BookE(env);
3515
    env->dcache_line_size = 32;
3516
    env->icache_line_size = 32;
3517
    /* XXX: TODO: allocate internal IRQ controller */
3518
}
3519

    
3520
/* PowerPC 440x4                                                             */
3521
#define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3522
                              PPC_DCR | PPC_WRTEE |                           \
3523
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3524
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3525
                              PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3526
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3527
                              PPC_440_SPEC)
3528
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3529
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3530
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3531
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3532
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3533
#define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3534
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3535
#define check_pow_440x4      check_pow_nocheck
3536

    
3537
__attribute__ (( unused ))
3538
static void init_proc_440x4 (CPUPPCState *env)
3539
{
3540
    /* Time base */
3541
    gen_tbl(env);
3542
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3543
    gen_spr_440(env);
3544
    gen_spr_usprgh(env);
3545
    /* Processor identification */
3546
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3547
                 SPR_NOACCESS, SPR_NOACCESS,
3548
                 &spr_read_generic, &spr_write_pir,
3549
                 0x00000000);
3550
    /* XXX : not implemented */
3551
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3552
                 SPR_NOACCESS, SPR_NOACCESS,
3553
                 &spr_read_generic, &spr_write_generic,
3554
                 0x00000000);
3555
    /* XXX : not implemented */
3556
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3557
                 SPR_NOACCESS, SPR_NOACCESS,
3558
                 &spr_read_generic, &spr_write_generic,
3559
                 0x00000000);
3560
    /* XXX : not implemented */
3561
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3562
                 SPR_NOACCESS, SPR_NOACCESS,
3563
                 &spr_read_generic, &spr_write_generic,
3564
                 0x00000000);
3565
    /* XXX : not implemented */
3566
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3567
                 SPR_NOACCESS, SPR_NOACCESS,
3568
                 &spr_read_generic, &spr_write_generic,
3569
                 0x00000000);
3570
    /* Memory management */
3571
#if !defined(CONFIG_USER_ONLY)
3572
    env->nb_tlb = 64;
3573
    env->nb_ways = 1;
3574
    env->id_tlbs = 0;
3575
#endif
3576
    init_excp_BookE(env);
3577
    env->dcache_line_size = 32;
3578
    env->icache_line_size = 32;
3579
    /* XXX: TODO: allocate internal IRQ controller */
3580
}
3581

    
3582
/* PowerPC 440x5                                                             */
3583
#define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3584
                              PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3585
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3586
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3587
                              PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3588
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3589
                              PPC_440_SPEC)
3590
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3591
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3592
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3593
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3594
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3595
#define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3596
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3597
#define check_pow_440x5      check_pow_nocheck
3598

    
3599
static void init_proc_440x5 (CPUPPCState *env)
3600
{
3601
    /* Time base */
3602
    gen_tbl(env);
3603
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3604
    gen_spr_440(env);
3605
    gen_spr_usprgh(env);
3606
    /* Processor identification */
3607
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3608
                 SPR_NOACCESS, SPR_NOACCESS,
3609
                 &spr_read_generic, &spr_write_pir,
3610
                 0x00000000);
3611
    /* XXX : not implemented */
3612
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3613
                 SPR_NOACCESS, SPR_NOACCESS,
3614
                 &spr_read_generic, &spr_write_generic,
3615
                 0x00000000);
3616
    /* XXX : not implemented */
3617
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3618
                 SPR_NOACCESS, SPR_NOACCESS,
3619
                 &spr_read_generic, &spr_write_generic,
3620
                 0x00000000);
3621
    /* XXX : not implemented */
3622
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3623
                 SPR_NOACCESS, SPR_NOACCESS,
3624
                 &spr_read_generic, &spr_write_generic,
3625
                 0x00000000);
3626
    /* XXX : not implemented */
3627
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3628
                 SPR_NOACCESS, SPR_NOACCESS,
3629
                 &spr_read_generic, &spr_write_generic,
3630
                 0x00000000);
3631
    /* XXX : not implemented */
3632
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3633
                 SPR_NOACCESS, SPR_NOACCESS,
3634
                 &spr_read_generic, &spr_write_generic,
3635
                 0x00000000);
3636
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3637
                 SPR_NOACCESS, SPR_NOACCESS,
3638
                 &spr_read_generic, &spr_write_generic,
3639
                 0x00000000);
3640
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3641
                 SPR_NOACCESS, SPR_NOACCESS,
3642
                 &spr_read_generic, &spr_write_generic,
3643
                 0x00000000);
3644
    /* XXX : not implemented */
3645
    spr_register(env, SPR_440_CCR1, "CCR1",
3646
                 SPR_NOACCESS, SPR_NOACCESS,
3647
                 &spr_read_generic, &spr_write_generic,
3648
                 0x00000000);
3649
    /* Memory management */
3650
#if !defined(CONFIG_USER_ONLY)
3651
    env->nb_tlb = 64;
3652
    env->nb_ways = 1;
3653
    env->id_tlbs = 0;
3654
#endif
3655
    init_excp_BookE(env);
3656
    env->dcache_line_size = 32;
3657
    env->icache_line_size = 32;
3658
    ppc40x_irq_init(env);
3659
}
3660

    
3661
/* PowerPC 460 (guessed)                                                     */
3662
#define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3663
                              PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3664
                              PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |            \
3665
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3666
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3667
                              PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3668
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3669
                              PPC_440_SPEC)
3670
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3671
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3672
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3673
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3674
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3675
#define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3676
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3677
#define check_pow_460        check_pow_nocheck
3678

    
3679
__attribute__ (( unused ))
3680
static void init_proc_460 (CPUPPCState *env)
3681
{
3682
    /* Time base */
3683
    gen_tbl(env);
3684
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3685
    gen_spr_440(env);
3686
    gen_spr_usprgh(env);
3687
    /* Processor identification */
3688
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3689
                 SPR_NOACCESS, SPR_NOACCESS,
3690
                 &spr_read_generic, &spr_write_pir,
3691
                 0x00000000);
3692
    /* XXX : not implemented */
3693
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3694
                 SPR_NOACCESS, SPR_NOACCESS,
3695
                 &spr_read_generic, &spr_write_generic,
3696
                 0x00000000);
3697
    /* XXX : not implemented */
3698
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3699
                 SPR_NOACCESS, SPR_NOACCESS,
3700
                 &spr_read_generic, &spr_write_generic,
3701
                 0x00000000);
3702
    /* XXX : not implemented */
3703
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3704
                 SPR_NOACCESS, SPR_NOACCESS,
3705
                 &spr_read_generic, &spr_write_generic,
3706
                 0x00000000);
3707
    /* XXX : not implemented */
3708
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3709
                 SPR_NOACCESS, SPR_NOACCESS,
3710
                 &spr_read_generic, &spr_write_generic,
3711
                 0x00000000);
3712
    /* XXX : not implemented */
3713
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3714
                 SPR_NOACCESS, SPR_NOACCESS,
3715
                 &spr_read_generic, &spr_write_generic,
3716
                 0x00000000);
3717
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3718
                 SPR_NOACCESS, SPR_NOACCESS,
3719
                 &spr_read_generic, &spr_write_generic,
3720
                 0x00000000);
3721
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3722
                 SPR_NOACCESS, SPR_NOACCESS,
3723
                 &spr_read_generic, &spr_write_generic,
3724
                 0x00000000);
3725
    /* XXX : not implemented */
3726
    spr_register(env, SPR_440_CCR1, "CCR1",
3727
                 SPR_NOACCESS, SPR_NOACCESS,
3728
                 &spr_read_generic, &spr_write_generic,
3729
                 0x00000000);
3730
    /* XXX : not implemented */
3731
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3732
                 &spr_read_generic, &spr_write_generic,
3733
                 &spr_read_generic, &spr_write_generic,
3734
                 0x00000000);
3735
    /* Memory management */
3736
#if !defined(CONFIG_USER_ONLY)
3737
    env->nb_tlb = 64;
3738
    env->nb_ways = 1;
3739
    env->id_tlbs = 0;
3740
#endif
3741
    init_excp_BookE(env);
3742
    env->dcache_line_size = 32;
3743
    env->icache_line_size = 32;
3744
    /* XXX: TODO: allocate internal IRQ controller */
3745
}
3746

    
3747
/* PowerPC 460F (guessed)                                                    */
3748
#define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3749
                              PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3750
                              PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3751
                              PPC_FLOAT_STFIWX | PPC_MFTB |                   \
3752
                              PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3753
                              PPC_WRTEE | PPC_MFAPIDI |                       \
3754
                              PPC_CACHE | PPC_CACHE_ICBI |                    \
3755
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3756
                              PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3757
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3758
                              PPC_440_SPEC)
3759
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3760
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3761
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3762
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3763
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3764
#define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3765
                              POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3766
#define check_pow_460F       check_pow_nocheck
3767

    
3768
__attribute__ (( unused ))
3769
static void init_proc_460F (CPUPPCState *env)
3770
{
3771
    /* Time base */
3772
    gen_tbl(env);
3773
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3774
    gen_spr_440(env);
3775
    gen_spr_usprgh(env);
3776
    /* Processor identification */
3777
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3778
                 SPR_NOACCESS, SPR_NOACCESS,
3779
                 &spr_read_generic, &spr_write_pir,
3780
                 0x00000000);
3781
    /* XXX : not implemented */
3782
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3783
                 SPR_NOACCESS, SPR_NOACCESS,
3784
                 &spr_read_generic, &spr_write_generic,
3785
                 0x00000000);
3786
    /* XXX : not implemented */
3787
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3788
                 SPR_NOACCESS, SPR_NOACCESS,
3789
                 &spr_read_generic, &spr_write_generic,
3790
                 0x00000000);
3791
    /* XXX : not implemented */
3792
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3793
                 SPR_NOACCESS, SPR_NOACCESS,
3794
                 &spr_read_generic, &spr_write_generic,
3795
                 0x00000000);
3796
    /* XXX : not implemented */
3797
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3798
                 SPR_NOACCESS, SPR_NOACCESS,
3799
                 &spr_read_generic, &spr_write_generic,
3800
                 0x00000000);
3801
    /* XXX : not implemented */
3802
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3803
                 SPR_NOACCESS, SPR_NOACCESS,
3804
                 &spr_read_generic, &spr_write_generic,
3805
                 0x00000000);
3806
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3807
                 SPR_NOACCESS, SPR_NOACCESS,
3808
                 &spr_read_generic, &spr_write_generic,
3809
                 0x00000000);
3810
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3811
                 SPR_NOACCESS, SPR_NOACCESS,
3812
                 &spr_read_generic, &spr_write_generic,
3813
                 0x00000000);
3814
    /* XXX : not implemented */
3815
    spr_register(env, SPR_440_CCR1, "CCR1",
3816
                 SPR_NOACCESS, SPR_NOACCESS,
3817
                 &spr_read_generic, &spr_write_generic,
3818
                 0x00000000);
3819
    /* XXX : not implemented */
3820
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3821
                 &spr_read_generic, &spr_write_generic,
3822
                 &spr_read_generic, &spr_write_generic,
3823
                 0x00000000);
3824
    /* Memory management */
3825
#if !defined(CONFIG_USER_ONLY)
3826
    env->nb_tlb = 64;
3827
    env->nb_ways = 1;
3828
    env->id_tlbs = 0;
3829
#endif
3830
    init_excp_BookE(env);
3831
    env->dcache_line_size = 32;
3832
    env->icache_line_size = 32;
3833
    /* XXX: TODO: allocate internal IRQ controller */
3834
}
3835

    
3836
/* Freescale 5xx cores (aka RCPU) */
3837
#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3838
                              PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3839
                              PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3840
                              PPC_MFTB)
3841
#define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3842
#define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3843
#define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3844
#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3845
#define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3846
#define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3847
                              POWERPC_FLAG_BUS_CLK)
3848
#define check_pow_MPC5xx     check_pow_none
3849

    
3850
__attribute__ (( unused ))
3851
static void init_proc_MPC5xx (CPUPPCState *env)
3852
{
3853
    /* Time base */
3854
    gen_tbl(env);
3855
    gen_spr_5xx_8xx(env);
3856
    gen_spr_5xx(env);
3857
    init_excp_MPC5xx(env);
3858
    env->dcache_line_size = 32;
3859
    env->icache_line_size = 32;
3860
    /* XXX: TODO: allocate internal IRQ controller */
3861
}
3862

    
3863
/* Freescale 8xx cores (aka PowerQUICC) */
3864
#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3865
                              PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3866
                              PPC_CACHE_ICBI | PPC_MFTB)
3867
#define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3868
#define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3869
#define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3870
#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3871
#define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3872
#define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3873
                              POWERPC_FLAG_BUS_CLK)
3874
#define check_pow_MPC8xx     check_pow_none
3875

    
3876
__attribute__ (( unused ))
3877
static void init_proc_MPC8xx (CPUPPCState *env)
3878
{
3879
    /* Time base */
3880
    gen_tbl(env);
3881
    gen_spr_5xx_8xx(env);
3882
    gen_spr_8xx(env);
3883
    init_excp_MPC8xx(env);
3884
    env->dcache_line_size = 32;
3885
    env->icache_line_size = 32;
3886
    /* XXX: TODO: allocate internal IRQ controller */
3887
}
3888

    
3889
/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3890
/* PowerPC G2                                                                */
3891
#define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3892
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3893
                              PPC_FLOAT_STFIWX |                              \
3894
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3895
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3896
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3897
                              PPC_SEGMENT | PPC_EXTERN)
3898
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3899
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3900
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3901
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3902
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3903
#define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3904
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3905
#define check_pow_G2         check_pow_hid0
3906

    
3907
static void init_proc_G2 (CPUPPCState *env)
3908
{
3909
    gen_spr_ne_601(env);
3910
    gen_spr_G2_755(env);
3911
    gen_spr_G2(env);
3912
    /* Time base */
3913
    gen_tbl(env);
3914
    /* External access control */
3915
    /* XXX : not implemented */
3916
    spr_register(env, SPR_EAR, "EAR",
3917
                 SPR_NOACCESS, SPR_NOACCESS,
3918
                 &spr_read_generic, &spr_write_generic,
3919
                 0x00000000);
3920
    /* Hardware implementation register */
3921
    /* XXX : not implemented */
3922
    spr_register(env, SPR_HID0, "HID0",
3923
                 SPR_NOACCESS, SPR_NOACCESS,
3924
                 &spr_read_generic, &spr_write_generic,
3925
                 0x00000000);
3926
    /* XXX : not implemented */
3927
    spr_register(env, SPR_HID1, "HID1",
3928
                 SPR_NOACCESS, SPR_NOACCESS,
3929
                 &spr_read_generic, &spr_write_generic,
3930
                 0x00000000);
3931
    /* XXX : not implemented */
3932
    spr_register(env, SPR_HID2, "HID2",
3933
                 SPR_NOACCESS, SPR_NOACCESS,
3934
                 &spr_read_generic, &spr_write_generic,
3935
                 0x00000000);
3936
    /* Memory management */
3937
    gen_low_BATs(env);
3938
    gen_high_BATs(env);
3939
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3940
    init_excp_G2(env);
3941
    env->dcache_line_size = 32;
3942
    env->icache_line_size = 32;
3943
    /* Allocate hardware IRQ controller */
3944
    ppc6xx_irq_init(env);
3945
}
3946

    
3947
/* PowerPC G2LE                                                              */
3948
#define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3949
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3950
                              PPC_FLOAT_STFIWX |                              \
3951
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3952
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3953
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3954
                              PPC_SEGMENT | PPC_EXTERN)
3955
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3956
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3957
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3958
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3959
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3960
#define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3961
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3962
#define check_pow_G2LE       check_pow_hid0
3963

    
3964
static void init_proc_G2LE (CPUPPCState *env)
3965
{
3966
    gen_spr_ne_601(env);
3967
    gen_spr_G2_755(env);
3968
    gen_spr_G2(env);
3969
    /* Time base */
3970
    gen_tbl(env);
3971
    /* External access control */
3972
    /* XXX : not implemented */
3973
    spr_register(env, SPR_EAR, "EAR",
3974
                 SPR_NOACCESS, SPR_NOACCESS,
3975
                 &spr_read_generic, &spr_write_generic,
3976
                 0x00000000);
3977
    /* Hardware implementation register */
3978
    /* XXX : not implemented */
3979
    spr_register(env, SPR_HID0, "HID0",
3980
                 SPR_NOACCESS, SPR_NOACCESS,
3981
                 &spr_read_generic, &spr_write_generic,
3982
                 0x00000000);
3983
    /* XXX : not implemented */
3984
    spr_register(env, SPR_HID1, "HID1",
3985
                 SPR_NOACCESS, SPR_NOACCESS,
3986
                 &spr_read_generic, &spr_write_generic,
3987
                 0x00000000);
3988
    /* XXX : not implemented */
3989
    spr_register(env, SPR_HID2, "HID2",
3990
                 SPR_NOACCESS, SPR_NOACCESS,
3991
                 &spr_read_generic, &spr_write_generic,
3992
                 0x00000000);
3993
    /* Memory management */
3994
    gen_low_BATs(env);
3995
    gen_high_BATs(env);
3996
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3997
    init_excp_G2(env);
3998
    env->dcache_line_size = 32;
3999
    env->icache_line_size = 32;
4000
    /* Allocate hardware IRQ controller */
4001
    ppc6xx_irq_init(env);
4002
}
4003

    
4004
/* e200 core                                                                 */
4005
/* XXX: unimplemented instructions:
4006
 * dcblc
4007
 * dcbtlst
4008
 * dcbtstls
4009
 * icblc
4010
 * icbtls
4011
 * tlbivax
4012
 * all SPE multiply-accumulate instructions
4013
 */
4014
#define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
4015
                              PPC_SPE | PPC_SPE_SINGLE |                      \
4016
                              PPC_WRTEE | PPC_RFDI |                          \
4017
                              PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4018
                              PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4019
                              PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4020
                              PPC_BOOKE)
4021
#define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
4022
#define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
4023
#define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
4024
#define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
4025
#define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
4026
#define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4027
                              POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4028
                              POWERPC_FLAG_BUS_CLK)
4029
#define check_pow_e200       check_pow_hid0
4030

    
4031
__attribute__ (( unused ))
4032
static void init_proc_e200 (CPUPPCState *env)
4033
{
4034
    /* Time base */
4035
    gen_tbl(env);
4036
    gen_spr_BookE(env, 0x000000070000FFFFULL);
4037
    /* XXX : not implemented */
4038
    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4039
                 &spr_read_spefscr, &spr_write_spefscr,
4040
                 &spr_read_spefscr, &spr_write_spefscr,
4041
                 0x00000000);
4042
    /* Memory management */
4043
    gen_spr_BookE_FSL(env, 0x0000005D);
4044
    /* XXX : not implemented */
4045
    spr_register(env, SPR_HID0, "HID0",
4046
                 SPR_NOACCESS, SPR_NOACCESS,
4047
                 &spr_read_generic, &spr_write_generic,
4048
                 0x00000000);
4049
    /* XXX : not implemented */
4050
    spr_register(env, SPR_HID1, "HID1",
4051
                 SPR_NOACCESS, SPR_NOACCESS,
4052
                 &spr_read_generic, &spr_write_generic,
4053
                 0x00000000);
4054
    /* XXX : not implemented */
4055
    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4056
                 SPR_NOACCESS, SPR_NOACCESS,
4057
                 &spr_read_generic, &spr_write_generic,
4058
                 0x00000000);
4059
    /* XXX : not implemented */
4060
    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4061
                 SPR_NOACCESS, SPR_NOACCESS,
4062
                 &spr_read_generic, &spr_write_generic,
4063
                 0x00000000);
4064
    /* XXX : not implemented */
4065
    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4066
                 SPR_NOACCESS, SPR_NOACCESS,
4067
                 &spr_read_generic, &spr_write_generic,
4068
                 0x00000000);
4069
    /* XXX : not implemented */
4070
    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4071
                 SPR_NOACCESS, SPR_NOACCESS,
4072
                 &spr_read_generic, &spr_write_generic,
4073
                 0x00000000);
4074
    /* XXX : not implemented */
4075
    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4076
                 SPR_NOACCESS, SPR_NOACCESS,
4077
                 &spr_read_generic, &spr_write_generic,
4078
                 0x00000000);
4079
    /* XXX : not implemented */
4080
    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4081
                 SPR_NOACCESS, SPR_NOACCESS,
4082
                 &spr_read_generic, &spr_write_generic,
4083
                 0x00000000);
4084
    /* XXX : not implemented */
4085
    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4086
                 SPR_NOACCESS, SPR_NOACCESS,
4087
                 &spr_read_generic, &spr_write_generic,
4088
                 0x00000000);
4089
    /* XXX : not implemented */
4090
    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4091
                 SPR_NOACCESS, SPR_NOACCESS,
4092
                 &spr_read_generic, &spr_write_generic,
4093
                 0x00000000);
4094
    /* XXX : not implemented */
4095
    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4096
                 SPR_NOACCESS, SPR_NOACCESS,
4097
                 &spr_read_generic, &spr_write_generic,
4098
                 0x00000000);
4099
    /* XXX : not implemented */
4100
    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4101
                 SPR_NOACCESS, SPR_NOACCESS,
4102
                 &spr_read_generic, &spr_write_generic,
4103
                 0x00000000);
4104
    /* XXX : not implemented */
4105
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4106
                 SPR_NOACCESS, SPR_NOACCESS,
4107
                 &spr_read_generic, &spr_write_generic,
4108
                 0x00000000);
4109
    /* XXX : not implemented */
4110
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4111
                 SPR_NOACCESS, SPR_NOACCESS,
4112
                 &spr_read_generic, &spr_write_generic,
4113
                 0x00000000);
4114
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4115
                 SPR_NOACCESS, SPR_NOACCESS,
4116
                 &spr_read_generic, &spr_write_generic,
4117
                 0x00000000);
4118
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4119
                 SPR_NOACCESS, SPR_NOACCESS,
4120
                 &spr_read_generic, &spr_write_generic,
4121
                 0x00000000);
4122
#if !defined(CONFIG_USER_ONLY)
4123
    env->nb_tlb = 64;
4124
    env->nb_ways = 1;
4125
    env->id_tlbs = 0;
4126
#endif
4127
    init_excp_e200(env);
4128
    env->dcache_line_size = 32;
4129
    env->icache_line_size = 32;
4130
    /* XXX: TODO: allocate internal IRQ controller */
4131
}
4132

    
4133
/* e300 core                                                                 */
4134
#define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4135
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4136
                              PPC_FLOAT_STFIWX |                              \
4137
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4138
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4139
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4140
                              PPC_SEGMENT | PPC_EXTERN)
4141
#define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4142
#define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4143
#define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4144
#define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4145
#define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4146
#define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4147
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4148
#define check_pow_e300       check_pow_hid0
4149

    
4150
__attribute__ (( unused ))
4151
static void init_proc_e300 (CPUPPCState *env)
4152
{
4153
    gen_spr_ne_601(env);
4154
    gen_spr_603(env);
4155
    /* Time base */
4156
    gen_tbl(env);
4157
    /* hardware implementation registers */
4158
    /* XXX : not implemented */
4159
    spr_register(env, SPR_HID0, "HID0",
4160
                 SPR_NOACCESS, SPR_NOACCESS,
4161
                 &spr_read_generic, &spr_write_generic,
4162
                 0x00000000);
4163
    /* XXX : not implemented */
4164
    spr_register(env, SPR_HID1, "HID1",
4165
                 SPR_NOACCESS, SPR_NOACCESS,
4166
                 &spr_read_generic, &spr_write_generic,
4167
                 0x00000000);
4168
    /* XXX : not implemented */
4169
    spr_register(env, SPR_HID2, "HID2",
4170
                 SPR_NOACCESS, SPR_NOACCESS,
4171
                 &spr_read_generic, &spr_write_generic,
4172
                 0x00000000);
4173
    /* Memory management */
4174
    gen_low_BATs(env);
4175
    gen_high_BATs(env);
4176
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4177
    init_excp_603(env);
4178
    env->dcache_line_size = 32;
4179
    env->icache_line_size = 32;
4180
    /* Allocate hardware IRQ controller */
4181
    ppc6xx_irq_init(env);
4182
}
4183

    
4184
/* e500v1 core                                                               */
4185
#define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
4186
                                PPC_SPE | PPC_SPE_SINGLE |              \
4187
                                PPC_WRTEE | PPC_RFDI |                  \
4188
                                PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4189
                                PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4190
                                PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4191
                                PPC_BOOKE)
4192
#define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
4193
#define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE_FSL)
4194
#define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
4195
#define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
4196
#define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
4197
#define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4198
                                POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4199
                                POWERPC_FLAG_BUS_CLK)
4200
#define check_pow_e500v1       check_pow_hid0
4201
#define init_proc_e500v1       init_proc_e500
4202

    
4203
/* e500v2 core                                                               */
4204
#define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
4205
                                PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4206
                                PPC_WRTEE | PPC_RFDI |                  \
4207
                                PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4208
                                PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4209
                                PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4210
                                PPC_BOOKE)
4211
#define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
4212
#define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE_FSL)
4213
#define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
4214
#define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
4215
#define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
4216
#define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4217
                                POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4218
                                POWERPC_FLAG_BUS_CLK)
4219
#define check_pow_e500v2       check_pow_hid0
4220
#define init_proc_e500v2       init_proc_e500
4221

    
4222
static void init_proc_e500 (CPUPPCState *env)
4223
{
4224
    /* Time base */
4225
    gen_tbl(env);
4226
    gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4227
    /* Processor identification */
4228
    spr_register(env, SPR_BOOKE_PIR, "PIR",
4229
                 SPR_NOACCESS, SPR_NOACCESS,
4230
                 &spr_read_generic, &spr_write_pir,
4231
                 0x00000000);
4232
    /* XXX : not implemented */
4233
    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4234
                 &spr_read_spefscr, &spr_write_spefscr,
4235
                 &spr_read_spefscr, &spr_write_spefscr,
4236
                 0x00000000);
4237
    /* Memory management */
4238
#if !defined(CONFIG_USER_ONLY)
4239
    env->nb_pids = 3;
4240
#endif
4241
    gen_spr_BookE_FSL(env, 0x0000005F);
4242
    /* XXX : not implemented */
4243
    spr_register(env, SPR_HID0, "HID0",
4244
                 SPR_NOACCESS, SPR_NOACCESS,
4245
                 &spr_read_generic, &spr_write_generic,
4246
                 0x00000000);
4247
    /* XXX : not implemented */
4248
    spr_register(env, SPR_HID1, "HID1",
4249
                 SPR_NOACCESS, SPR_NOACCESS,
4250
                 &spr_read_generic, &spr_write_generic,
4251
                 0x00000000);
4252
    /* XXX : not implemented */
4253
    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4254
                 SPR_NOACCESS, SPR_NOACCESS,
4255
                 &spr_read_generic, &spr_write_generic,
4256
                 0x00000000);
4257
    /* XXX : not implemented */
4258
    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4259
                 SPR_NOACCESS, SPR_NOACCESS,
4260
                 &spr_read_generic, &spr_write_generic,
4261
                 0x00000000);
4262
    /* XXX : not implemented */
4263
    spr_register(env, SPR_Exxx_MCAR, "MCAR",
4264
                 SPR_NOACCESS, SPR_NOACCESS,
4265
                 &spr_read_generic, &spr_write_generic,
4266
                 0x00000000);
4267
    /* XXX : not implemented */
4268
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4269
                 SPR_NOACCESS, SPR_NOACCESS,
4270
                 &spr_read_generic, &spr_write_generic,
4271
                 0x00000000);
4272
    /* XXX : not implemented */
4273
    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4274
                 SPR_NOACCESS, SPR_NOACCESS,
4275
                 &spr_read_generic, &spr_write_generic,
4276
                 0x00000000);
4277
    /* XXX : not implemented */
4278
    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4279
                 SPR_NOACCESS, SPR_NOACCESS,
4280
                 &spr_read_generic, &spr_write_generic,
4281
                 0x00000000);
4282
    /* XXX : not implemented */
4283
    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4284
                 SPR_NOACCESS, SPR_NOACCESS,
4285
                 &spr_read_generic, &spr_write_generic,
4286
                 0x00000000);
4287
    /* XXX : not implemented */
4288
    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4289
                 SPR_NOACCESS, SPR_NOACCESS,
4290
                 &spr_read_generic, &spr_write_generic,
4291
                 0x00000000);
4292
    /* XXX : not implemented */
4293
    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4294
                 SPR_NOACCESS, SPR_NOACCESS,
4295
                 &spr_read_generic, &spr_write_generic,
4296
                 0x00000000);
4297
    /* XXX : not implemented */
4298
    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4299
                 SPR_NOACCESS, SPR_NOACCESS,
4300
                 &spr_read_generic, &spr_write_generic,
4301
                 0x00000000);
4302
    /* XXX : not implemented */
4303
    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4304
                 SPR_NOACCESS, SPR_NOACCESS,
4305
                 &spr_read_generic, &spr_write_generic,
4306
                 0x00000000);
4307
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4308
                 SPR_NOACCESS, SPR_NOACCESS,
4309
                 &spr_read_generic, &spr_write_generic,
4310
                 0x00000000);
4311
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4312
                 SPR_NOACCESS, SPR_NOACCESS,
4313
                 &spr_read_generic, &spr_write_generic,
4314
                 0x00000000);
4315
#if !defined(CONFIG_USER_ONLY)
4316
    env->nb_tlb = 64;
4317
    env->nb_ways = 1;
4318
    env->id_tlbs = 0;
4319
#endif
4320
    init_excp_e200(env);
4321
    env->dcache_line_size = 32;
4322
    env->icache_line_size = 32;
4323
    /* Allocate hardware IRQ controller */
4324
    ppce500_irq_init(env);
4325
}
4326

    
4327
/* Non-embedded PowerPC                                                      */
4328

    
4329
/* POWER : same as 601, without mfmsr, mfsr                                  */
4330
#if defined(TODO)
4331
#define POWERPC_INSNS_POWER  (XXX_TODO)
4332
/* POWER RSC (from RAD6000) */
4333
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4334
#endif /* TODO */
4335

    
4336
/* PowerPC 601                                                               */
4337
#define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4338
                              PPC_FLOAT |                                     \
4339
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4340
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4341
                              PPC_SEGMENT | PPC_EXTERN)
4342
#define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4343
#define POWERPC_MSRR_601     (0x0000000000001040ULL)
4344
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
4345
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4346
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4347
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4348
#define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4349
#define check_pow_601        check_pow_none
4350

    
4351
static void init_proc_601 (CPUPPCState *env)
4352
{
4353
    gen_spr_ne_601(env);
4354
    gen_spr_601(env);
4355
    /* Hardware implementation registers */
4356
    /* XXX : not implemented */
4357
    spr_register(env, SPR_HID0, "HID0",
4358
                 SPR_NOACCESS, SPR_NOACCESS,
4359
                 &spr_read_generic, &spr_write_hid0_601,
4360
                 0x80010080);
4361
    /* XXX : not implemented */
4362
    spr_register(env, SPR_HID1, "HID1",
4363
                 SPR_NOACCESS, SPR_NOACCESS,
4364
                 &spr_read_generic, &spr_write_generic,
4365
                 0x00000000);
4366
    /* XXX : not implemented */
4367
    spr_register(env, SPR_601_HID2, "HID2",
4368
                 SPR_NOACCESS, SPR_NOACCESS,
4369
                 &spr_read_generic, &spr_write_generic,
4370
                 0x00000000);
4371
    /* XXX : not implemented */
4372
    spr_register(env, SPR_601_HID5, "HID5",
4373
                 SPR_NOACCESS, SPR_NOACCESS,
4374
                 &spr_read_generic, &spr_write_generic,
4375
                 0x00000000);
4376
    /* Memory management */
4377
    init_excp_601(env);
4378
    /* XXX: beware that dcache line size is 64 
4379
     *      but dcbz uses 32 bytes "sectors"
4380
     * XXX: this breaks clcs instruction !
4381
     */
4382
    env->dcache_line_size = 32;
4383
    env->icache_line_size = 64;
4384
    /* Allocate hardware IRQ controller */
4385
    ppc6xx_irq_init(env);
4386
}
4387

    
4388
/* PowerPC 601v                                                              */
4389
#define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4390
                              PPC_FLOAT |                                     \
4391
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4392
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4393
                              PPC_SEGMENT | PPC_EXTERN)
4394
#define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4395
#define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4396
#define POWERPC_MMU_601v     (POWERPC_MMU_601)
4397
#define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4398
#define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4399
#define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4400
#define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4401
#define check_pow_601v       check_pow_none
4402

    
4403
static void init_proc_601v (CPUPPCState *env)
4404
{
4405
    init_proc_601(env);
4406
    /* XXX : not implemented */
4407
    spr_register(env, SPR_601_HID15, "HID15",
4408
                 SPR_NOACCESS, SPR_NOACCESS,
4409
                 &spr_read_generic, &spr_write_generic,
4410
                 0x00000000);
4411
}
4412

    
4413
/* PowerPC 602                                                               */
4414
#define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4415
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4416
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4417
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4418
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4419
                              PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4420
                              PPC_SEGMENT | PPC_602_SPEC)
4421
#define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4422
/* XXX: 602 MMU is quite specific. Should add a special case */
4423
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4424
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4425
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4426
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4427
#define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4428
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4429
#define check_pow_602        check_pow_hid0
4430

    
4431
static void init_proc_602 (CPUPPCState *env)
4432
{
4433
    gen_spr_ne_601(env);
4434
    gen_spr_602(env);
4435
    /* Time base */
4436
    gen_tbl(env);
4437
    /* hardware implementation registers */
4438
    /* XXX : not implemented */
4439
    spr_register(env, SPR_HID0, "HID0",
4440
                 SPR_NOACCESS, SPR_NOACCESS,
4441
                 &spr_read_generic, &spr_write_generic,
4442
                 0x00000000);
4443
    /* XXX : not implemented */
4444
    spr_register(env, SPR_HID1, "HID1",
4445
                 SPR_NOACCESS, SPR_NOACCESS,
4446
                 &spr_read_generic, &spr_write_generic,
4447
                 0x00000000);
4448
    /* Memory management */
4449
    gen_low_BATs(env);
4450
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4451
    init_excp_602(env);
4452
    env->dcache_line_size = 32;
4453
    env->icache_line_size = 32;
4454
    /* Allocate hardware IRQ controller */
4455
    ppc6xx_irq_init(env);
4456
}
4457

    
4458
/* PowerPC 603                                                               */
4459
#define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4460
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4461
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4462
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4463
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4464
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4465
                              PPC_SEGMENT | PPC_EXTERN)
4466
#define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4467
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4468
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4469
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4470
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4471
#define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4472
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4473
#define check_pow_603        check_pow_hid0
4474

    
4475
static void init_proc_603 (CPUPPCState *env)
4476
{
4477
    gen_spr_ne_601(env);
4478
    gen_spr_603(env);
4479
    /* Time base */
4480
    gen_tbl(env);
4481
    /* hardware implementation registers */
4482
    /* XXX : not implemented */
4483
    spr_register(env, SPR_HID0, "HID0",
4484
                 SPR_NOACCESS, SPR_NOACCESS,
4485
                 &spr_read_generic, &spr_write_generic,
4486
                 0x00000000);
4487
    /* XXX : not implemented */
4488
    spr_register(env, SPR_HID1, "HID1",
4489
                 SPR_NOACCESS, SPR_NOACCESS,
4490
                 &spr_read_generic, &spr_write_generic,
4491
                 0x00000000);
4492
    /* Memory management */
4493
    gen_low_BATs(env);
4494
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4495
    init_excp_603(env);
4496
    env->dcache_line_size = 32;
4497
    env->icache_line_size = 32;
4498
    /* Allocate hardware IRQ controller */
4499
    ppc6xx_irq_init(env);
4500
}
4501

    
4502
/* PowerPC 603e                                                              */
4503
#define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4504
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4505
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4506
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4507
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4508
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4509
                              PPC_SEGMENT | PPC_EXTERN)
4510
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4511
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4512
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4513
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4514
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4515
#define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4516
                              POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4517
#define check_pow_603E       check_pow_hid0
4518

    
4519
static void init_proc_603E (CPUPPCState *env)
4520
{
4521
    gen_spr_ne_601(env);
4522
    gen_spr_603(env);
4523
    /* Time base */
4524
    gen_tbl(env);
4525
    /* hardware implementation registers */
4526
    /* XXX : not implemented */
4527
    spr_register(env, SPR_HID0, "HID0",
4528
                 SPR_NOACCESS, SPR_NOACCESS,
4529
                 &spr_read_generic, &spr_write_generic,
4530
                 0x00000000);
4531
    /* XXX : not implemented */
4532
    spr_register(env, SPR_HID1, "HID1",
4533
                 SPR_NOACCESS, SPR_NOACCESS,
4534
                 &spr_read_generic, &spr_write_generic,
4535
                 0x00000000);
4536
    /* XXX : not implemented */
4537
    spr_register(env, SPR_IABR, "IABR",
4538
                 SPR_NOACCESS, SPR_NOACCESS,
4539
                 &spr_read_generic, &spr_write_generic,
4540
                 0x00000000);
4541
    /* Memory management */
4542
    gen_low_BATs(env);
4543
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4544
    init_excp_603(env);
4545
    env->dcache_line_size = 32;
4546
    env->icache_line_size = 32;
4547
    /* Allocate hardware IRQ controller */
4548
    ppc6xx_irq_init(env);
4549
}
4550

    
4551
/* PowerPC 604                                                               */
4552
#define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4553
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4554
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4555
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4556
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4557
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4558
                              PPC_SEGMENT | PPC_EXTERN)
4559
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4560
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
4561
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4562
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4563
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4564
#define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4565
                              POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4566
#define check_pow_604        check_pow_nocheck
4567

    
4568
static void init_proc_604 (CPUPPCState *env)
4569
{
4570
    gen_spr_ne_601(env);
4571
    gen_spr_604(env);
4572
    /* Time base */
4573
    gen_tbl(env);
4574
    /* Hardware implementation registers */
4575
    /* XXX : not implemented */
4576
    spr_register(env, SPR_HID0, "HID0",
4577
                 SPR_NOACCESS, SPR_NOACCESS,
4578
                 &spr_read_generic, &spr_write_generic,
4579
                 0x00000000);
4580
    /* Memory management */
4581
    gen_low_BATs(env);
4582
    init_excp_604(env);
4583
    env->dcache_line_size = 32;
4584
    env->icache_line_size = 32;
4585
    /* Allocate hardware IRQ controller */
4586
    ppc6xx_irq_init(env);
4587
}
4588

    
4589
/* PowerPC 604E                                                              */
4590
#define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4591
                              PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4592
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4593
                              PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4594
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4595
                              PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4596
                              PPC_SEGMENT | PPC_EXTERN)
4597
#define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4598
#define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4599
#define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4600
#define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4601
#define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4602
#define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4603
                              POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4604
#define check_pow_604E       check_pow_nocheck
4605

    
4606
static void init_proc_604E (CPUPPCState *env)
4607
{
4608
    gen_spr_ne_601(env);
4609
    gen_spr_604(env);
4610
    /* XXX : not implemented */
4611
    spr_register(env, SPR_MMCR1, "MMCR1",
4612
                 SPR_NOACCESS, SPR_NOACCESS,
4613
                 &spr_read_generic, &spr_write_generic,
4614
                 0x00000000);
4615
    /* XXX : not implemented */
4616
    spr_register(env, SPR_PMC3, "PMC3",
4617
                 SPR_NOACCESS, SPR_NOACCESS,
4618
                 &spr_read_generic, &spr_write_generic,
4619
                 0x00000000);
4620
    /* XXX : not implemented */
4621
    spr_register(env, SPR_PMC4, "PMC4",
4622
                 SPR_NOACCESS, SPR_NOACCESS,
4623
                 &spr_read_generic, &spr_write_generic,
4624
                 0x00000000);
4625
    /* Time base */
4626
    gen_tbl(env);
4627
    /* Hardware implementation registers */
4628
    /* XXX : not implemented */
4629
    spr_register(env, SPR_HID0, "HID0",
4630
                 SPR_NOACCESS, SPR_NOACCESS,
4631
                 &spr_read_generic, &spr_write_generic,
4632
                 0x00000000);
4633
    /* XXX : not implemented */
4634
    spr_register(env, SPR_HID1, "HID1",
4635
                 SPR_NOACCESS, SPR_NOACCESS,
4636
                 &spr_read_generic, &spr_write_generic,
4637
                 0x00000000);
4638
    /* Memory management */
4639
    gen_low_BATs(env);
4640
    init_excp_604(e