Revision 952760bb
b/Makefile.objs | ||
---|---|---|
129 | 129 |
hw-obj-y = |
130 | 130 |
hw-obj-y += loader.o |
131 | 131 |
hw-obj-y += virtio.o virtio-console.o |
132 |
hw-obj-y += fw_cfg.o pci.o pcie_host.o |
|
132 |
hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o
|
|
133 | 133 |
hw-obj-y += watchdog.o |
134 | 134 |
hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o |
135 | 135 |
hw-obj-$(CONFIG_ECC) += ecc.o |
b/Makefile.target | ||
---|---|---|
161 | 161 |
# System emulator target |
162 | 162 |
ifdef CONFIG_SOFTMMU |
163 | 163 |
|
164 |
obj-y = vl.o monitor.o pci_host.o machine.o gdbstub.o
|
|
164 |
obj-y = vl.o monitor.o machine.o gdbstub.o |
|
165 | 165 |
obj-y += qemu-timer.o |
166 | 166 |
# virtio has to be here due to weird dependency between PCI and virtio-net. |
167 | 167 |
# need to fix this properly |
b/hw/dec_pci.c | ||
---|---|---|
69 | 69 |
|
70 | 70 |
s = FROM_SYSBUS(DECState, dev); |
71 | 71 |
|
72 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state); |
|
73 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
|
72 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
|
|
73 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
|
|
74 | 74 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
75 | 75 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
76 | 76 |
return 0; |
b/hw/grackle_pci.c | ||
---|---|---|
108 | 108 |
|
109 | 109 |
s = FROM_SYSBUS(GrackleState, dev); |
110 | 110 |
|
111 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state); |
|
112 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
|
111 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
|
|
112 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
|
|
113 | 113 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
114 | 114 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
115 | 115 |
|
b/hw/pci_host.c | ||
---|---|---|
78 | 78 |
return val; |
79 | 79 |
} |
80 | 80 |
|
81 |
static void pci_host_config_write(ReadWriteHandler *handler, |
|
82 |
pcibus_t addr, uint32_t val, int len) |
|
81 |
static void pci_host_config_write_swap(ReadWriteHandler *handler,
|
|
82 |
pcibus_t addr, uint32_t val, int len)
|
|
83 | 83 |
{ |
84 | 84 |
PCIHostState *s = container_of(handler, PCIHostState, conf_handler); |
85 | 85 |
|
86 | 86 |
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n", |
87 | 87 |
__func__, addr, len, val); |
88 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
89 | 88 |
val = qemu_bswap_len(val, len); |
90 |
#endif |
|
91 | 89 |
s->config_reg = val; |
92 | 90 |
} |
93 | 91 |
|
94 |
static uint32_t pci_host_config_read(ReadWriteHandler *handler, |
|
95 |
pcibus_t addr, int len)
|
|
92 |
static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
|
|
93 |
pcibus_t addr, int len) |
|
96 | 94 |
{ |
97 | 95 |
PCIHostState *s = container_of(handler, PCIHostState, conf_handler); |
98 | 96 |
uint32_t val = s->config_reg; |
99 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
97 |
|
|
100 | 98 |
val = qemu_bswap_len(val, len); |
101 |
#endif |
|
102 | 99 |
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n", |
103 | 100 |
__func__, addr, len, val); |
104 | 101 |
return val; |
... | ... | |
125 | 122 |
return val; |
126 | 123 |
} |
127 | 124 |
|
128 |
static void pci_host_data_write(ReadWriteHandler *handler, |
|
129 |
pcibus_t addr, uint32_t val, int len) |
|
125 |
static void pci_host_data_write_swap(ReadWriteHandler *handler,
|
|
126 |
pcibus_t addr, uint32_t val, int len)
|
|
130 | 127 |
{ |
131 | 128 |
PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
132 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
129 |
|
|
133 | 130 |
val = qemu_bswap_len(val, len); |
134 |
#endif |
|
135 | 131 |
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", |
136 | 132 |
addr, len, val); |
137 | 133 |
if (s->config_reg & (1u << 31)) |
138 | 134 |
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); |
139 | 135 |
} |
140 | 136 |
|
141 |
static uint32_t pci_host_data_read(ReadWriteHandler *handler, |
|
142 |
pcibus_t addr, int len) |
|
137 |
static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
|
|
138 |
pcibus_t addr, int len)
|
|
143 | 139 |
{ |
144 | 140 |
PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
145 | 141 |
uint32_t val; |
... | ... | |
148 | 144 |
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); |
149 | 145 |
PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", |
150 | 146 |
addr, len, val); |
151 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
152 | 147 |
val = qemu_bswap_len(val, len); |
153 |
#endif |
|
154 | 148 |
return val; |
155 | 149 |
} |
156 | 150 |
|
157 |
static void pci_host_init(PCIHostState *s) |
|
151 |
static void pci_host_data_write_noswap(ReadWriteHandler *handler, |
|
152 |
pcibus_t addr, uint32_t val, int len) |
|
158 | 153 |
{ |
159 |
s->conf_handler.write = pci_host_config_write; |
|
160 |
s->conf_handler.read = pci_host_config_read; |
|
161 |
s->conf_noswap_handler.write = pci_host_config_write_noswap; |
|
162 |
s->conf_noswap_handler.read = pci_host_config_read_noswap; |
|
163 |
s->data_handler.write = pci_host_data_write; |
|
164 |
s->data_handler.read = pci_host_data_read; |
|
154 |
PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
|
155 |
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", |
|
156 |
addr, len, val); |
|
157 |
if (s->config_reg & (1u << 31)) |
|
158 |
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); |
|
165 | 159 |
} |
166 | 160 |
|
167 |
int pci_host_conf_register_mmio(PCIHostState *s) |
|
161 |
static uint32_t pci_host_data_read_noswap(ReadWriteHandler *handler, |
|
162 |
pcibus_t addr, int len) |
|
168 | 163 |
{ |
169 |
pci_host_init(s); |
|
170 |
return cpu_register_io_memory_simple(&s->conf_handler); |
|
164 |
PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
|
165 |
uint32_t val; |
|
166 |
if (!(s->config_reg & (1 << 31))) |
|
167 |
return 0xffffffff; |
|
168 |
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); |
|
169 |
PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", |
|
170 |
addr, len, val); |
|
171 |
return val; |
|
171 | 172 |
} |
172 | 173 |
|
173 |
int pci_host_conf_register_mmio_noswap(PCIHostState *s) |
|
174 |
static void pci_host_init(PCIHostState *s) |
|
175 |
{ |
|
176 |
s->conf_handler.write = pci_host_config_write_swap; |
|
177 |
s->conf_handler.read = pci_host_config_read_swap; |
|
178 |
s->conf_noswap_handler.write = pci_host_config_write_noswap; |
|
179 |
s->conf_noswap_handler.read = pci_host_config_read_noswap; |
|
180 |
s->data_handler.write = pci_host_data_write_swap; |
|
181 |
s->data_handler.read = pci_host_data_read_swap; |
|
182 |
s->data_noswap_handler.write = pci_host_data_write_noswap; |
|
183 |
s->data_noswap_handler.read = pci_host_data_read_noswap; |
|
184 |
} |
|
185 |
|
|
186 |
int pci_host_conf_register_mmio(PCIHostState *s, int swap) |
|
174 | 187 |
{ |
175 | 188 |
pci_host_init(s); |
176 |
return cpu_register_io_memory_simple(&s->conf_noswap_handler); |
|
189 |
if (swap) { |
|
190 |
return cpu_register_io_memory_simple(&s->conf_handler); |
|
191 |
} else { |
|
192 |
return cpu_register_io_memory_simple(&s->conf_noswap_handler); |
|
193 |
} |
|
177 | 194 |
} |
178 | 195 |
|
179 | 196 |
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s) |
... | ... | |
182 | 199 |
register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4); |
183 | 200 |
} |
184 | 201 |
|
185 |
int pci_host_data_register_mmio(PCIHostState *s) |
|
202 |
int pci_host_data_register_mmio(PCIHostState *s, int swap)
|
|
186 | 203 |
{ |
187 | 204 |
pci_host_init(s); |
188 |
return cpu_register_io_memory_simple(&s->data_handler); |
|
205 |
if (swap) { |
|
206 |
return cpu_register_io_memory_simple(&s->data_handler); |
|
207 |
} else { |
|
208 |
return cpu_register_io_memory_simple(&s->data_noswap_handler); |
|
209 |
} |
|
189 | 210 |
} |
190 | 211 |
|
191 | 212 |
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s) |
b/hw/pci_host.h | ||
---|---|---|
35 | 35 |
SysBusDevice busdev; |
36 | 36 |
ReadWriteHandler conf_noswap_handler; |
37 | 37 |
ReadWriteHandler conf_handler; |
38 |
ReadWriteHandler data_noswap_handler; |
|
38 | 39 |
ReadWriteHandler data_handler; |
39 | 40 |
uint32_t config_reg; |
40 | 41 |
PCIBus *bus; |
... | ... | |
44 | 45 |
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); |
45 | 46 |
|
46 | 47 |
/* for mmio */ |
47 |
int pci_host_conf_register_mmio(PCIHostState *s); |
|
48 |
int pci_host_conf_register_mmio_noswap(PCIHostState *s); |
|
49 |
int pci_host_data_register_mmio(PCIHostState *s); |
|
48 |
int pci_host_conf_register_mmio(PCIHostState *s, int swap); |
|
49 |
int pci_host_data_register_mmio(PCIHostState *s, int swap); |
|
50 | 50 |
|
51 | 51 |
/* for ioio */ |
52 | 52 |
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s); |
b/hw/ppc4xx_pci.c | ||
---|---|---|
378 | 378 |
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); |
379 | 379 |
|
380 | 380 |
/* CFGDATA */ |
381 |
index = pci_host_data_register_mmio(&controller->pci_state); |
|
381 |
index = pci_host_data_register_mmio(&controller->pci_state, 1);
|
|
382 | 382 |
if (index < 0) |
383 | 383 |
goto free; |
384 | 384 |
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index); |
b/hw/ppce500_pci.c | ||
---|---|---|
293 | 293 |
controller->pci_dev = d; |
294 | 294 |
|
295 | 295 |
/* CFGADDR */ |
296 |
index = pci_host_conf_register_mmio_noswap(&controller->pci_state);
|
|
296 |
index = pci_host_conf_register_mmio(&controller->pci_state, 0);
|
|
297 | 297 |
if (index < 0) |
298 | 298 |
goto free; |
299 | 299 |
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index); |
300 | 300 |
|
301 | 301 |
/* CFGDATA */ |
302 |
index = pci_host_data_register_mmio(&controller->pci_state); |
|
302 |
index = pci_host_data_register_mmio(&controller->pci_state, 0);
|
|
303 | 303 |
if (index < 0) |
304 | 304 |
goto free; |
305 | 305 |
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index); |
b/hw/unin_pci.c | ||
---|---|---|
155 | 155 |
/* Uninorth main bus */ |
156 | 156 |
s = FROM_SYSBUS(UNINState, dev); |
157 | 157 |
|
158 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state); |
|
158 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
|
|
159 | 159 |
s->data_handler.read = unin_data_read; |
160 | 160 |
s->data_handler.write = unin_data_write; |
161 | 161 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); |
... | ... | |
175 | 175 |
/* Uninorth U3 AGP bus */ |
176 | 176 |
s = FROM_SYSBUS(UNINState, dev); |
177 | 177 |
|
178 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state); |
|
178 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
|
|
179 | 179 |
s->data_handler.read = unin_data_read; |
180 | 180 |
s->data_handler.write = unin_data_write; |
181 | 181 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); |
... | ... | |
196 | 196 |
/* Uninorth AGP bus */ |
197 | 197 |
s = FROM_SYSBUS(UNINState, dev); |
198 | 198 |
|
199 |
pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
|
|
200 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
|
199 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
|
|
200 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
|
|
201 | 201 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
202 | 202 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
203 | 203 |
return 0; |
... | ... | |
211 | 211 |
/* Uninorth internal bus */ |
212 | 212 |
s = FROM_SYSBUS(UNINState, dev); |
213 | 213 |
|
214 |
pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
|
|
215 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
|
214 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
|
|
215 |
pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
|
|
216 | 216 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
217 | 217 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
218 | 218 |
return 0; |
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