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/*
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 * PXA270-based Intel Mainstone platforms.
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 *
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 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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 *                                    <akuster@mvista.com>
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 *
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 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
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 *
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 * This code is licensed under the GNU GPL v2.
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 */
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#include "hw.h"
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#include "pxa.h"
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#include "arm-misc.h"
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#include "net.h"
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#include "devices.h"
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#include "boards.h"
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#include "sysemu.h"
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#include "flash.h"
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#include "blockdev.h"
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#include "sysbus.h"
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/* Device addresses */
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#define MST_FPGA_PHYS        0x08000000
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#define MST_ETH_PHYS        0x10000300
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#define MST_FLASH_0                0x00000000
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#define MST_FLASH_1                0x04000000
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/* IRQ definitions */
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#define MMC_IRQ       0
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#define USIM_IRQ      1
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#define USBC_IRQ      2
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#define ETHERNET_IRQ  3
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#define AC97_IRQ      4
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#define PEN_IRQ       5
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#define MSINS_IRQ     6
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#define EXBRD_IRQ     7
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#define S0_CD_IRQ     9
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#define S0_STSCHG_IRQ 10
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#define S0_IRQ        11
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#define S1_CD_IRQ     13
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#define S1_STSCHG_IRQ 14
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#define S1_IRQ        15
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static struct keymap map[0xE0] = {
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    [0 ... 0xDF] = { -1, -1 },
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    [0x1e] = {0,0}, /* a */
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    [0x30] = {0,1}, /* b */
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    [0x2e] = {0,2}, /* c */
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    [0x20] = {0,3}, /* d */
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    [0x12] = {0,4}, /* e */
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    [0x21] = {0,5}, /* f */
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    [0x22] = {1,0}, /* g */
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    [0x23] = {1,1}, /* h */
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    [0x17] = {1,2}, /* i */
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    [0x24] = {1,3}, /* j */
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    [0x25] = {1,4}, /* k */
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    [0x26] = {1,5}, /* l */
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    [0x32] = {2,0}, /* m */
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    [0x31] = {2,1}, /* n */
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    [0x18] = {2,2}, /* o */
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    [0x19] = {2,3}, /* p */
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    [0x10] = {2,4}, /* q */
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    [0x13] = {2,5}, /* r */
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    [0x1f] = {3,0}, /* s */
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    [0x14] = {3,1}, /* t */
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    [0x16] = {3,2}, /* u */
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    [0x2f] = {3,3}, /* v */
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    [0x11] = {3,4}, /* w */
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    [0x2d] = {3,5}, /* x */
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    [0x15] = {4,2}, /* y */
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    [0x2c] = {4,3}, /* z */
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    [0xc7] = {5,0}, /* Home */
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    [0x2a] = {5,1}, /* shift */
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    [0x39] = {5,2}, /* space */
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    [0x39] = {5,3}, /* space */
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    [0x1c] = {5,5}, /*  enter */
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    [0xc8] = {6,0}, /* up */
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    [0xd0] = {6,1}, /* down */
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    [0xcb] = {6,2}, /* left */
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    [0xcd] = {6,3}, /* right */
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};
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enum mainstone_model_e { mainstone };
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#define MAINSTONE_RAM        0x04000000
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#define MAINSTONE_ROM        0x00800000
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#define MAINSTONE_FLASH        0x02000000
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static struct arm_boot_info mainstone_binfo = {
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    .loader_start = PXA2XX_SDRAM_BASE,
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    .ram_size = 0x04000000,
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};
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static void mainstone_common_init(ram_addr_t ram_size,
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                const char *kernel_filename,
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                const char *kernel_cmdline, const char *initrd_filename,
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                const char *cpu_model, enum mainstone_model_e model, int arm_id)
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{
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    uint32_t sector_len = 256 * 1024;
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    target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
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    PXA2xxState *cpu;
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    DeviceState *mst_irq;
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    DriveInfo *dinfo;
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    int i;
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    int be;
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    if (!cpu_model)
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        cpu_model = "pxa270-c5";
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    /* Setup CPU & memory */
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    cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
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    cpu_register_physical_memory(0, MAINSTONE_ROM,
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                    qemu_ram_alloc(NULL, "mainstone.rom",
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                                   MAINSTONE_ROM) | IO_MEM_ROM);
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#ifdef TARGET_WORDS_BIGENDIAN
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    be = 1;
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#else
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    be = 0;
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#endif
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    /* There are two 32MiB flash devices on the board */
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    for (i = 0; i < 2; i ++) {
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        dinfo = drive_get(IF_PFLASH, 0, i);
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        if (!dinfo) {
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            fprintf(stderr, "Two flash images must be given with the "
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                    "'pflash' parameter\n");
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            exit(1);
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        }
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        if (!pflash_cfi01_register(mainstone_flash_base[i],
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                                   qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
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                                                  "mainstone.flash0",
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                                                  MAINSTONE_FLASH),
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                                   dinfo->bdrv, sector_len,
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                                   MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
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                                   be)) {
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            fprintf(stderr, "qemu: Error registering flash memory.\n");
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            exit(1);
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        }
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    }
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    mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
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                    qdev_get_gpio_in(cpu->gpio, 0));
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    /* setup keypad */
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    printf("map addr %p\n", &map);
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    pxa27x_register_keypad(cpu->kp, map, 0xe0);
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    /* MMC/SD host */
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    pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
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    smc91c111_init(&nd_table[0], MST_ETH_PHYS,
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                    qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
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    mainstone_binfo.kernel_filename = kernel_filename;
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    mainstone_binfo.kernel_cmdline = kernel_cmdline;
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    mainstone_binfo.initrd_filename = initrd_filename;
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    mainstone_binfo.board_id = arm_id;
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    arm_load_kernel(cpu->env, &mainstone_binfo);
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}
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static void mainstone_init(ram_addr_t ram_size,
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                const char *boot_device,
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                const char *kernel_filename, const char *kernel_cmdline,
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                const char *initrd_filename, const char *cpu_model)
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{
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    mainstone_common_init(ram_size, kernel_filename,
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                kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
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}
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static QEMUMachine mainstone2_machine = {
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    .name = "mainstone",
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    .desc = "Mainstone II (PXA27x)",
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    .init = mainstone_init,
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};
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static void mainstone_machine_init(void)
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{
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    qemu_register_machine(&mainstone2_machine);
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}
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machine_init(mainstone_machine_init);