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1
/*
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   SPARC translation
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4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
33

    
34
#define DEBUG_DISAS
35

    
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#define DYNAMIC_PC  1 /* dynamic pc value */
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#define JUMP_PC     2 /* dynamic pc value which takes only two values
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                         according to jump_pc[T2] */
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/* global register indexes */
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static TCGv cpu_env, cpu_regwptr;
42
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv cpu_xcc;
47
#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50

    
51
#include "gen-icount.h"
52

    
53
typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    int fpu_enabled;
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    int address_mask_32bit;
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    struct TranslationBlock *tb;
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    uint32_t features;
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} DisasContext;
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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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    GET_FIELD(X, 31 - (TO), 31 - (FROM))
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73
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
81
#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
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#define QFPREG(r) (r & 0x1c)
84
#endif
85

    
86
static int sign_extend(int x, int len)
87
{
88
    len = 32 - len;
89
    return (x << len) >> len;
90
}
91

    
92
#define IS_IMM (insn & (1<<13))
93

    
94
/* floating point registers moves */
95
static void gen_op_load_fpr_FT0(unsigned int src)
96
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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}
100

    
101
static void gen_op_load_fpr_FT1(unsigned int src)
102
{
103
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
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}
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107
static void gen_op_store_FT0_fpr(unsigned int dst)
108
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
114
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
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}
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123
static void gen_op_load_fpr_DT1(unsigned int src)
124
{
125
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.lower));
131
}
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133
static void gen_op_store_DT0_fpr(unsigned int dst)
134
{
135
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141
}
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143
static void gen_op_load_fpr_QT0(unsigned int src)
144
{
145
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150
                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153
                   offsetof(CPU_QuadU, l.lower));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
156
                   offsetof(CPU_QuadU, l.lowest));
157
}
158

    
159
static void gen_op_load_fpr_QT1(unsigned int src)
160
{
161
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upmost));
164
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169
                   offsetof(CPU_QuadU, l.lower));
170
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
172
                   offsetof(CPU_QuadU, l.lowest));
173
}
174

    
175
static void gen_op_store_QT0_fpr(unsigned int dst)
176
{
177
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178
                   offsetof(CPU_QuadU, l.upmost));
179
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181
                   offsetof(CPU_QuadU, l.upper));
182
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184
                   offsetof(CPU_QuadU, l.lower));
185
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187
                   offsetof(CPU_QuadU, l.lowest));
188
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
189
}
190

    
191
/* moves */
192
#ifdef CONFIG_USER_ONLY
193
#define supervisor(dc) 0
194
#ifdef TARGET_SPARC64
195
#define hypervisor(dc) 0
196
#endif
197
#else
198
#define supervisor(dc) (dc->mem_idx >= 1)
199
#ifdef TARGET_SPARC64
200
#define hypervisor(dc) (dc->mem_idx == 2)
201
#else
202
#endif
203
#endif
204

    
205
#ifdef TARGET_SPARC64
206
#ifndef TARGET_ABI32
207
#define AM_CHECK(dc) ((dc)->address_mask_32bit)
208
#else
209
#define AM_CHECK(dc) (1)
210
#endif
211
#endif
212

    
213
static inline void gen_address_mask(DisasContext *dc, TCGv addr)
214
{
215
#ifdef TARGET_SPARC64
216
    if (AM_CHECK(dc))
217
        tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218
#endif
219
}
220

    
221
static inline void gen_movl_reg_TN(int reg, TCGv tn)
222
{
223
    if (reg == 0)
224
        tcg_gen_movi_tl(tn, 0);
225
    else if (reg < 8)
226
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
227
    else {
228
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229
    }
230
}
231

    
232
static inline void gen_movl_TN_reg(int reg, TCGv tn)
233
{
234
    if (reg == 0)
235
        return;
236
    else if (reg < 8)
237
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
238
    else {
239
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
240
    }
241
}
242

    
243
static inline void gen_goto_tb(DisasContext *s, int tb_num,
244
                               target_ulong pc, target_ulong npc)
245
{
246
    TranslationBlock *tb;
247

    
248
    tb = s->tb;
249
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
251
        /* jump to same page: we can use a direct jump */
252
        tcg_gen_goto_tb(tb_num);
253
        tcg_gen_movi_tl(cpu_pc, pc);
254
        tcg_gen_movi_tl(cpu_npc, npc);
255
        tcg_gen_exit_tb((long)tb + tb_num);
256
    } else {
257
        /* jump to another page: currently not optimized */
258
        tcg_gen_movi_tl(cpu_pc, pc);
259
        tcg_gen_movi_tl(cpu_npc, npc);
260
        tcg_gen_exit_tb(0);
261
    }
262
}
263

    
264
// XXX suboptimal
265
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
266
{
267
    tcg_gen_extu_i32_tl(reg, src);
268
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269
    tcg_gen_andi_tl(reg, reg, 0x1);
270
}
271

    
272
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
273
{
274
    tcg_gen_extu_i32_tl(reg, src);
275
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276
    tcg_gen_andi_tl(reg, reg, 0x1);
277
}
278

    
279
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
280
{
281
    tcg_gen_extu_i32_tl(reg, src);
282
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283
    tcg_gen_andi_tl(reg, reg, 0x1);
284
}
285

    
286
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
287
{
288
    tcg_gen_extu_i32_tl(reg, src);
289
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290
    tcg_gen_andi_tl(reg, reg, 0x1);
291
}
292

    
293
static inline void gen_cc_clear_icc(void)
294
{
295
    tcg_gen_movi_i32(cpu_psr, 0);
296
}
297

    
298
#ifdef TARGET_SPARC64
299
static inline void gen_cc_clear_xcc(void)
300
{
301
    tcg_gen_movi_i32(cpu_xcc, 0);
302
}
303
#endif
304

    
305
/* old op:
306
    if (!T0)
307
        env->psr |= PSR_ZERO;
308
    if ((int32_t) T0 < 0)
309
        env->psr |= PSR_NEG;
310
*/
311
static inline void gen_cc_NZ_icc(TCGv dst)
312
{
313
    TCGv r_temp;
314
    int l1, l2;
315

    
316
    l1 = gen_new_label();
317
    l2 = gen_new_label();
318
    r_temp = tcg_temp_new(TCG_TYPE_TL);
319
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
322
    gen_set_label(l1);
323
    tcg_gen_ext_i32_tl(r_temp, dst);
324
    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
326
    gen_set_label(l2);
327
    tcg_temp_free(r_temp);
328
}
329

    
330
#ifdef TARGET_SPARC64
331
static inline void gen_cc_NZ_xcc(TCGv dst)
332
{
333
    int l1, l2;
334

    
335
    l1 = gen_new_label();
336
    l2 = gen_new_label();
337
    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339
    gen_set_label(l1);
340
    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342
    gen_set_label(l2);
343
}
344
#endif
345

    
346
/* old op:
347
    if (T0 < src1)
348
        env->psr |= PSR_CARRY;
349
*/
350
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351
{
352
    TCGv r_temp;
353
    int l1;
354

    
355
    l1 = gen_new_label();
356
    r_temp = tcg_temp_new(TCG_TYPE_TL);
357
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
358
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
359
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
360
    gen_set_label(l1);
361
    tcg_temp_free(r_temp);
362
}
363

    
364
#ifdef TARGET_SPARC64
365
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
366
{
367
    int l1;
368

    
369
    l1 = gen_new_label();
370
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
371
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
372
    gen_set_label(l1);
373
}
374
#endif
375

    
376
/* old op:
377
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
378
        env->psr |= PSR_OVF;
379
*/
380
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
381
{
382
    TCGv r_temp;
383

    
384
    r_temp = tcg_temp_new(TCG_TYPE_TL);
385
    tcg_gen_xor_tl(r_temp, src1, src2);
386
    tcg_gen_xori_tl(r_temp, r_temp, -1);
387
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
388
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
389
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
390
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
391
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
392
    tcg_temp_free(r_temp);
393
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
394
}
395

    
396
#ifdef TARGET_SPARC64
397
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
398
{
399
    TCGv r_temp;
400

    
401
    r_temp = tcg_temp_new(TCG_TYPE_TL);
402
    tcg_gen_xor_tl(r_temp, src1, src2);
403
    tcg_gen_xori_tl(r_temp, r_temp, -1);
404
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
405
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
406
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
407
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
408
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
409
    tcg_temp_free(r_temp);
410
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
411
}
412
#endif
413

    
414
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
415
{
416
    TCGv r_temp, r_const;
417
    int l1;
418

    
419
    l1 = gen_new_label();
420

    
421
    r_temp = tcg_temp_new(TCG_TYPE_TL);
422
    tcg_gen_xor_tl(r_temp, src1, src2);
423
    tcg_gen_xori_tl(r_temp, r_temp, -1);
424
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
425
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
426
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
427
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
428
    r_const = tcg_const_i32(TT_TOVF);
429
    tcg_gen_helper_0_1(raise_exception, r_const);
430
    tcg_temp_free(r_const);
431
    gen_set_label(l1);
432
    tcg_temp_free(r_temp);
433
}
434

    
435
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
436
{
437
    int l1;
438

    
439
    l1 = gen_new_label();
440
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
441
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
444
    gen_set_label(l1);
445
}
446

    
447
static inline void gen_tag_tv(TCGv src1, TCGv src2)
448
{
449
    int l1;
450
    TCGv r_const;
451

    
452
    l1 = gen_new_label();
453
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
454
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
455
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
456
    r_const = tcg_const_i32(TT_TOVF);
457
    tcg_gen_helper_0_1(raise_exception, r_const);
458
    tcg_temp_free(r_const);
459
    gen_set_label(l1);
460
}
461

    
462
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
463
{
464
    tcg_gen_mov_tl(cpu_cc_src, src1);
465
    tcg_gen_mov_tl(cpu_cc_src2, src2);
466
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
467
    gen_cc_clear_icc();
468
    gen_cc_NZ_icc(cpu_cc_dst);
469
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
470
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
471
#ifdef TARGET_SPARC64
472
    gen_cc_clear_xcc();
473
    gen_cc_NZ_xcc(cpu_cc_dst);
474
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
475
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
476
#endif
477
    tcg_gen_mov_tl(dst, cpu_cc_dst);
478
}
479

    
480
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
481
{
482
    tcg_gen_mov_tl(cpu_cc_src, src1);
483
    tcg_gen_mov_tl(cpu_cc_src2, src2);
484
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
485
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
486
    gen_cc_clear_icc();
487
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
488
#ifdef TARGET_SPARC64
489
    gen_cc_clear_xcc();
490
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
491
#endif
492
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
493
    gen_cc_NZ_icc(cpu_cc_dst);
494
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
495
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
496
#ifdef TARGET_SPARC64
497
    gen_cc_NZ_xcc(cpu_cc_dst);
498
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
499
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
500
#endif
501
    tcg_gen_mov_tl(dst, cpu_cc_dst);
502
}
503

    
504
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
505
{
506
    tcg_gen_mov_tl(cpu_cc_src, src1);
507
    tcg_gen_mov_tl(cpu_cc_src2, src2);
508
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
509
    gen_cc_clear_icc();
510
    gen_cc_NZ_icc(cpu_cc_dst);
511
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
512
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
513
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
514
#ifdef TARGET_SPARC64
515
    gen_cc_clear_xcc();
516
    gen_cc_NZ_xcc(cpu_cc_dst);
517
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
518
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
519
#endif
520
    tcg_gen_mov_tl(dst, cpu_cc_dst);
521
}
522

    
523
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
524
{
525
    tcg_gen_mov_tl(cpu_cc_src, src1);
526
    tcg_gen_mov_tl(cpu_cc_src2, src2);
527
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
528
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
529
    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
530
    gen_cc_clear_icc();
531
    gen_cc_NZ_icc(cpu_cc_dst);
532
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
533
#ifdef TARGET_SPARC64
534
    gen_cc_clear_xcc();
535
    gen_cc_NZ_xcc(cpu_cc_dst);
536
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
537
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
538
#endif
539
    tcg_gen_mov_tl(dst, cpu_cc_dst);
540
}
541

    
542
/* old op:
543
    if (src1 < T1)
544
        env->psr |= PSR_CARRY;
545
*/
546
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
547
{
548
    TCGv r_temp1, r_temp2;
549
    int l1;
550

    
551
    l1 = gen_new_label();
552
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
553
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
554
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
555
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
556
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
557
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
558
    gen_set_label(l1);
559
    tcg_temp_free(r_temp1);
560
    tcg_temp_free(r_temp2);
561
}
562

    
563
#ifdef TARGET_SPARC64
564
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
565
{
566
    int l1;
567

    
568
    l1 = gen_new_label();
569
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
570
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
571
    gen_set_label(l1);
572
}
573
#endif
574

    
575
/* old op:
576
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
577
        env->psr |= PSR_OVF;
578
*/
579
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
580
{
581
    TCGv r_temp;
582

    
583
    r_temp = tcg_temp_new(TCG_TYPE_TL);
584
    tcg_gen_xor_tl(r_temp, src1, src2);
585
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
586
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
587
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
588
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
589
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
590
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
591
    tcg_temp_free(r_temp);
592
}
593

    
594
#ifdef TARGET_SPARC64
595
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
596
{
597
    TCGv r_temp;
598

    
599
    r_temp = tcg_temp_new(TCG_TYPE_TL);
600
    tcg_gen_xor_tl(r_temp, src1, src2);
601
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
602
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
603
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
604
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
605
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
606
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
607
    tcg_temp_free(r_temp);
608
}
609
#endif
610

    
611
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
612
{
613
    TCGv r_temp, r_const;
614
    int l1;
615

    
616
    l1 = gen_new_label();
617

    
618
    r_temp = tcg_temp_new(TCG_TYPE_TL);
619
    tcg_gen_xor_tl(r_temp, src1, src2);
620
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
621
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
622
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
623
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
624
    r_const = tcg_const_i32(TT_TOVF);
625
    tcg_gen_helper_0_1(raise_exception, r_const);
626
    tcg_temp_free(r_const);
627
    gen_set_label(l1);
628
    tcg_temp_free(r_temp);
629
}
630

    
631
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
632
{
633
    tcg_gen_mov_tl(cpu_cc_src, src1);
634
    tcg_gen_mov_tl(cpu_cc_src2, src2);
635
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
636
    gen_cc_clear_icc();
637
    gen_cc_NZ_icc(cpu_cc_dst);
638
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
639
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
640
#ifdef TARGET_SPARC64
641
    gen_cc_clear_xcc();
642
    gen_cc_NZ_xcc(cpu_cc_dst);
643
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
644
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
645
#endif
646
    tcg_gen_mov_tl(dst, cpu_cc_dst);
647
}
648

    
649
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
650
{
651
    tcg_gen_mov_tl(cpu_cc_src, src1);
652
    tcg_gen_mov_tl(cpu_cc_src2, src2);
653
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
654
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
655
    gen_cc_clear_icc();
656
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
657
#ifdef TARGET_SPARC64
658
    gen_cc_clear_xcc();
659
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
660
#endif
661
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
662
    gen_cc_NZ_icc(cpu_cc_dst);
663
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
664
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
665
#ifdef TARGET_SPARC64
666
    gen_cc_NZ_xcc(cpu_cc_dst);
667
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
668
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
669
#endif
670
    tcg_gen_mov_tl(dst, cpu_cc_dst);
671
}
672

    
673
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
674
{
675
    tcg_gen_mov_tl(cpu_cc_src, src1);
676
    tcg_gen_mov_tl(cpu_cc_src2, src2);
677
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
678
    gen_cc_clear_icc();
679
    gen_cc_NZ_icc(cpu_cc_dst);
680
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
681
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
682
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
683
#ifdef TARGET_SPARC64
684
    gen_cc_clear_xcc();
685
    gen_cc_NZ_xcc(cpu_cc_dst);
686
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
687
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
688
#endif
689
    tcg_gen_mov_tl(dst, cpu_cc_dst);
690
}
691

    
692
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
693
{
694
    tcg_gen_mov_tl(cpu_cc_src, src1);
695
    tcg_gen_mov_tl(cpu_cc_src2, src2);
696
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
697
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
698
    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
699
    gen_cc_clear_icc();
700
    gen_cc_NZ_icc(cpu_cc_dst);
701
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
702
#ifdef TARGET_SPARC64
703
    gen_cc_clear_xcc();
704
    gen_cc_NZ_xcc(cpu_cc_dst);
705
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
706
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
707
#endif
708
    tcg_gen_mov_tl(dst, cpu_cc_dst);
709
}
710

    
711
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
712
{
713
    TCGv r_temp, r_temp2;
714
    int l1;
715

    
716
    l1 = gen_new_label();
717
    r_temp = tcg_temp_new(TCG_TYPE_TL);
718
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
719

    
720
    /* old op:
721
    if (!(env->y & 1))
722
        T1 = 0;
723
    */
724
    tcg_gen_mov_tl(cpu_cc_src, src1);
725
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
726
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
727
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
728
    tcg_gen_mov_tl(cpu_cc_src2, src2);
729
    tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
730
    tcg_gen_movi_tl(cpu_cc_src2, 0);
731
    gen_set_label(l1);
732

    
733
    // b2 = T0 & 1;
734
    // env->y = (b2 << 31) | (env->y >> 1);
735
    tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
736
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
737
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
738
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
739
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
740
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
741
    tcg_temp_free(r_temp2);
742
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
743

    
744
    // b1 = N ^ V;
745
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
746
    gen_mov_reg_V(r_temp, cpu_psr);
747
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
748
    tcg_temp_free(r_temp);
749

    
750
    // T0 = (b1 << 31) | (T0 >> 1);
751
    // src1 = T0;
752
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
753
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
754
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
755

    
756
    /* do addition and update flags */
757
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
758

    
759
    gen_cc_clear_icc();
760
    gen_cc_NZ_icc(cpu_cc_dst);
761
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
762
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
763
    tcg_gen_mov_tl(dst, cpu_cc_dst);
764
}
765

    
766
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
767
{
768
    TCGv r_temp, r_temp2;
769

    
770
    r_temp = tcg_temp_new(TCG_TYPE_I64);
771
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
772

    
773
    tcg_gen_extu_tl_i64(r_temp, src2);
774
    tcg_gen_extu_tl_i64(r_temp2, src1);
775
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
776

    
777
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
778
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
779
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
780
    tcg_temp_free(r_temp);
781
#ifdef TARGET_SPARC64
782
    tcg_gen_mov_i64(dst, r_temp2);
783
#else
784
    tcg_gen_trunc_i64_tl(dst, r_temp2);
785
#endif
786
    tcg_temp_free(r_temp2);
787
}
788

    
789
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
790
{
791
    TCGv r_temp, r_temp2;
792

    
793
    r_temp = tcg_temp_new(TCG_TYPE_I64);
794
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
795

    
796
    tcg_gen_ext_tl_i64(r_temp, src2);
797
    tcg_gen_ext_tl_i64(r_temp2, src1);
798
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
799

    
800
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
801
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
802
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
803
    tcg_temp_free(r_temp);
804
#ifdef TARGET_SPARC64
805
    tcg_gen_mov_i64(dst, r_temp2);
806
#else
807
    tcg_gen_trunc_i64_tl(dst, r_temp2);
808
#endif
809
    tcg_temp_free(r_temp2);
810
}
811

    
812
#ifdef TARGET_SPARC64
813
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
814
{
815
    TCGv r_const;
816
    int l1;
817

    
818
    l1 = gen_new_label();
819
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
820
    r_const = tcg_const_i32(TT_DIV_ZERO);
821
    tcg_gen_helper_0_1(raise_exception, r_const);
822
    tcg_temp_free(r_const);
823
    gen_set_label(l1);
824
}
825

    
826
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
827
{
828
    int l1, l2;
829

    
830
    l1 = gen_new_label();
831
    l2 = gen_new_label();
832
    tcg_gen_mov_tl(cpu_cc_src, src1);
833
    tcg_gen_mov_tl(cpu_cc_src2, src2);
834
    gen_trap_ifdivzero_tl(cpu_cc_src2);
835
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
836
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
837
    tcg_gen_movi_i64(dst, INT64_MIN);
838
    tcg_gen_br(l2);
839
    gen_set_label(l1);
840
    tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
841
    gen_set_label(l2);
842
}
843
#endif
844

    
845
static inline void gen_op_div_cc(TCGv dst)
846
{
847
    int l1;
848

    
849
    tcg_gen_mov_tl(cpu_cc_dst, dst);
850
    gen_cc_clear_icc();
851
    gen_cc_NZ_icc(cpu_cc_dst);
852
    l1 = gen_new_label();
853
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
854
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
855
    gen_set_label(l1);
856
}
857

    
858
static inline void gen_op_logic_cc(TCGv dst)
859
{
860
    tcg_gen_mov_tl(cpu_cc_dst, dst);
861

    
862
    gen_cc_clear_icc();
863
    gen_cc_NZ_icc(cpu_cc_dst);
864
#ifdef TARGET_SPARC64
865
    gen_cc_clear_xcc();
866
    gen_cc_NZ_xcc(cpu_cc_dst);
867
#endif
868
}
869

    
870
// 1
871
static inline void gen_op_eval_ba(TCGv dst)
872
{
873
    tcg_gen_movi_tl(dst, 1);
874
}
875

    
876
// Z
877
static inline void gen_op_eval_be(TCGv dst, TCGv src)
878
{
879
    gen_mov_reg_Z(dst, src);
880
}
881

    
882
// Z | (N ^ V)
883
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
884
{
885
    gen_mov_reg_N(cpu_tmp0, src);
886
    gen_mov_reg_V(dst, src);
887
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
888
    gen_mov_reg_Z(cpu_tmp0, src);
889
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
890
}
891

    
892
// N ^ V
893
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
894
{
895
    gen_mov_reg_V(cpu_tmp0, src);
896
    gen_mov_reg_N(dst, src);
897
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
898
}
899

    
900
// C | Z
901
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
902
{
903
    gen_mov_reg_Z(cpu_tmp0, src);
904
    gen_mov_reg_C(dst, src);
905
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
906
}
907

    
908
// C
909
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
910
{
911
    gen_mov_reg_C(dst, src);
912
}
913

    
914
// V
915
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
916
{
917
    gen_mov_reg_V(dst, src);
918
}
919

    
920
// 0
921
static inline void gen_op_eval_bn(TCGv dst)
922
{
923
    tcg_gen_movi_tl(dst, 0);
924
}
925

    
926
// N
927
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
928
{
929
    gen_mov_reg_N(dst, src);
930
}
931

    
932
// !Z
933
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
934
{
935
    gen_mov_reg_Z(dst, src);
936
    tcg_gen_xori_tl(dst, dst, 0x1);
937
}
938

    
939
// !(Z | (N ^ V))
940
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
941
{
942
    gen_mov_reg_N(cpu_tmp0, src);
943
    gen_mov_reg_V(dst, src);
944
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
945
    gen_mov_reg_Z(cpu_tmp0, src);
946
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
947
    tcg_gen_xori_tl(dst, dst, 0x1);
948
}
949

    
950
// !(N ^ V)
951
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
952
{
953
    gen_mov_reg_V(cpu_tmp0, src);
954
    gen_mov_reg_N(dst, src);
955
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
956
    tcg_gen_xori_tl(dst, dst, 0x1);
957
}
958

    
959
// !(C | Z)
960
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
961
{
962
    gen_mov_reg_Z(cpu_tmp0, src);
963
    gen_mov_reg_C(dst, src);
964
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
965
    tcg_gen_xori_tl(dst, dst, 0x1);
966
}
967

    
968
// !C
969
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
970
{
971
    gen_mov_reg_C(dst, src);
972
    tcg_gen_xori_tl(dst, dst, 0x1);
973
}
974

    
975
// !N
976
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
977
{
978
    gen_mov_reg_N(dst, src);
979
    tcg_gen_xori_tl(dst, dst, 0x1);
980
}
981

    
982
// !V
983
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
984
{
985
    gen_mov_reg_V(dst, src);
986
    tcg_gen_xori_tl(dst, dst, 0x1);
987
}
988

    
989
/*
990
  FPSR bit field FCC1 | FCC0:
991
   0 =
992
   1 <
993
   2 >
994
   3 unordered
995
*/
996
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
997
                                    unsigned int fcc_offset)
998
{
999
    tcg_gen_extu_i32_tl(reg, src);
1000
    tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
1001
    tcg_gen_andi_tl(reg, reg, 0x1);
1002
}
1003

    
1004
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005
                                    unsigned int fcc_offset)
1006
{
1007
    tcg_gen_extu_i32_tl(reg, src);
1008
    tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
1009
    tcg_gen_andi_tl(reg, reg, 0x1);
1010
}
1011

    
1012
// !0: FCC0 | FCC1
1013
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1014
                                    unsigned int fcc_offset)
1015
{
1016
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1017
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1018
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1019
}
1020

    
1021
// 1 or 2: FCC0 ^ FCC1
1022
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1023
                                    unsigned int fcc_offset)
1024
{
1025
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1026
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1027
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1028
}
1029

    
1030
// 1 or 3: FCC0
1031
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1032
                                    unsigned int fcc_offset)
1033
{
1034
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1035
}
1036

    
1037
// 1: FCC0 & !FCC1
1038
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1039
                                    unsigned int fcc_offset)
1040
{
1041
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1042
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1044
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1045
}
1046

    
1047
// 2 or 3: FCC1
1048
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1049
                                    unsigned int fcc_offset)
1050
{
1051
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1052
}
1053

    
1054
// 2: !FCC0 & FCC1
1055
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1056
                                    unsigned int fcc_offset)
1057
{
1058
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1059
    tcg_gen_xori_tl(dst, dst, 0x1);
1060
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1061
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1062
}
1063

    
1064
// 3: FCC0 & FCC1
1065
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1066
                                    unsigned int fcc_offset)
1067
{
1068
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1069
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1070
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071
}
1072

    
1073
// 0: !(FCC0 | FCC1)
1074
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1075
                                    unsigned int fcc_offset)
1076
{
1077
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1078
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1079
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1080
    tcg_gen_xori_tl(dst, dst, 0x1);
1081
}
1082

    
1083
// 0 or 3: !(FCC0 ^ FCC1)
1084
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1085
                                    unsigned int fcc_offset)
1086
{
1087
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1088
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1090
    tcg_gen_xori_tl(dst, dst, 0x1);
1091
}
1092

    
1093
// 0 or 2: !FCC0
1094
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1095
                                    unsigned int fcc_offset)
1096
{
1097
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1098
    tcg_gen_xori_tl(dst, dst, 0x1);
1099
}
1100

    
1101
// !1: !(FCC0 & !FCC1)
1102
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1103
                                    unsigned int fcc_offset)
1104
{
1105
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1106
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1107
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1108
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1109
    tcg_gen_xori_tl(dst, dst, 0x1);
1110
}
1111

    
1112
// 0 or 1: !FCC1
1113
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1114
                                    unsigned int fcc_offset)
1115
{
1116
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1117
    tcg_gen_xori_tl(dst, dst, 0x1);
1118
}
1119

    
1120
// !2: !(!FCC0 & FCC1)
1121
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1122
                                    unsigned int fcc_offset)
1123
{
1124
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1125
    tcg_gen_xori_tl(dst, dst, 0x1);
1126
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1127
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1128
    tcg_gen_xori_tl(dst, dst, 0x1);
1129
}
1130

    
1131
// !3: !(FCC0 & FCC1)
1132
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1133
                                    unsigned int fcc_offset)
1134
{
1135
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1136
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1137
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1138
    tcg_gen_xori_tl(dst, dst, 0x1);
1139
}
1140

    
1141
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1142
                               target_ulong pc2, TCGv r_cond)
1143
{
1144
    int l1;
1145

    
1146
    l1 = gen_new_label();
1147

    
1148
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1149

    
1150
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1151

    
1152
    gen_set_label(l1);
1153
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1154
}
1155

    
1156
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1157
                                target_ulong pc2, TCGv r_cond)
1158
{
1159
    int l1;
1160

    
1161
    l1 = gen_new_label();
1162

    
1163
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1164

    
1165
    gen_goto_tb(dc, 0, pc2, pc1);
1166

    
1167
    gen_set_label(l1);
1168
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1169
}
1170

    
1171
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1172
                                      TCGv r_cond)
1173
{
1174
    int l1, l2;
1175

    
1176
    l1 = gen_new_label();
1177
    l2 = gen_new_label();
1178

    
1179
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1180

    
1181
    tcg_gen_movi_tl(cpu_npc, npc1);
1182
    tcg_gen_br(l2);
1183

    
1184
    gen_set_label(l1);
1185
    tcg_gen_movi_tl(cpu_npc, npc2);
1186
    gen_set_label(l2);
1187
}
1188

    
1189
/* call this function before using the condition register as it may
1190
   have been set for a jump */
1191
static inline void flush_cond(DisasContext *dc, TCGv cond)
1192
{
1193
    if (dc->npc == JUMP_PC) {
1194
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195
        dc->npc = DYNAMIC_PC;
1196
    }
1197
}
1198

    
1199
static inline void save_npc(DisasContext *dc, TCGv cond)
1200
{
1201
    if (dc->npc == JUMP_PC) {
1202
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1203
        dc->npc = DYNAMIC_PC;
1204
    } else if (dc->npc != DYNAMIC_PC) {
1205
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1206
    }
1207
}
1208

    
1209
static inline void save_state(DisasContext *dc, TCGv cond)
1210
{
1211
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1212
    save_npc(dc, cond);
1213
}
1214

    
1215
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1216
{
1217
    if (dc->npc == JUMP_PC) {
1218
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1219
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220
        dc->pc = DYNAMIC_PC;
1221
    } else if (dc->npc == DYNAMIC_PC) {
1222
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1223
        dc->pc = DYNAMIC_PC;
1224
    } else {
1225
        dc->pc = dc->npc;
1226
    }
1227
}
1228

    
1229
static inline void gen_op_next_insn(void)
1230
{
1231
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1232
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1233
}
1234

    
1235
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1236
{
1237
    TCGv r_src;
1238

    
1239
#ifdef TARGET_SPARC64
1240
    if (cc)
1241
        r_src = cpu_xcc;
1242
    else
1243
        r_src = cpu_psr;
1244
#else
1245
    r_src = cpu_psr;
1246
#endif
1247
    switch (cond) {
1248
    case 0x0:
1249
        gen_op_eval_bn(r_dst);
1250
        break;
1251
    case 0x1:
1252
        gen_op_eval_be(r_dst, r_src);
1253
        break;
1254
    case 0x2:
1255
        gen_op_eval_ble(r_dst, r_src);
1256
        break;
1257
    case 0x3:
1258
        gen_op_eval_bl(r_dst, r_src);
1259
        break;
1260
    case 0x4:
1261
        gen_op_eval_bleu(r_dst, r_src);
1262
        break;
1263
    case 0x5:
1264
        gen_op_eval_bcs(r_dst, r_src);
1265
        break;
1266
    case 0x6:
1267
        gen_op_eval_bneg(r_dst, r_src);
1268
        break;
1269
    case 0x7:
1270
        gen_op_eval_bvs(r_dst, r_src);
1271
        break;
1272
    case 0x8:
1273
        gen_op_eval_ba(r_dst);
1274
        break;
1275
    case 0x9:
1276
        gen_op_eval_bne(r_dst, r_src);
1277
        break;
1278
    case 0xa:
1279
        gen_op_eval_bg(r_dst, r_src);
1280
        break;
1281
    case 0xb:
1282
        gen_op_eval_bge(r_dst, r_src);
1283
        break;
1284
    case 0xc:
1285
        gen_op_eval_bgu(r_dst, r_src);
1286
        break;
1287
    case 0xd:
1288
        gen_op_eval_bcc(r_dst, r_src);
1289
        break;
1290
    case 0xe:
1291
        gen_op_eval_bpos(r_dst, r_src);
1292
        break;
1293
    case 0xf:
1294
        gen_op_eval_bvc(r_dst, r_src);
1295
        break;
1296
    }
1297
}
1298

    
1299
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1300
{
1301
    unsigned int offset;
1302

    
1303
    switch (cc) {
1304
    default:
1305
    case 0x0:
1306
        offset = 0;
1307
        break;
1308
    case 0x1:
1309
        offset = 32 - 10;
1310
        break;
1311
    case 0x2:
1312
        offset = 34 - 10;
1313
        break;
1314
    case 0x3:
1315
        offset = 36 - 10;
1316
        break;
1317
    }
1318

    
1319
    switch (cond) {
1320
    case 0x0:
1321
        gen_op_eval_bn(r_dst);
1322
        break;
1323
    case 0x1:
1324
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1325
        break;
1326
    case 0x2:
1327
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1328
        break;
1329
    case 0x3:
1330
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1331
        break;
1332
    case 0x4:
1333
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1334
        break;
1335
    case 0x5:
1336
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1337
        break;
1338
    case 0x6:
1339
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1340
        break;
1341
    case 0x7:
1342
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1343
        break;
1344
    case 0x8:
1345
        gen_op_eval_ba(r_dst);
1346
        break;
1347
    case 0x9:
1348
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1349
        break;
1350
    case 0xa:
1351
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1352
        break;
1353
    case 0xb:
1354
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1355
        break;
1356
    case 0xc:
1357
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1358
        break;
1359
    case 0xd:
1360
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1361
        break;
1362
    case 0xe:
1363
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1364
        break;
1365
    case 0xf:
1366
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1367
        break;
1368
    }
1369
}
1370

    
1371
#ifdef TARGET_SPARC64
1372
// Inverted logic
1373
static const int gen_tcg_cond_reg[8] = {
1374
    -1,
1375
    TCG_COND_NE,
1376
    TCG_COND_GT,
1377
    TCG_COND_GE,
1378
    -1,
1379
    TCG_COND_EQ,
1380
    TCG_COND_LE,
1381
    TCG_COND_LT,
1382
};
1383

    
1384
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1385
{
1386
    int l1;
1387

    
1388
    l1 = gen_new_label();
1389
    tcg_gen_movi_tl(r_dst, 0);
1390
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1391
    tcg_gen_movi_tl(r_dst, 1);
1392
    gen_set_label(l1);
1393
}
1394
#endif
1395

    
1396
/* XXX: potentially incorrect if dynamic npc */
1397
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1398
                      TCGv r_cond)
1399
{
1400
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1401
    target_ulong target = dc->pc + offset;
1402

    
1403
    if (cond == 0x0) {
1404
        /* unconditional not taken */
1405
        if (a) {
1406
            dc->pc = dc->npc + 4;
1407
            dc->npc = dc->pc + 4;
1408
        } else {
1409
            dc->pc = dc->npc;
1410
            dc->npc = dc->pc + 4;
1411
        }
1412
    } else if (cond == 0x8) {
1413
        /* unconditional taken */
1414
        if (a) {
1415
            dc->pc = target;
1416
            dc->npc = dc->pc + 4;
1417
        } else {
1418
            dc->pc = dc->npc;
1419
            dc->npc = target;
1420
        }
1421
    } else {
1422
        flush_cond(dc, r_cond);
1423
        gen_cond(r_cond, cc, cond);
1424
        if (a) {
1425
            gen_branch_a(dc, target, dc->npc, r_cond);
1426
            dc->is_br = 1;
1427
        } else {
1428
            dc->pc = dc->npc;
1429
            dc->jump_pc[0] = target;
1430
            dc->jump_pc[1] = dc->npc + 4;
1431
            dc->npc = JUMP_PC;
1432
        }
1433
    }
1434
}
1435

    
1436
/* XXX: potentially incorrect if dynamic npc */
1437
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1438
                      TCGv r_cond)
1439
{
1440
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1441
    target_ulong target = dc->pc + offset;
1442

    
1443
    if (cond == 0x0) {
1444
        /* unconditional not taken */
1445
        if (a) {
1446
            dc->pc = dc->npc + 4;
1447
            dc->npc = dc->pc + 4;
1448
        } else {
1449
            dc->pc = dc->npc;
1450
            dc->npc = dc->pc + 4;
1451
        }
1452
    } else if (cond == 0x8) {
1453
        /* unconditional taken */
1454
        if (a) {
1455
            dc->pc = target;
1456
            dc->npc = dc->pc + 4;
1457
        } else {
1458
            dc->pc = dc->npc;
1459
            dc->npc = target;
1460
        }
1461
    } else {
1462
        flush_cond(dc, r_cond);
1463
        gen_fcond(r_cond, cc, cond);
1464
        if (a) {
1465
            gen_branch_a(dc, target, dc->npc, r_cond);
1466
            dc->is_br = 1;
1467
        } else {
1468
            dc->pc = dc->npc;
1469
            dc->jump_pc[0] = target;
1470
            dc->jump_pc[1] = dc->npc + 4;
1471
            dc->npc = JUMP_PC;
1472
        }
1473
    }
1474
}
1475

    
1476
#ifdef TARGET_SPARC64
1477
/* XXX: potentially incorrect if dynamic npc */
1478
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1479
                          TCGv r_cond, TCGv r_reg)
1480
{
1481
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1482
    target_ulong target = dc->pc + offset;
1483

    
1484
    flush_cond(dc, r_cond);
1485
    gen_cond_reg(r_cond, cond, r_reg);
1486
    if (a) {
1487
        gen_branch_a(dc, target, dc->npc, r_cond);
1488
        dc->is_br = 1;
1489
    } else {
1490
        dc->pc = dc->npc;
1491
        dc->jump_pc[0] = target;
1492
        dc->jump_pc[1] = dc->npc + 4;
1493
        dc->npc = JUMP_PC;
1494
    }
1495
}
1496

    
1497
static GenOpFunc * const gen_fcmps[4] = {
1498
    helper_fcmps,
1499
    helper_fcmps_fcc1,
1500
    helper_fcmps_fcc2,
1501
    helper_fcmps_fcc3,
1502
};
1503

    
1504
static GenOpFunc * const gen_fcmpd[4] = {
1505
    helper_fcmpd,
1506
    helper_fcmpd_fcc1,
1507
    helper_fcmpd_fcc2,
1508
    helper_fcmpd_fcc3,
1509
};
1510

    
1511
static GenOpFunc * const gen_fcmpq[4] = {
1512
    helper_fcmpq,
1513
    helper_fcmpq_fcc1,
1514
    helper_fcmpq_fcc2,
1515
    helper_fcmpq_fcc3,
1516
};
1517

    
1518
static GenOpFunc * const gen_fcmpes[4] = {
1519
    helper_fcmpes,
1520
    helper_fcmpes_fcc1,
1521
    helper_fcmpes_fcc2,
1522
    helper_fcmpes_fcc3,
1523
};
1524

    
1525
static GenOpFunc * const gen_fcmped[4] = {
1526
    helper_fcmped,
1527
    helper_fcmped_fcc1,
1528
    helper_fcmped_fcc2,
1529
    helper_fcmped_fcc3,
1530
};
1531

    
1532
static GenOpFunc * const gen_fcmpeq[4] = {
1533
    helper_fcmpeq,
1534
    helper_fcmpeq_fcc1,
1535
    helper_fcmpeq_fcc2,
1536
    helper_fcmpeq_fcc3,
1537
};
1538

    
1539
static inline void gen_op_fcmps(int fccno)
1540
{
1541
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1542
}
1543

    
1544
static inline void gen_op_fcmpd(int fccno)
1545
{
1546
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1547
}
1548

    
1549
static inline void gen_op_fcmpq(int fccno)
1550
{
1551
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1552
}
1553

    
1554
static inline void gen_op_fcmpes(int fccno)
1555
{
1556
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1557
}
1558

    
1559
static inline void gen_op_fcmped(int fccno)
1560
{
1561
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1562
}
1563

    
1564
static inline void gen_op_fcmpeq(int fccno)
1565
{
1566
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1567
}
1568

    
1569
#else
1570

    
1571
static inline void gen_op_fcmps(int fccno)
1572
{
1573
    tcg_gen_helper_0_0(helper_fcmps);
1574
}
1575

    
1576
static inline void gen_op_fcmpd(int fccno)
1577
{
1578
    tcg_gen_helper_0_0(helper_fcmpd);
1579
}
1580

    
1581
static inline void gen_op_fcmpq(int fccno)
1582
{
1583
    tcg_gen_helper_0_0(helper_fcmpq);
1584
}
1585

    
1586
static inline void gen_op_fcmpes(int fccno)
1587
{
1588
    tcg_gen_helper_0_0(helper_fcmpes);
1589
}
1590

    
1591
static inline void gen_op_fcmped(int fccno)
1592
{
1593
    tcg_gen_helper_0_0(helper_fcmped);
1594
}
1595

    
1596
static inline void gen_op_fcmpeq(int fccno)
1597
{
1598
    tcg_gen_helper_0_0(helper_fcmpeq);
1599
}
1600
#endif
1601

    
1602
static inline void gen_op_fpexception_im(int fsr_flags)
1603
{
1604
    TCGv r_const;
1605

    
1606
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1607
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1608
    r_const = tcg_const_i32(TT_FP_EXCP);
1609
    tcg_gen_helper_0_1(raise_exception, r_const);
1610
    tcg_temp_free(r_const);
1611
}
1612

    
1613
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1614
{
1615
#if !defined(CONFIG_USER_ONLY)
1616
    if (!dc->fpu_enabled) {
1617
        TCGv r_const;
1618

    
1619
        save_state(dc, r_cond);
1620
        r_const = tcg_const_i32(TT_NFPU_INSN);
1621
        tcg_gen_helper_0_1(raise_exception, r_const);
1622
        tcg_temp_free(r_const);
1623
        dc->is_br = 1;
1624
        return 1;
1625
    }
1626
#endif
1627
    return 0;
1628
}
1629

    
1630
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1631
{
1632
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1633
}
1634

    
1635
static inline void gen_clear_float_exceptions(void)
1636
{
1637
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1638
}
1639

    
1640
/* asi moves */
1641
#ifdef TARGET_SPARC64
1642
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1643
{
1644
    int asi;
1645
    TCGv r_asi;
1646

    
1647
    if (IS_IMM) {
1648
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1649
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1650
    } else {
1651
        asi = GET_FIELD(insn, 19, 26);
1652
        r_asi = tcg_const_i32(asi);
1653
    }
1654
    return r_asi;
1655
}
1656

    
1657
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1658
                              int sign)
1659
{
1660
    TCGv r_asi, r_size, r_sign;
1661

    
1662
    r_asi = gen_get_asi(insn, addr);
1663
    r_size = tcg_const_i32(size);
1664
    r_sign = tcg_const_i32(sign);
1665
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1666
    tcg_temp_free(r_sign);
1667
    tcg_temp_free(r_size);
1668
    tcg_temp_free(r_asi);
1669
}
1670

    
1671
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1672
{
1673
    TCGv r_asi, r_size;
1674

    
1675
    r_asi = gen_get_asi(insn, addr);
1676
    r_size = tcg_const_i32(size);
1677
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1678
    tcg_temp_free(r_size);
1679
    tcg_temp_free(r_asi);
1680
}
1681

    
1682
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1683
{
1684
    TCGv r_asi, r_size, r_rd;
1685

    
1686
    r_asi = gen_get_asi(insn, addr);
1687
    r_size = tcg_const_i32(size);
1688
    r_rd = tcg_const_i32(rd);
1689
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1690
    tcg_temp_free(r_rd);
1691
    tcg_temp_free(r_size);
1692
    tcg_temp_free(r_asi);
1693
}
1694

    
1695
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1696
{
1697
    TCGv r_asi, r_size, r_rd;
1698

    
1699
    r_asi = gen_get_asi(insn, addr);
1700
    r_size = tcg_const_i32(size);
1701
    r_rd = tcg_const_i32(rd);
1702
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1703
    tcg_temp_free(r_rd);
1704
    tcg_temp_free(r_size);
1705
    tcg_temp_free(r_asi);
1706
}
1707

    
1708
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1709
{
1710
    TCGv r_asi, r_size, r_sign;
1711

    
1712
    r_asi = gen_get_asi(insn, addr);
1713
    r_size = tcg_const_i32(4);
1714
    r_sign = tcg_const_i32(0);
1715
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1716
    tcg_temp_free(r_sign);
1717
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1718
    tcg_temp_free(r_size);
1719
    tcg_temp_free(r_asi);
1720
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1721
}
1722

    
1723
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1724
{
1725
    TCGv r_asi, r_rd;
1726

    
1727
    r_asi = gen_get_asi(insn, addr);
1728
    r_rd = tcg_const_i32(rd);
1729
    tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1730
    tcg_temp_free(r_rd);
1731
    tcg_temp_free(r_asi);
1732
}
1733

    
1734
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1735
{
1736
    TCGv r_temp, r_asi, r_size;
1737

    
1738
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1739
    gen_movl_reg_TN(rd + 1, r_temp);
1740
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1741
                       r_temp);
1742
    tcg_temp_free(r_temp);
1743
    r_asi = gen_get_asi(insn, addr);
1744
    r_size = tcg_const_i32(8);
1745
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1746
    tcg_temp_free(r_size);
1747
    tcg_temp_free(r_asi);
1748
}
1749

    
1750
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1751
                               int rd)
1752
{
1753
    TCGv r_val1, r_asi;
1754

    
1755
    r_val1 = tcg_temp_new(TCG_TYPE_TL);
1756
    gen_movl_reg_TN(rd, r_val1);
1757
    r_asi = gen_get_asi(insn, addr);
1758
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1759
    tcg_temp_free(r_asi);
1760
    tcg_temp_free(r_val1);
1761
}
1762

    
1763
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1764
                                int rd)
1765
{
1766
    TCGv r_asi;
1767

    
1768
    gen_movl_reg_TN(rd, cpu_tmp64);
1769
    r_asi = gen_get_asi(insn, addr);
1770
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1771
    tcg_temp_free(r_asi);
1772
}
1773

    
1774
#elif !defined(CONFIG_USER_ONLY)
1775

    
1776
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1777
                              int sign)
1778
{
1779
    TCGv r_asi, r_size, r_sign;
1780

    
1781
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1782
    r_size = tcg_const_i32(size);
1783
    r_sign = tcg_const_i32(sign);
1784
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1785
    tcg_temp_free(r_sign);
1786
    tcg_temp_free(r_size);
1787
    tcg_temp_free(r_asi);
1788
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1789
}
1790

    
1791
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1792
{
1793
    TCGv r_asi, r_size;
1794

    
1795
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1796
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1797
    r_size = tcg_const_i32(size);
1798
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1799
    tcg_temp_free(r_size);
1800
    tcg_temp_free(r_asi);
1801
}
1802

    
1803
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1804
{
1805
    TCGv r_asi, r_size, r_sign;
1806

    
1807
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1808
    r_size = tcg_const_i32(4);
1809
    r_sign = tcg_const_i32(0);
1810
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1811
    tcg_temp_free(r_sign);
1812
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1813
    tcg_temp_free(r_size);
1814
    tcg_temp_free(r_asi);
1815
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1816
}
1817

    
1818
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1819
{
1820
    TCGv r_asi, r_size, r_sign;
1821

    
1822
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1823
    r_size = tcg_const_i32(8);
1824
    r_sign = tcg_const_i32(0);
1825
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1826
    tcg_temp_free(r_sign);
1827
    tcg_temp_free(r_size);
1828
    tcg_temp_free(r_asi);
1829
    tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1830
    gen_movl_TN_reg(rd + 1, cpu_tmp0);
1831
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1832
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1833
    gen_movl_TN_reg(rd, hi);
1834
}
1835

    
1836
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1837
{
1838
    TCGv r_temp, r_asi, r_size;
1839

    
1840
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1841
    gen_movl_reg_TN(rd + 1, r_temp);
1842
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1843
    tcg_temp_free(r_temp);
1844
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1845
    r_size = tcg_const_i32(8);
1846
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1847
    tcg_temp_free(r_size);
1848
    tcg_temp_free(r_asi);
1849
}
1850
#endif
1851

    
1852
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1853
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1854
{
1855
    TCGv r_val, r_asi, r_size;
1856

    
1857
    gen_ld_asi(dst, addr, insn, 1, 0);
1858

    
1859
    r_val = tcg_const_i64(0xffULL);
1860
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1861
    r_size = tcg_const_i32(1);
1862
    tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1863
    tcg_temp_free(r_size);
1864
    tcg_temp_free(r_asi);
1865
    tcg_temp_free(r_val);
1866
}
1867
#endif
1868

    
1869
static inline TCGv get_src1(unsigned int insn, TCGv def)
1870
{
1871
    TCGv r_rs1 = def;
1872
    unsigned int rs1;
1873

    
1874
    rs1 = GET_FIELD(insn, 13, 17);
1875
    if (rs1 == 0)
1876
        r_rs1 = tcg_const_tl(0); // XXX how to free?
1877
    else if (rs1 < 8)
1878
        r_rs1 = cpu_gregs[rs1];
1879
    else
1880
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1881
    return r_rs1;
1882
}
1883

    
1884
static inline TCGv get_src2(unsigned int insn, TCGv def)
1885
{
1886
    TCGv r_rs2 = def;
1887
    unsigned int rs2;
1888

    
1889
    if (IS_IMM) { /* immediate */
1890
        rs2 = GET_FIELDs(insn, 19, 31);
1891
        r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1892
    } else { /* register */
1893
        rs2 = GET_FIELD(insn, 27, 31);
1894
        if (rs2 == 0)
1895
            r_rs2 = tcg_const_tl(0); // XXX how to free?
1896
        else if (rs2 < 8)
1897
            r_rs2 = cpu_gregs[rs2];
1898
        else
1899
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1900
    }
1901
    return r_rs2;
1902
}
1903

    
1904
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1905
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1906
        goto illegal_insn;
1907
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1908
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1909
        goto nfpu_insn;
1910

    
1911
/* before an instruction, dc->pc must be static */
1912
static void disas_sparc_insn(DisasContext * dc)
1913
{
1914
    unsigned int insn, opc, rs1, rs2, rd;
1915

    
1916
    if (unlikely(loglevel & CPU_LOG_TB_OP))
1917
        tcg_gen_debug_insn_start(dc->pc);
1918
    insn = ldl_code(dc->pc);
1919
    opc = GET_FIELD(insn, 0, 1);
1920

    
1921
    rd = GET_FIELD(insn, 2, 6);
1922

    
1923
    cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1924
    cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1925

    
1926
    switch (opc) {
1927
    case 0:                     /* branches/sethi */
1928
        {
1929
            unsigned int xop = GET_FIELD(insn, 7, 9);
1930
            int32_t target;
1931
            switch (xop) {
1932
#ifdef TARGET_SPARC64
1933
            case 0x1:           /* V9 BPcc */
1934
                {
1935
                    int cc;
1936

    
1937
                    target = GET_FIELD_SP(insn, 0, 18);
1938
                    target = sign_extend(target, 18);
1939
                    target <<= 2;
1940
                    cc = GET_FIELD_SP(insn, 20, 21);
1941
                    if (cc == 0)
1942
                        do_branch(dc, target, insn, 0, cpu_cond);
1943
                    else if (cc == 2)
1944
                        do_branch(dc, target, insn, 1, cpu_cond);
1945
                    else
1946
                        goto illegal_insn;
1947
                    goto jmp_insn;
1948
                }
1949
            case 0x3:           /* V9 BPr */
1950
                {
1951
                    target = GET_FIELD_SP(insn, 0, 13) |
1952
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1953
                    target = sign_extend(target, 16);
1954
                    target <<= 2;
1955
                    cpu_src1 = get_src1(insn, cpu_src1);
1956
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1957
                    goto jmp_insn;
1958
                }
1959
            case 0x5:           /* V9 FBPcc */
1960
                {
1961
                    int cc = GET_FIELD_SP(insn, 20, 21);
1962
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1963
                        goto jmp_insn;
1964
                    target = GET_FIELD_SP(insn, 0, 18);
1965
                    target = sign_extend(target, 19);
1966
                    target <<= 2;
1967
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1968
                    goto jmp_insn;
1969
                }
1970
#else
1971
            case 0x7:           /* CBN+x */
1972
                {
1973
                    goto ncp_insn;
1974
                }
1975
#endif
1976
            case 0x2:           /* BN+x */
1977
                {
1978
                    target = GET_FIELD(insn, 10, 31);
1979
                    target = sign_extend(target, 22);
1980
                    target <<= 2;
1981
                    do_branch(dc, target, insn, 0, cpu_cond);
1982
                    goto jmp_insn;
1983
                }
1984
            case 0x6:           /* FBN+x */
1985
                {
1986
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1987
                        goto jmp_insn;
1988
                    target = GET_FIELD(insn, 10, 31);
1989
                    target = sign_extend(target, 22);
1990
                    target <<= 2;
1991
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1992
                    goto jmp_insn;
1993
                }
1994
            case 0x4:           /* SETHI */
1995
                if (rd) { // nop
1996
                    uint32_t value = GET_FIELD(insn, 10, 31);
1997
                    TCGv r_const;
1998

    
1999
                    r_const = tcg_const_tl(value << 10);
2000
                    gen_movl_TN_reg(rd, r_const);
2001
                    tcg_temp_free(r_const);
2002
                }
2003
                break;
2004
            case 0x0:           /* UNIMPL */
2005
            default:
2006
                goto illegal_insn;
2007
            }
2008
            break;
2009
        }
2010
        break;
2011
    case 1:
2012
        /*CALL*/ {
2013
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
2014
            TCGv r_const;
2015

    
2016
            r_const = tcg_const_tl(dc->pc);
2017
            gen_movl_TN_reg(15, r_const);
2018
            tcg_temp_free(r_const);
2019
            target += dc->pc;
2020
            gen_mov_pc_npc(dc, cpu_cond);
2021
            dc->npc = target;
2022
        }
2023
        goto jmp_insn;
2024
    case 2:                     /* FPU & Logical Operations */
2025
        {
2026
            unsigned int xop = GET_FIELD(insn, 7, 12);
2027
            if (xop == 0x3a) {  /* generate trap */
2028
                int cond;
2029

    
2030
                cpu_src1 = get_src1(insn, cpu_src1);
2031
                if (IS_IMM) {
2032
                    rs2 = GET_FIELD(insn, 25, 31);
2033
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2034
                } else {
2035
                    rs2 = GET_FIELD(insn, 27, 31);
2036
                    if (rs2 != 0) {
2037
                        gen_movl_reg_TN(rs2, cpu_src2);
2038
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2039
                    } else
2040
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2041
                }
2042
                cond = GET_FIELD(insn, 3, 6);
2043
                if (cond == 0x8) {
2044
                    save_state(dc, cpu_cond);
2045
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
2046
                } else if (cond != 0) {
2047
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2048
#ifdef TARGET_SPARC64
2049
                    /* V9 icc/xcc */
2050
                    int cc = GET_FIELD_SP(insn, 11, 12);
2051

    
2052
                    save_state(dc, cpu_cond);
2053
                    if (cc == 0)
2054
                        gen_cond(r_cond, 0, cond);
2055
                    else if (cc == 2)
2056
                        gen_cond(r_cond, 1, cond);
2057
                    else
2058
                        goto illegal_insn;
2059
#else
2060
                    save_state(dc, cpu_cond);
2061
                    gen_cond(r_cond, 0, cond);
2062
#endif
2063
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2064
                    tcg_temp_free(r_cond);
2065
                }
2066
                gen_op_next_insn();
2067
                tcg_gen_exit_tb(0);
2068
                dc->is_br = 1;
2069
                goto jmp_insn;
2070
            } else if (xop == 0x28) {
2071
                rs1 = GET_FIELD(insn, 13, 17);
2072
                switch(rs1) {
2073
                case 0: /* rdy */
2074
#ifndef TARGET_SPARC64
2075
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2076
                                       manual, rdy on the microSPARC
2077
                                       II */
2078
                case 0x0f:          /* stbar in the SPARCv8 manual,
2079
                                       rdy on the microSPARC II */
2080
                case 0x10 ... 0x1f: /* implementation-dependent in the
2081
                                       SPARCv8 manual, rdy on the
2082
                                       microSPARC II */
2083
#endif
2084
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2085
                                  offsetof(CPUSPARCState, y));
2086
                    gen_movl_TN_reg(rd, cpu_tmp0);
2087
                    break;
2088
#ifdef TARGET_SPARC64
2089
                case 0x2: /* V9 rdccr */
2090
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2091
                    gen_movl_TN_reg(rd, cpu_dst);
2092
                    break;
2093
                case 0x3: /* V9 rdasi */
2094
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2095
                                   offsetof(CPUSPARCState, asi));
2096
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2097
                    gen_movl_TN_reg(rd, cpu_dst);
2098
                    break;
2099
                case 0x4: /* V9 rdtick */
2100
                    {
2101
                        TCGv r_tickptr;
2102

    
2103
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2104
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2105
                                       offsetof(CPUState, tick));
2106
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2107
                                           r_tickptr);
2108
                        tcg_temp_free(r_tickptr);
2109
                        gen_movl_TN_reg(rd, cpu_dst);
2110
                    }
2111
                    break;
2112
                case 0x5: /* V9 rdpc */
2113
                    {
2114
                        TCGv r_const;
2115

    
2116
                        r_const = tcg_const_tl(dc->pc);
2117
                        gen_movl_TN_reg(rd, r_const);
2118
                        tcg_temp_free(r_const);
2119
                    }
2120
                    break;
2121
                case 0x6: /* V9 rdfprs */
2122
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2123
                                   offsetof(CPUSPARCState, fprs));
2124
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2125
                    gen_movl_TN_reg(rd, cpu_dst);
2126
                    break;
2127
                case 0xf: /* V9 membar */
2128
                    break; /* no effect */
2129
                case 0x13: /* Graphics Status */
2130
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2131
                        goto jmp_insn;
2132
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2133
                                  offsetof(CPUSPARCState, gsr));
2134
                    gen_movl_TN_reg(rd, cpu_tmp0);
2135
                    break;
2136
                case 0x17: /* Tick compare */
2137
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2138
                                  offsetof(CPUSPARCState, tick_cmpr));
2139
                    gen_movl_TN_reg(rd, cpu_tmp0);
2140
                    break;
2141
                case 0x18: /* System tick */
2142
                    {
2143
                        TCGv r_tickptr;
2144

    
2145
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2146
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2147
                                       offsetof(CPUState, stick));
2148
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2149
                                           r_tickptr);
2150
                        tcg_temp_free(r_tickptr);
2151
                        gen_movl_TN_reg(rd, cpu_dst);
2152
                    }
2153
                    break;
2154
                case 0x19: /* System tick compare */
2155
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2156
                                  offsetof(CPUSPARCState, stick_cmpr));
2157
                    gen_movl_TN_reg(rd, cpu_tmp0);
2158
                    break;
2159
                case 0x10: /* Performance Control */
2160
                case 0x11: /* Performance Instrumentation Counter */
2161
                case 0x12: /* Dispatch Control */
2162
                case 0x14: /* Softint set, WO */
2163
                case 0x15: /* Softint clear, WO */
2164
                case 0x16: /* Softint write */
2165
#endif
2166
                default:
2167
                    goto illegal_insn;
2168
                }
2169
#if !defined(CONFIG_USER_ONLY)
2170
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2171
#ifndef TARGET_SPARC64
2172
                if (!supervisor(dc))
2173
                    goto priv_insn;
2174
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2175
#else
2176
                CHECK_IU_FEATURE(dc, HYPV);
2177
                if (!hypervisor(dc))
2178
                    goto priv_insn;
2179
                rs1 = GET_FIELD(insn, 13, 17);
2180
                switch (rs1) {
2181
                case 0: // hpstate
2182
                    // gen_op_rdhpstate();
2183
                    break;
2184
                case 1: // htstate
2185
                    // gen_op_rdhtstate();
2186
                    break;
2187
                case 3: // hintp
2188
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2189
                                   offsetof(CPUSPARCState, hintp));
2190
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2191
                    break;
2192
                case 5: // htba
2193
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2194
                                   offsetof(CPUSPARCState, htba));
2195
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2196
                    break;
2197
                case 6: // hver
2198
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2199
                                   offsetof(CPUSPARCState, hver));
2200
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2201
                    break;
2202
                case 31: // hstick_cmpr
2203
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2204
                                  offsetof(CPUSPARCState, hstick_cmpr));
2205
                    break;
2206
                default:
2207
                    goto illegal_insn;
2208
                }
2209
#endif
2210
                gen_movl_TN_reg(rd, cpu_dst);
2211
                break;
2212
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2213
                if (!supervisor(dc))
2214
                    goto priv_insn;
2215
#ifdef TARGET_SPARC64
2216
                rs1 = GET_FIELD(insn, 13, 17);
2217
                switch (rs1) {
2218
                case 0: // tpc
2219
                    {
2220
                        TCGv r_tsptr;
2221

    
2222
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2223
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2224
                                       offsetof(CPUState, tsptr));
2225
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2226
                                      offsetof(trap_state, tpc));
2227
                        tcg_temp_free(r_tsptr);
2228
                    }
2229
                    break;
2230
                case 1: // tnpc
2231
                    {
2232
                        TCGv r_tsptr;
2233

    
2234
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2235
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2236
                                       offsetof(CPUState, tsptr));
2237
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2238
                                      offsetof(trap_state, tnpc));
2239
                        tcg_temp_free(r_tsptr);
2240
                    }
2241
                    break;
2242
                case 2: // tstate
2243
                    {
2244
                        TCGv r_tsptr;
2245

    
2246
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2247
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2248
                                       offsetof(CPUState, tsptr));
2249
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2250
                                      offsetof(trap_state, tstate));
2251
                        tcg_temp_free(r_tsptr);
2252
                    }
2253
                    break;
2254
                case 3: // tt
2255
                    {
2256
                        TCGv r_tsptr;
2257

    
2258
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2259
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2260
                                       offsetof(CPUState, tsptr));
2261
                        tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2262
                                       offsetof(trap_state, tt));
2263
                        tcg_temp_free(r_tsptr);
2264
                    }
2265
                    break;
2266
                case 4: // tick
2267
                    {
2268
                        TCGv r_tickptr;
2269

    
2270
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2271
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2272
                                       offsetof(CPUState, tick));
2273
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2274
                                           r_tickptr);
2275
                        gen_movl_TN_reg(rd, cpu_tmp0);
2276
                        tcg_temp_free(r_tickptr);
2277
                    }
2278
                    break;
2279
                case 5: // tba
2280
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2281
                                  offsetof(CPUSPARCState, tbr));
2282
                    break;
2283
                case 6: // pstate
2284
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285
                                   offsetof(CPUSPARCState, pstate));
2286
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2287
                    break;
2288
                case 7: // tl
2289
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290
                                   offsetof(CPUSPARCState, tl));
2291
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2292
                    break;
2293
                case 8: // pil
2294
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295
                                   offsetof(CPUSPARCState, psrpil));
2296
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2297
                    break;
2298
                case 9: // cwp
2299
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2300
                    break;
2301
                case 10: // cansave
2302
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2303
                                   offsetof(CPUSPARCState, cansave));
2304
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2305
                    break;
2306
                case 11: // canrestore
2307
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2308
                                   offsetof(CPUSPARCState, canrestore));
2309
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2310
                    break;
2311
                case 12: // cleanwin
2312
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2313
                                   offsetof(CPUSPARCState, cleanwin));
2314
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2315
                    break;
2316
                case 13: // otherwin
2317
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2318
                                   offsetof(CPUSPARCState, otherwin));
2319
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2320
                    break;
2321
                case 14: // wstate
2322
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2323
                                   offsetof(CPUSPARCState, wstate));
2324
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2325
                    break;
2326
                case 16: // UA2005 gl
2327
                    CHECK_IU_FEATURE(dc, GL);
2328
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2329
                                   offsetof(CPUSPARCState, gl));
2330
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2331
                    break;
2332
                case 26: // UA2005 strand status
2333
                    CHECK_IU_FEATURE(dc, HYPV);
2334
                    if (!hypervisor(dc))
2335
                        goto priv_insn;
2336
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2337
                                   offsetof(CPUSPARCState, ssr));
2338
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2339
                    break;
2340
                case 31: // ver
2341
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2342
                                  offsetof(CPUSPARCState, version));
2343
                    break;
2344
                case 15: // fq
2345
                default:
2346
                    goto illegal_insn;
2347
                }
2348
#else
2349
                tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2350
                               offsetof(CPUSPARCState, wim));
2351
                tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2352
#endif
2353
                gen_movl_TN_reg(rd, cpu_tmp0);
2354
                break;
2355
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2356
#ifdef TARGET_SPARC64
2357
                save_state(dc, cpu_cond);
2358
                tcg_gen_helper_0_0(helper_flushw);
2359
#else
2360
                if (!supervisor(dc))
2361
                    goto priv_insn;
2362
                tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2363
                gen_movl_TN_reg(rd, cpu_tmp0);
2364
#endif
2365
                break;
2366
#endif
2367
            } else if (xop == 0x34) {   /* FPU Operations */
2368
                if (gen_trap_ifnofpu(dc, cpu_cond))
2369
                    goto jmp_insn;
2370
                gen_op_clear_ieee_excp_and_FTT();
2371
                rs1 = GET_FIELD(insn, 13, 17);
2372
                rs2 = GET_FIELD(insn, 27, 31);
2373
                xop = GET_FIELD(insn, 18, 26);
2374
                switch (xop) {
2375
                    case 0x1: /* fmovs */
2376
                        gen_op_load_fpr_FT0(rs2);
2377
                        gen_op_store_FT0_fpr(rd);
2378
                        break;
2379
                    case 0x5: /* fnegs */
2380
                        gen_op_load_fpr_FT1(rs2);
2381
                        tcg_gen_helper_0_0(helper_fnegs);
2382
                        gen_op_store_FT0_fpr(rd);
2383
                        break;
2384
                    case 0x9: /* fabss */
2385
                        gen_op_load_fpr_FT1(rs2);
2386
                        tcg_gen_helper_0_0(helper_fabss);
2387
                        gen_op_store_FT0_fpr(rd);
2388
                        break;
2389
                    case 0x29: /* fsqrts */
2390
                        CHECK_FPU_FEATURE(dc, FSQRT);
2391
                        gen_op_load_fpr_FT1(rs2);
2392
                        gen_clear_float_exceptions();
2393
                        tcg_gen_helper_0_0(helper_fsqrts);
2394
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2395
                        gen_op_store_FT0_fpr(rd);
2396
                        break;
2397
                    case 0x2a: /* fsqrtd */
2398
                        CHECK_FPU_FEATURE(dc, FSQRT);
2399
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2400
                        gen_clear_float_exceptions();
2401
                        tcg_gen_helper_0_0(helper_fsqrtd);
2402
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2403
                        gen_op_store_DT0_fpr(DFPREG(rd));
2404
                        break;
2405
                    case 0x2b: /* fsqrtq */
2406
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2407
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2408
                        gen_clear_float_exceptions();
2409
                        tcg_gen_helper_0_0(helper_fsqrtq);
2410
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2411
                        gen_op_store_QT0_fpr(QFPREG(rd));
2412
                        break;
2413
                    case 0x41:
2414
                        gen_op_load_fpr_FT0(rs1);
2415
                        gen_op_load_fpr_FT1(rs2);
2416
                        gen_clear_float_exceptions();
2417
                        tcg_gen_helper_0_0(helper_fadds);
2418
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2419
                        gen_op_store_FT0_fpr(rd);
2420
                        break;
2421
                    case 0x42:
2422
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2423
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2424
                        gen_clear_float_exceptions();
2425
                        tcg_gen_helper_0_0(helper_faddd);
2426
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2427
                        gen_op_store_DT0_fpr(DFPREG(rd));
2428
                        break;
2429
                    case 0x43: /* faddq */
2430
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2431
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2432
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2433
                        gen_clear_float_exceptions();
2434
                        tcg_gen_helper_0_0(helper_faddq);
2435
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2436
                        gen_op_store_QT0_fpr(QFPREG(rd));
2437
                        break;
2438
                    case 0x45:
2439
                        gen_op_load_fpr_FT0(rs1);
2440
                        gen_op_load_fpr_FT1(rs2);
2441
                        gen_clear_float_exceptions();
2442
                        tcg_gen_helper_0_0(helper_fsubs);
2443
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2444
                        gen_op_store_FT0_fpr(rd);
2445
                        break;
2446
                    case 0x46:
2447
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2448
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2449
                        gen_clear_float_exceptions();
2450
                        tcg_gen_helper_0_0(helper_fsubd);
2451
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2452
                        gen_op_store_DT0_fpr(DFPREG(rd));
2453
                        break;
2454
                    case 0x47: /* fsubq */
2455
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2456
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2457
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2458
                        gen_clear_float_exceptions();
2459
                        tcg_gen_helper_0_0(helper_fsubq);
2460
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2461
                        gen_op_store_QT0_fpr(QFPREG(rd));
2462
                        break;
2463
                    case 0x49: /* fmuls */
2464
                        CHECK_FPU_FEATURE(dc, FMUL);
2465
                        gen_op_load_fpr_FT0(rs1);
2466
                        gen_op_load_fpr_FT1(rs2);
2467
                        gen_clear_float_exceptions();
2468
                        tcg_gen_helper_0_0(helper_fmuls);
2469
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2470
                        gen_op_store_FT0_fpr(rd);
2471
                        break;
2472
                    case 0x4a: /* fmuld */
2473
                        CHECK_FPU_FEATURE(dc, FMUL);
2474
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2475
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2476
                        gen_clear_float_exceptions();
2477
                        tcg_gen_helper_0_0(helper_fmuld);
2478
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2479
                        gen_op_store_DT0_fpr(DFPREG(rd));
2480
                        break;
2481
                    case 0x4b: /* fmulq */
2482
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2483
                        CHECK_FPU_FEATURE(dc, FMUL);
2484
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2485
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2486
                        gen_clear_float_exceptions();
2487
                        tcg_gen_helper_0_0(helper_fmulq);
2488
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2489
                        gen_op_store_QT0_fpr(QFPREG(rd));
2490
                        break;
2491
                    case 0x4d:
2492
                        gen_op_load_fpr_FT0(rs1);
2493
                        gen_op_load_fpr_FT1(rs2);
2494
                        gen_clear_float_exceptions();
2495
                        tcg_gen_helper_0_0(helper_fdivs);
2496
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2497
                        gen_op_store_FT0_fpr(rd);
2498
                        break;
2499
                    case 0x4e:
2500
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2501
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2502
                        gen_clear_float_exceptions();
2503
                        tcg_gen_helper_0_0(helper_fdivd);
2504
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2505
                        gen_op_store_DT0_fpr(DFPREG(rd));
2506
                        break;
2507
                    case 0x4f: /* fdivq */
2508
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2509
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2510
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2511
                        gen_clear_float_exceptions();
2512
                        tcg_gen_helper_0_0(helper_fdivq);
2513
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2514
                        gen_op_store_QT0_fpr(QFPREG(rd));
2515
                        break;
2516
                    case 0x69:
2517
                        CHECK_FPU_FEATURE(dc, FSMULD);
2518
                        gen_op_load_fpr_FT0(rs1);
2519
                        gen_op_load_fpr_FT1(rs2);
2520
                        gen_clear_float_exceptions();
2521
                        tcg_gen_helper_0_0(helper_fsmuld);
2522
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2523
                        gen_op_store_DT0_fpr(DFPREG(rd));
2524
                        break;
2525
                    case 0x6e: /* fdmulq */
2526
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2527
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2528
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2529
                        gen_clear_float_exceptions();
2530
                        tcg_gen_helper_0_0(helper_fdmulq);
2531
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2532
                        gen_op_store_QT0_fpr(QFPREG(rd));
2533
                        break;
2534
                    case 0xc4:
2535
                        gen_op_load_fpr_FT1(rs2);
2536
                        gen_clear_float_exceptions();
2537
                        tcg_gen_helper_0_0(helper_fitos);
2538
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2539
                        gen_op_store_FT0_fpr(rd);
2540
                        break;
2541
                    case 0xc6:
2542
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2543
                        gen_clear_float_exceptions();
2544
                        tcg_gen_helper_0_0(helper_fdtos);
2545
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2546
                        gen_op_store_FT0_fpr(rd);
2547
                        break;
2548
                    case 0xc7: /* fqtos */
2549
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2550
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2551
                        gen_clear_float_exceptions();
2552
                        tcg_gen_helper_0_0(helper_fqtos);
2553
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2554
                        gen_op_store_FT0_fpr(rd);
2555
                        break;
2556
                    case 0xc8:
2557
                        gen_op_load_fpr_FT1(rs2);
2558
                        tcg_gen_helper_0_0(helper_fitod);
2559
                        gen_op_store_DT0_fpr(DFPREG(rd));
2560
                        break;
2561
                    case 0xc9:
2562
                        gen_op_load_fpr_FT1(rs2);
2563
                        tcg_gen_helper_0_0(helper_fstod);
2564
                        gen_op_store_DT0_fpr(DFPREG(rd));
2565
                        break;
2566
                    case 0xcb: /* fqtod */
2567
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2568
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2569
                        gen_clear_float_exceptions();
2570
                        tcg_gen_helper_0_0(helper_fqtod);
2571
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2572
                        gen_op_store_DT0_fpr(DFPREG(rd));
2573
                        break;
2574
                    case 0xcc: /* fitoq */
2575
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2576
                        gen_op_load_fpr_FT1(rs2);
2577
                        tcg_gen_helper_0_0(helper_fitoq);
2578
                        gen_op_store_QT0_fpr(QFPREG(rd));
2579
                        break;
2580
                    case 0xcd: /* fstoq */
2581
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2582
                        gen_op_load_fpr_FT1(rs2);
2583
                        tcg_gen_helper_0_0(helper_fstoq);
2584
                        gen_op_store_QT0_fpr(QFPREG(rd));
2585
                        break;
2586
                    case 0xce: /* fdtoq */
2587
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2588
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2589
                        tcg_gen_helper_0_0(helper_fdtoq);
2590
                        gen_op_store_QT0_fpr(QFPREG(rd));
2591
                        break;
2592
                    case 0xd1:
2593
                        gen_op_load_fpr_FT1(rs2);
2594
                        gen_clear_float_exceptions();
2595
                        tcg_gen_helper_0_0(helper_fstoi);
2596
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2597
                        gen_op_store_FT0_fpr(rd);
2598
                        break;
2599
                    case 0xd2:
2600
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2601
                        gen_clear_float_exceptions();
2602
                        tcg_gen_helper_0_0(helper_fdtoi);
2603
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2604
                        gen_op_store_FT0_fpr(rd);
2605
                        break;
2606
                    case 0xd3: /* fqtoi */
2607
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2608
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2609
                        gen_clear_float_exceptions();
2610
                        tcg_gen_helper_0_0(helper_fqtoi);
2611
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2612
                        gen_op_store_FT0_fpr(rd);
2613
                        break;
2614
#ifdef TARGET_SPARC64
2615
                    case 0x2: /* V9 fmovd */
2616
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2617
                        gen_op_store_DT0_fpr(DFPREG(rd));
2618
                        break;
2619
                    case 0x3: /* V9 fmovq */
2620
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2621
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2622
                        gen_op_store_QT0_fpr(QFPREG(rd));
2623
                        break;
2624
                    case 0x6: /* V9 fnegd */
2625
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2626
                        tcg_gen_helper_0_0(helper_fnegd);
2627
                        gen_op_store_DT0_fpr(DFPREG(rd));
2628
                        break;
2629
                    case 0x7: /* V9 fnegq */
2630
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2631
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2632
                        tcg_gen_helper_0_0(helper_fnegq);
2633
                        gen_op_store_QT0_fpr(QFPREG(rd));
2634
                        break;
2635
                    case 0xa: /* V9 fabsd */
2636
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2637
                        tcg_gen_helper_0_0(helper_fabsd);
2638
                        gen_op_store_DT0_fpr(DFPREG(rd));
2639
                        break;
2640
                    case 0xb: /* V9 fabsq */
2641
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2642
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2643
                        tcg_gen_helper_0_0(helper_fabsq);
2644
                        gen_op_store_QT0_fpr(QFPREG(rd));
2645
                        break;
2646
                    case 0x81: /* V9 fstox */
2647
                        gen_op_load_fpr_FT1(rs2);
2648
                        gen_clear_float_exceptions();
2649
                        tcg_gen_helper_0_0(helper_fstox);
2650
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2651
                        gen_op_store_DT0_fpr(DFPREG(rd));
2652
                        break;
2653
                    case 0x82: /* V9 fdtox */
2654
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2655
                        gen_clear_float_exceptions();
2656
                        tcg_gen_helper_0_0(helper_fdtox);
2657
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2658
                        gen_op_store_DT0_fpr(DFPREG(rd));
2659
                        break;
2660
                    case 0x83: /* V9 fqtox */
2661
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2662
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2663
                        gen_clear_float_exceptions();
2664
                        tcg_gen_helper_0_0(helper_fqtox);
2665
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2666
                        gen_op_store_DT0_fpr(DFPREG(rd));
2667
                        break;
2668
                    case 0x84: /* V9 fxtos */
2669
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2670
                        gen_clear_float_exceptions();
2671
                        tcg_gen_helper_0_0(helper_fxtos);
2672
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2673
                        gen_op_store_FT0_fpr(rd);
2674
                        break;
2675
                    case 0x88: /* V9 fxtod */
2676
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2677
                        gen_clear_float_exceptions();
2678
                        tcg_gen_helper_0_0(helper_fxtod);
2679
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2680
                        gen_op_store_DT0_fpr(DFPREG(rd));
2681
                        break;
2682
                    case 0x8c: /* V9 fxtoq */
2683
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2684
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2685
                        gen_clear_float_exceptions();
2686
                        tcg_gen_helper_0_0(helper_fxtoq);
2687
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2688
                        gen_op_store_QT0_fpr(QFPREG(rd));
2689
                        break;
2690
#endif
2691
                    default:
2692
                        goto illegal_insn;
2693
                }
2694
            } else if (xop == 0x35) {   /* FPU Operations */
2695
#ifdef TARGET_SPARC64
2696
                int cond;
2697
#endif
2698
                if (gen_trap_ifnofpu(dc, cpu_cond))
2699
                    goto jmp_insn;
2700
                gen_op_clear_ieee_excp_and_FTT();
2701
                rs1 = GET_FIELD(insn, 13, 17);
2702
                rs2 = GET_FIELD(insn, 27, 31);
2703
                xop = GET_FIELD(insn, 18, 26);
2704
#ifdef TARGET_SPARC64
2705
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2706
                    int l1;
2707

    
2708
                    l1 = gen_new_label();
2709
                    cond = GET_FIELD_SP(insn, 14, 17);
2710
                    cpu_src1 = get_src1(insn, cpu_src1);
2711
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2712
                                       0, l1);
2713
                    gen_op_load_fpr_FT0(rs2);
2714
                    gen_op_store_FT0_fpr(rd);
2715
                    gen_set_label(l1);
2716
                    break;
2717
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2718
                    int l1;
2719

    
2720
                    l1 = gen_new_label();
2721
                    cond = GET_FIELD_SP(insn, 14, 17);
2722
                    cpu_src1 = get_src1(insn, cpu_src1);
2723
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2724
                                       0, l1);
2725
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2726
                    gen_op_store_DT0_fpr(DFPREG(rd));
2727
                    gen_set_label(l1);
2728
                    break;
2729
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2730
                    int l1;
2731

    
2732
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2733
                    l1 = gen_new_label();
2734
                    cond = GET_FIELD_SP(insn, 14, 17);
2735
                    cpu_src1 = get_src1(insn, cpu_src1);
2736
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2737
                                       0, l1);
2738
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2739
                    gen_op_store_QT0_fpr(QFPREG(rd));
2740
                    gen_set_label(l1);
2741
                    break;
2742
                }
2743
#endif
2744
                switch (xop) {
2745
#ifdef TARGET_SPARC64
2746
#define FMOVCC(size_FDQ, fcc)                                           \
2747
                    {                                                   \
2748
                        TCGv r_cond;                                    \
2749
                        int l1;                                         \
2750
                                                                        \
2751
                        l1 = gen_new_label();                           \
2752
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2753
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2754
                        gen_fcond(r_cond, fcc, cond);                   \
2755
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2756
                                           0, l1);                      \
2757
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2758
                            (glue(size_FDQ, FPREG(rs2)));               \
2759
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2760
                            (glue(size_FDQ, FPREG(rd)));                \
2761
                        gen_set_label(l1);                              \
2762
                        tcg_temp_free(r_cond);                          \
2763
                    }
2764
                    case 0x001: /* V9 fmovscc %fcc0 */
2765
                        FMOVCC(F, 0);
2766
                        break;
2767
                    case 0x002: /* V9 fmovdcc %fcc0 */
2768
                        FMOVCC(D, 0);
2769
                        break;
2770
                    case 0x003: /* V9 fmovqcc %fcc0 */
2771
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2772
                        FMOVCC(Q, 0);
2773
                        break;
2774
                    case 0x041: /* V9 fmovscc %fcc1 */
2775
                        FMOVCC(F, 1);
2776
                        break;
2777
                    case 0x042: /* V9 fmovdcc %fcc1 */
2778
                        FMOVCC(D, 1);
2779
                        break;
2780
                    case 0x043: /* V9 fmovqcc %fcc1 */
2781
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2782
                        FMOVCC(Q, 1);
2783
                        break;
2784
                    case 0x081: /* V9 fmovscc %fcc2 */
2785
                        FMOVCC(F, 2);
2786
                        break;
2787
                    case 0x082: /* V9 fmovdcc %fcc2 */
2788
                        FMOVCC(D, 2);
2789
                        break;
2790
                    case 0x083: /* V9 fmovqcc %fcc2 */
2791
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2792
                        FMOVCC(Q, 2);
2793
                        break;
2794
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2795
                        FMOVCC(F, 3);
2796
                        break;
2797
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2798
                        FMOVCC(D, 3);
2799
                        break;
2800
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2801
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2802
                        FMOVCC(Q, 3);
2803
                        break;
2804
#undef FMOVCC
2805
#define FMOVCC(size_FDQ, icc)                                           \
2806
                    {                                                   \
2807
                        TCGv r_cond;                                    \
2808
                        int l1;                                         \
2809
                                                                        \
2810
                        l1 = gen_new_label();                           \
2811
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2812
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2813
                        gen_cond(r_cond, icc, cond);                    \
2814
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2815
                                           0, l1);                      \
2816
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2817
                            (glue(size_FDQ, FPREG(rs2)));               \
2818
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2819
                            (glue(size_FDQ, FPREG(rd)));                \
2820
                        gen_set_label(l1);                              \
2821
                        tcg_temp_free(r_cond);                          \
2822
                    }
2823

    
2824
                    case 0x101: /* V9 fmovscc %icc */
2825
                        FMOVCC(F, 0);
2826
                        break;
2827
                    case 0x102: /* V9 fmovdcc %icc */
2828
                        FMOVCC(D, 0);
2829
                    case 0x103: /* V9 fmovqcc %icc */
2830
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2831
                        FMOVCC(Q, 0);
2832
                        break;
2833
                    case 0x181: /* V9 fmovscc %xcc */
2834
                        FMOVCC(F, 1);
2835
                        break;
2836
                    case 0x182: /* V9 fmovdcc %xcc */
2837
                        FMOVCC(D, 1);
2838
                        break;
2839
                    case 0x183: /* V9 fmovqcc %xcc */
2840
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2841
                        FMOVCC(Q, 1);
2842
                        break;
2843
#undef FMOVCC
2844
#endif
2845
                    case 0x51: /* fcmps, V9 %fcc */
2846
                        gen_op_load_fpr_FT0(rs1);
2847
                        gen_op_load_fpr_FT1(rs2);
2848
                        gen_op_fcmps(rd & 3);
2849
                        break;
2850
                    case 0x52: /* fcmpd, V9 %fcc */
2851
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2852
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2853
                        gen_op_fcmpd(rd & 3);
2854
                        break;
2855
                    case 0x53: /* fcmpq, V9 %fcc */
2856
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2857
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2858
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2859
                        gen_op_fcmpq(rd & 3);
2860
                        break;
2861
                    case 0x55: /* fcmpes, V9 %fcc */
2862
                        gen_op_load_fpr_FT0(rs1);
2863
                        gen_op_load_fpr_FT1(rs2);
2864
                        gen_op_fcmpes(rd & 3);
2865
                        break;
2866
                    case 0x56: /* fcmped, V9 %fcc */
2867
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2868
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2869
                        gen_op_fcmped(rd & 3);
2870
                        break;
2871
                    case 0x57: /* fcmpeq, V9 %fcc */
2872
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2873
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2874
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2875
                        gen_op_fcmpeq(rd & 3);
2876
                        break;
2877
                    default:
2878
                        goto illegal_insn;
2879
                }
2880
            } else if (xop == 0x2) {
2881
                // clr/mov shortcut
2882

    
2883
                rs1 = GET_FIELD(insn, 13, 17);
2884
                if (rs1 == 0) {
2885
                    // or %g0, x, y -> mov T0, x; mov y, T0
2886
                    if (IS_IMM) {       /* immediate */
2887
                        TCGv r_const;
2888

    
2889
                        rs2 = GET_FIELDs(insn, 19, 31);
2890
                        r_const = tcg_const_tl((int)rs2);
2891
                        gen_movl_TN_reg(rd, r_const);
2892
                        tcg_temp_free(r_const);
2893
                    } else {            /* register */
2894
                        rs2 = GET_FIELD(insn, 27, 31);
2895
                        gen_movl_reg_TN(rs2, cpu_dst);
2896
                        gen_movl_TN_reg(rd, cpu_dst);
2897
                    }
2898
                } else {
2899
                    cpu_src1 = get_src1(insn, cpu_src1);
2900
                    if (IS_IMM) {       /* immediate */
2901
                        rs2 = GET_FIELDs(insn, 19, 31);
2902
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2903
                        gen_movl_TN_reg(rd, cpu_dst);
2904
                    } else {            /* register */
2905
                        // or x, %g0, y -> mov T1, x; mov y, T1
2906
                        rs2 = GET_FIELD(insn, 27, 31);
2907
                        if (rs2 != 0) {
2908
                            gen_movl_reg_TN(rs2, cpu_src2);
2909
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2910
                            gen_movl_TN_reg(rd, cpu_dst);
2911
                        } else
2912
                            gen_movl_TN_reg(rd, cpu_src1);
2913
                    }
2914
                }
2915
#ifdef TARGET_SPARC64
2916
            } else if (xop == 0x25) { /* sll, V9 sllx */
2917
                cpu_src1 = get_src1(insn, cpu_src1);
2918
                if (IS_IMM) {   /* immediate */
2919
                    rs2 = GET_FIELDs(insn, 20, 31);
2920
                    if (insn & (1 << 12)) {
2921
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2922
                    } else {
2923
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2924
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2925
                    }
2926
                } else {                /* register */
2927
                    rs2 = GET_FIELD(insn, 27, 31);
2928
                    gen_movl_reg_TN(rs2, cpu_src2);
2929
                    if (insn & (1 << 12)) {
2930
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2931
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2932
                    } else {
2933
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2934
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2935
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2936
                    }
2937
                }
2938
                gen_movl_TN_reg(rd, cpu_dst);
2939
            } else if (xop == 0x26) { /* srl, V9 srlx */
2940
                cpu_src1 = get_src1(insn, cpu_src1);
2941
                if (IS_IMM) {   /* immediate */
2942
                    rs2 = GET_FIELDs(insn, 20, 31);
2943
                    if (insn & (1 << 12)) {
2944
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2945
                    } else {
2946
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2947
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2948
                    }
2949
                } else {                /* register */
2950
                    rs2 = GET_FIELD(insn, 27, 31);
2951
                    gen_movl_reg_TN(rs2, cpu_src2);
2952
                    if (insn & (1 << 12)) {
2953
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2954
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2955
                    } else {
2956
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2957
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2958
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2959
                    }
2960
                }
2961
                gen_movl_TN_reg(rd, cpu_dst);
2962
            } else if (xop == 0x27) { /* sra, V9 srax */
2963
                cpu_src1 = get_src1(insn, cpu_src1);
2964
                if (IS_IMM) {   /* immediate */
2965
                    rs2 = GET_FIELDs(insn, 20, 31);
2966
                    if (insn & (1 << 12)) {
2967
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2968
                    } else {
2969
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2970
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2971
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2972
                    }
2973
                } else {                /* register */
2974
                    rs2 = GET_FIELD(insn, 27, 31);
2975
                    gen_movl_reg_TN(rs2, cpu_src2);
2976
                    if (insn & (1 << 12)) {
2977
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2978
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2979
                    } else {
2980
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2981
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2982
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2983
                    }
2984
                }
2985
                gen_movl_TN_reg(rd, cpu_dst);
2986
#endif
2987
            } else if (xop < 0x36) {
2988
                cpu_src1 = get_src1(insn, cpu_src1);
2989
                cpu_src2 = get_src2(insn, cpu_src2);
2990
                if (xop < 0x20) {
2991
                    switch (xop & ~0x10) {
2992
                    case 0x0:
2993
                        if (xop & 0x10)
2994
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2995
                        else
2996
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2997
                        break;
2998
                    case 0x1:
2999
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3000
                        if (xop & 0x10)
3001
                            gen_op_logic_cc(cpu_dst);
3002
                        break;
3003
                    case 0x2:
3004
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3005
                        if (xop & 0x10)
3006
                            gen_op_logic_cc(cpu_dst);
3007
                        break;
3008
                    case 0x3:
3009
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3010
                        if (xop & 0x10)
3011
                            gen_op_logic_cc(cpu_dst);
3012
                        break;
3013
                    case 0x4:
3014
                        if (xop & 0x10)
3015
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3016
                        else
3017
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3018
                        break;
3019
                    case 0x5:
3020
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3021
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3022
                        if (xop & 0x10)
3023
                            gen_op_logic_cc(cpu_dst);
3024
                        break;
3025
                    case 0x6:
3026
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3027
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3028
                        if (xop & 0x10)
3029
                            gen_op_logic_cc(cpu_dst);
3030
                        break;
3031
                    case 0x7:
3032
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3033
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3034
                        if (xop & 0x10)
3035
                            gen_op_logic_cc(cpu_dst);
3036
                        break;
3037
                    case 0x8:
3038
                        if (xop & 0x10)
3039
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3040
                        else {
3041
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3042
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3043
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3044
                        }
3045
                        break;
3046
#ifdef TARGET_SPARC64
3047
                    case 0x9: /* V9 mulx */
3048
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3049
                        break;
3050
#endif
3051
                    case 0xa:
3052
                        CHECK_IU_FEATURE(dc, MUL);
3053
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3054
                        if (xop & 0x10)
3055
                            gen_op_logic_cc(cpu_dst);
3056
                        break;
3057
                    case 0xb:
3058
                        CHECK_IU_FEATURE(dc, MUL);
3059
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3060
                        if (xop & 0x10)
3061
                            gen_op_logic_cc(cpu_dst);
3062
                        break;
3063
                    case 0xc:
3064
                        if (xop & 0x10)
3065
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3066
                        else {
3067
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3068
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3069
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3070
                        }
3071
                        break;
3072
#ifdef TARGET_SPARC64
3073
                    case 0xd: /* V9 udivx */
3074
                        tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3075
                        tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3076
                        gen_trap_ifdivzero_tl(cpu_cc_src2);
3077
                        tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3078
                        break;
3079
#endif
3080
                    case 0xe:
3081
                        CHECK_IU_FEATURE(dc, DIV);
3082
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3083
                                           cpu_src2);
3084
                        if (xop & 0x10)
3085
                            gen_op_div_cc(cpu_dst);
3086
                        break;
3087
                    case 0xf:
3088
                        CHECK_IU_FEATURE(dc, DIV);
3089
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3090
                                           cpu_src2);
3091
                        if (xop & 0x10)
3092
                            gen_op_div_cc(cpu_dst);
3093
                        break;
3094
                    default:
3095
                        goto illegal_insn;
3096
                    }
3097
                    gen_movl_TN_reg(rd, cpu_dst);
3098
                } else {
3099
                    switch (xop) {
3100
                    case 0x20: /* taddcc */
3101
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3102
                        gen_movl_TN_reg(rd, cpu_dst);
3103
                        break;
3104
                    case 0x21: /* tsubcc */
3105
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3106
                        gen_movl_TN_reg(rd, cpu_dst);
3107
                        break;
3108
                    case 0x22: /* taddcctv */
3109
                        save_state(dc, cpu_cond);
3110
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3111
                        gen_movl_TN_reg(rd, cpu_dst);
3112
                        break;
3113
                    case 0x23: /* tsubcctv */
3114
                        save_state(dc, cpu_cond);
3115
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3116
                        gen_movl_TN_reg(rd, cpu_dst);
3117
                        break;
3118
                    case 0x24: /* mulscc */
3119
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3120
                        gen_movl_TN_reg(rd, cpu_dst);
3121
                        break;
3122
#ifndef TARGET_SPARC64
3123
                    case 0x25:  /* sll */
3124
                        if (IS_IMM) { /* immediate */
3125
                            rs2 = GET_FIELDs(insn, 20, 31);
3126
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3127
                        } else { /* register */
3128
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3129
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3130
                        }
3131
                        gen_movl_TN_reg(rd, cpu_dst);
3132
                        break;
3133
                    case 0x26:  /* srl */
3134
                        if (IS_IMM) { /* immediate */
3135
                            rs2 = GET_FIELDs(insn, 20, 31);
3136
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3137
                        } else { /* register */
3138
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3139
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3140
                        }
3141
                        gen_movl_TN_reg(rd, cpu_dst);
3142
                        break;
3143
                    case 0x27:  /* sra */
3144
                        if (IS_IMM) { /* immediate */
3145
                            rs2 = GET_FIELDs(insn, 20, 31);
3146
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3147
                        } else { /* register */
3148
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3149
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3150
                        }
3151
                        gen_movl_TN_reg(rd, cpu_dst);
3152
                        break;
3153
#endif
3154
                    case 0x30:
3155
                        {
3156
                            switch(rd) {
3157
                            case 0: /* wry */
3158
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3159
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3160
                                              offsetof(CPUSPARCState, y));
3161
                                break;
3162
#ifndef TARGET_SPARC64
3163
                            case 0x01 ... 0x0f: /* undefined in the
3164
                                                   SPARCv8 manual, nop
3165
                                                   on the microSPARC
3166
                                                   II */
3167
                            case 0x10 ... 0x1f: /* implementation-dependent
3168
                                                   in the SPARCv8
3169
                                                   manual, nop on the
3170
                                                   microSPARC II */
3171
                                break;
3172
#else
3173
                            case 0x2: /* V9 wrccr */
3174
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3175
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3176
                                break;
3177
                            case 0x3: /* V9 wrasi */
3178
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3179
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3180
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3181
                                               offsetof(CPUSPARCState, asi));
3182
                                break;
3183
                            case 0x6: /* V9 wrfprs */
3184
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3185
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3186
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3187
                                               offsetof(CPUSPARCState, fprs));
3188
                                save_state(dc, cpu_cond);
3189
                                gen_op_next_insn();
3190
                                tcg_gen_exit_tb(0);
3191
                                dc->is_br = 1;
3192
                                break;
3193
                            case 0xf: /* V9 sir, nop if user */
3194
#if !defined(CONFIG_USER_ONLY)
3195
                                if (supervisor(dc))
3196
                                    ; // XXX
3197
#endif
3198
                                break;
3199
                            case 0x13: /* Graphics Status */
3200
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3201
                                    goto jmp_insn;
3202
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3203
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3204
                                              offsetof(CPUSPARCState, gsr));
3205
                                break;
3206
                            case 0x17: /* Tick compare */
3207
#if !defined(CONFIG_USER_ONLY)
3208
                                if (!supervisor(dc))
3209
                                    goto illegal_insn;
3210
#endif
3211
                                {
3212
                                    TCGv r_tickptr;
3213

    
3214
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3215
                                                   cpu_src2);
3216
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3217
                                                  offsetof(CPUSPARCState,
3218
                                                           tick_cmpr));
3219
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3220
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3221
                                                   offsetof(CPUState, tick));
3222
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3223
                                                       r_tickptr, cpu_tmp0);
3224
                                    tcg_temp_free(r_tickptr);
3225
                                }
3226
                                break;
3227
                            case 0x18: /* System tick */
3228
#if !defined(CONFIG_USER_ONLY)
3229
                                if (!supervisor(dc))
3230
                                    goto illegal_insn;
3231
#endif
3232
                                {
3233
                                    TCGv r_tickptr;
3234

    
3235
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3236
                                                   cpu_src2);
3237
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3238
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3239
                                                   offsetof(CPUState, stick));
3240
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3241
                                                       r_tickptr, cpu_dst);
3242
                                    tcg_temp_free(r_tickptr);
3243
                                }
3244
                                break;
3245
                            case 0x19: /* System tick compare */
3246
#if !defined(CONFIG_USER_ONLY)
3247
                                if (!supervisor(dc))
3248
                                    goto illegal_insn;
3249
#endif
3250
                                {
3251
                                    TCGv r_tickptr;
3252

    
3253
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3254
                                                   cpu_src2);
3255
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3256
                                                  offsetof(CPUSPARCState,
3257
                                                           stick_cmpr));
3258
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3259
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3260
                                                   offsetof(CPUState, stick));
3261
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3262
                                                       r_tickptr, cpu_tmp0);
3263
                                    tcg_temp_free(r_tickptr);
3264
                                }
3265
                                break;
3266

    
3267
                            case 0x10: /* Performance Control */
3268
                            case 0x11: /* Performance Instrumentation
3269
                                          Counter */
3270
                            case 0x12: /* Dispatch Control */
3271
                            case 0x14: /* Softint set */
3272
                            case 0x15: /* Softint clear */
3273
                            case 0x16: /* Softint write */
3274
#endif
3275
                            default:
3276
                                goto illegal_insn;
3277
                            }
3278
                        }
3279
                        break;
3280
#if !defined(CONFIG_USER_ONLY)
3281
                    case 0x31: /* wrpsr, V9 saved, restored */
3282
                        {
3283
                            if (!supervisor(dc))
3284
                                goto priv_insn;
3285
#ifdef TARGET_SPARC64
3286
                            switch (rd) {
3287
                            case 0:
3288
                                tcg_gen_helper_0_0(helper_saved);
3289
                                break;
3290
                            case 1:
3291
                                tcg_gen_helper_0_0(helper_restored);
3292
                                break;
3293
                            case 2: /* UA2005 allclean */
3294
                            case 3: /* UA2005 otherw */
3295
                            case 4: /* UA2005 normalw */
3296
                            case 5: /* UA2005 invalw */
3297
                                // XXX
3298
                            default:
3299
                                goto illegal_insn;
3300
                            }
3301
#else
3302
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3303
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3304
                            save_state(dc, cpu_cond);
3305
                            gen_op_next_insn();
3306
                            tcg_gen_exit_tb(0);
3307
                            dc->is_br = 1;
3308
#endif
3309
                        }
3310
                        break;
3311
                    case 0x32: /* wrwim, V9 wrpr */
3312
                        {
3313
                            if (!supervisor(dc))
3314
                                goto priv_insn;
3315
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3316
#ifdef TARGET_SPARC64
3317
                            switch (rd) {
3318
                            case 0: // tpc
3319
                                {
3320
                                    TCGv r_tsptr;
3321

    
3322
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3323
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3324
                                                   offsetof(CPUState, tsptr));
3325
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3326
                                                  offsetof(trap_state, tpc));
3327
                                    tcg_temp_free(r_tsptr);
3328
                                }
3329
                                break;
3330
                            case 1: // tnpc
3331
                                {
3332
                                    TCGv r_tsptr;
3333

    
3334
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3335
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3336
                                                   offsetof(CPUState, tsptr));
3337
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3338
                                                  offsetof(trap_state, tnpc));
3339
                                    tcg_temp_free(r_tsptr);
3340
                                }
3341
                                break;
3342
                            case 2: // tstate
3343
                                {
3344
                                    TCGv r_tsptr;
3345

    
3346
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3347
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3348
                                                   offsetof(CPUState, tsptr));
3349
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3350
                                                  offsetof(trap_state,
3351
                                                           tstate));
3352
                                    tcg_temp_free(r_tsptr);
3353
                                }
3354
                                break;
3355
                            case 3: // tt
3356
                                {
3357
                                    TCGv r_tsptr;
3358

    
3359
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3360
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3361
                                                   offsetof(CPUState, tsptr));
3362
                                    tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3363
                                                   offsetof(trap_state, tt));
3364
                                    tcg_temp_free(r_tsptr);
3365
                                }
3366
                                break;
3367
                            case 4: // tick
3368
                                {
3369
                                    TCGv r_tickptr;
3370

    
3371
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3372
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3373
                                                   offsetof(CPUState, tick));
3374
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3375
                                                       r_tickptr, cpu_tmp0);
3376
                                    tcg_temp_free(r_tickptr);
3377
                                }
3378
                                break;
3379
                            case 5: // tba
3380
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3381
                                              offsetof(CPUSPARCState, tbr));
3382
                                break;
3383
                            case 6: // pstate
3384
                                save_state(dc, cpu_cond);
3385
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3386
                                gen_op_next_insn();
3387
                                tcg_gen_exit_tb(0);
3388
                                dc->is_br = 1;
3389
                                break;
3390
                            case 7: // tl
3391
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3392
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3393
                                               offsetof(CPUSPARCState, tl));
3394
                                break;
3395
                            case 8: // pil
3396
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3397
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3398
                                               offsetof(CPUSPARCState,
3399
                                                        psrpil));
3400
                                break;
3401
                            case 9: // cwp
3402
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3403
                                break;
3404
                            case 10: // cansave
3405
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3406
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3407
                                               offsetof(CPUSPARCState,
3408
                                                        cansave));
3409
                                break;
3410
                            case 11: // canrestore
3411
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3412
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3413
                                               offsetof(CPUSPARCState,
3414
                                                        canrestore));
3415
                                break;
3416
                            case 12: // cleanwin
3417
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3418
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3419
                                               offsetof(CPUSPARCState,
3420
                                                        cleanwin));
3421
                                break;
3422
                            case 13: // otherwin
3423
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3424
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3425
                                               offsetof(CPUSPARCState,
3426
                                                        otherwin));
3427
                                break;
3428
                            case 14: // wstate
3429
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3430
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3431
                                               offsetof(CPUSPARCState,
3432
                                                        wstate));
3433
                                break;
3434
                            case 16: // UA2005 gl
3435
                                CHECK_IU_FEATURE(dc, GL);
3436
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3437
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3438
                                               offsetof(CPUSPARCState, gl));
3439
                                break;
3440
                            case 26: // UA2005 strand status
3441
                                CHECK_IU_FEATURE(dc, HYPV);
3442
                                if (!hypervisor(dc))
3443
                                    goto priv_insn;
3444
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3445
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3446
                                               offsetof(CPUSPARCState, ssr));
3447
                                break;
3448
                            default:
3449
                                goto illegal_insn;
3450
                            }
3451
#else
3452
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3453
                            tcg_gen_st_i32(cpu_tmp32, cpu_env,
3454
                                           offsetof(CPUSPARCState, wim));
3455
#endif
3456
                        }
3457
                        break;
3458
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3459
                        {
3460
#ifndef TARGET_SPARC64
3461
                            if (!supervisor(dc))
3462
                                goto priv_insn;
3463
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3464
                            tcg_gen_st_tl(cpu_tmp0, cpu_env,
3465
                                          offsetof(CPUSPARCState, tbr));
3466
#else
3467
                            CHECK_IU_FEATURE(dc, HYPV);
3468
                            if (!hypervisor(dc))
3469
                                goto priv_insn;
3470
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3471
                            switch (rd) {
3472
                            case 0: // hpstate
3473
                                // XXX gen_op_wrhpstate();
3474
                                save_state(dc, cpu_cond);
3475
                                gen_op_next_insn();
3476
                                tcg_gen_exit_tb(0);
3477
                                dc->is_br = 1;
3478
                                break;
3479
                            case 1: // htstate
3480
                                // XXX gen_op_wrhtstate();
3481
                                break;
3482
                            case 3: // hintp
3483
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3484
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3485
                                               offsetof(CPUSPARCState, hintp));
3486
                                break;
3487
                            case 5: // htba
3488
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3489
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3490
                                               offsetof(CPUSPARCState, htba));
3491
                                break;
3492
                            case 31: // hstick_cmpr
3493
                                {
3494
                                    TCGv r_tickptr;
3495

    
3496
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3497
                                                  offsetof(CPUSPARCState,
3498
                                                           hstick_cmpr));
3499
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3500
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3501
                                                   offsetof(CPUState, hstick));
3502
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3503
                                                       r_tickptr, cpu_tmp0);
3504
                                    tcg_temp_free(r_tickptr);
3505
                                }
3506
                                break;
3507
                            case 6: // hver readonly
3508
                            default:
3509
                                goto illegal_insn;
3510
                            }
3511
#endif
3512
                        }
3513
                        break;
3514
#endif
3515
#ifdef TARGET_SPARC64
3516
                    case 0x2c: /* V9 movcc */
3517
                        {
3518
                            int cc = GET_FIELD_SP(insn, 11, 12);
3519
                            int cond = GET_FIELD_SP(insn, 14, 17);
3520
                            TCGv r_cond;
3521
                            int l1;
3522

    
3523
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3524
                            if (insn & (1 << 18)) {
3525
                                if (cc == 0)
3526
                                    gen_cond(r_cond, 0, cond);
3527
                                else if (cc == 2)
3528
                                    gen_cond(r_cond, 1, cond);
3529
                                else
3530
                                    goto illegal_insn;
3531
                            } else {
3532
                                gen_fcond(r_cond, cc, cond);
3533
                            }
3534

    
3535
                            l1 = gen_new_label();
3536

    
3537
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3538
                            if (IS_IMM) {       /* immediate */
3539
                                TCGv r_const;
3540

    
3541
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3542
                                r_const = tcg_const_tl((int)rs2);
3543
                                gen_movl_TN_reg(rd, r_const);
3544
                                tcg_temp_free(r_const);
3545
                            } else {
3546
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3547
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3548
                                gen_movl_TN_reg(rd, cpu_tmp0);
3549
                            }
3550
                            gen_set_label(l1);
3551
                            tcg_temp_free(r_cond);
3552
                            break;
3553
                        }
3554
                    case 0x2d: /* V9 sdivx */
3555
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3556
                        gen_movl_TN_reg(rd, cpu_dst);
3557
                        break;
3558
                    case 0x2e: /* V9 popc */
3559
                        {
3560
                            cpu_src2 = get_src2(insn, cpu_src2);
3561
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3562
                                               cpu_src2);
3563
                            gen_movl_TN_reg(rd, cpu_dst);
3564
                        }
3565
                    case 0x2f: /* V9 movr */
3566
                        {
3567
                            int cond = GET_FIELD_SP(insn, 10, 12);
3568
                            int l1;
3569

    
3570
                            cpu_src1 = get_src1(insn, cpu_src1);
3571

    
3572
                            l1 = gen_new_label();
3573

    
3574
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3575
                                              cpu_src1, 0, l1);
3576
                            if (IS_IMM) {       /* immediate */
3577
                                TCGv r_const;
3578

    
3579
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3580
                                r_const = tcg_const_tl((int)rs2);
3581
                                gen_movl_TN_reg(rd, r_const);
3582
                                tcg_temp_free(r_const);
3583
                            } else {
3584
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3585
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3586
                                gen_movl_TN_reg(rd, cpu_tmp0);
3587
                            }
3588
                            gen_set_label(l1);
3589
                            break;
3590
                        }
3591
#endif
3592
                    default:
3593
                        goto illegal_insn;
3594
                    }
3595
                }
3596
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3597
#ifdef TARGET_SPARC64
3598
                int opf = GET_FIELD_SP(insn, 5, 13);
3599
                rs1 = GET_FIELD(insn, 13, 17);
3600
                rs2 = GET_FIELD(insn, 27, 31);
3601
                if (gen_trap_ifnofpu(dc, cpu_cond))
3602
                    goto jmp_insn;
3603

    
3604
                switch (opf) {
3605
                case 0x000: /* VIS I edge8cc */
3606
                case 0x001: /* VIS II edge8n */
3607
                case 0x002: /* VIS I edge8lcc */
3608
                case 0x003: /* VIS II edge8ln */
3609
                case 0x004: /* VIS I edge16cc */
3610
                case 0x005: /* VIS II edge16n */
3611
                case 0x006: /* VIS I edge16lcc */
3612
                case 0x007: /* VIS II edge16ln */
3613
                case 0x008: /* VIS I edge32cc */
3614
                case 0x009: /* VIS II edge32n */
3615
                case 0x00a: /* VIS I edge32lcc */
3616
                case 0x00b: /* VIS II edge32ln */
3617
                    // XXX
3618
                    goto illegal_insn;
3619
                case 0x010: /* VIS I array8 */
3620
                    CHECK_FPU_FEATURE(dc, VIS1);
3621
                    cpu_src1 = get_src1(insn, cpu_src1);
3622
                    gen_movl_reg_TN(rs2, cpu_src2);
3623
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3624
                                       cpu_src2);
3625
                    gen_movl_TN_reg(rd, cpu_dst);
3626
                    break;
3627
                case 0x012: /* VIS I array16 */
3628
                    CHECK_FPU_FEATURE(dc, VIS1);
3629
                    cpu_src1 = get_src1(insn, cpu_src1);
3630
                    gen_movl_reg_TN(rs2, cpu_src2);
3631
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3632
                                       cpu_src2);
3633
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3634
                    gen_movl_TN_reg(rd, cpu_dst);
3635
                    break;
3636
                case 0x014: /* VIS I array32 */
3637
                    CHECK_FPU_FEATURE(dc, VIS1);
3638
                    cpu_src1 = get_src1(insn, cpu_src1);
3639
                    gen_movl_reg_TN(rs2, cpu_src2);
3640
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3641
                                       cpu_src2);
3642
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3643
                    gen_movl_TN_reg(rd, cpu_dst);
3644
                    break;
3645
                case 0x018: /* VIS I alignaddr */
3646
                    CHECK_FPU_FEATURE(dc, VIS1);
3647
                    cpu_src1 = get_src1(insn, cpu_src1);
3648
                    gen_movl_reg_TN(rs2, cpu_src2);
3649
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3650
                                       cpu_src2);
3651
                    gen_movl_TN_reg(rd, cpu_dst);
3652
                    break;
3653
                case 0x019: /* VIS II bmask */
3654
                case 0x01a: /* VIS I alignaddrl */
3655
                    // XXX
3656
                    goto illegal_insn;
3657
                case 0x020: /* VIS I fcmple16 */
3658
                    CHECK_FPU_FEATURE(dc, VIS1);
3659
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3660
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3661
                    tcg_gen_helper_0_0(helper_fcmple16);
3662
                    gen_op_store_DT0_fpr(DFPREG(rd));
3663
                    break;
3664
                case 0x022: /* VIS I fcmpne16 */
3665
                    CHECK_FPU_FEATURE(dc, VIS1);
3666
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3667
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3668
                    tcg_gen_helper_0_0(helper_fcmpne16);
3669
                    gen_op_store_DT0_fpr(DFPREG(rd));
3670
                    break;
3671
                case 0x024: /* VIS I fcmple32 */
3672
                    CHECK_FPU_FEATURE(dc, VIS1);
3673
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3674
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3675
                    tcg_gen_helper_0_0(helper_fcmple32);
3676
                    gen_op_store_DT0_fpr(DFPREG(rd));
3677
                    break;
3678
                case 0x026: /* VIS I fcmpne32 */
3679
                    CHECK_FPU_FEATURE(dc, VIS1);
3680
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3681
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3682
                    tcg_gen_helper_0_0(helper_fcmpne32);
3683
                    gen_op_store_DT0_fpr(DFPREG(rd));
3684
                    break;
3685
                case 0x028: /* VIS I fcmpgt16 */
3686
                    CHECK_FPU_FEATURE(dc, VIS1);
3687
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3688
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3689
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3690
                    gen_op_store_DT0_fpr(DFPREG(rd));
3691
                    break;
3692
                case 0x02a: /* VIS I fcmpeq16 */
3693
                    CHECK_FPU_FEATURE(dc, VIS1);
3694
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3695
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3696
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3697
                    gen_op_store_DT0_fpr(DFPREG(rd));
3698
                    break;
3699
                case 0x02c: /* VIS I fcmpgt32 */
3700
                    CHECK_FPU_FEATURE(dc, VIS1);
3701
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3702
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3703
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3704
                    gen_op_store_DT0_fpr(DFPREG(rd));
3705
                    break;
3706
                case 0x02e: /* VIS I fcmpeq32 */
3707
                    CHECK_FPU_FEATURE(dc, VIS1);
3708
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3709
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3710
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3711
                    gen_op_store_DT0_fpr(DFPREG(rd));
3712
                    break;
3713
                case 0x031: /* VIS I fmul8x16 */
3714
                    CHECK_FPU_FEATURE(dc, VIS1);
3715
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3716
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3717
                    tcg_gen_helper_0_0(helper_fmul8x16);
3718
                    gen_op_store_DT0_fpr(DFPREG(rd));
3719
                    break;
3720
                case 0x033: /* VIS I fmul8x16au */
3721
                    CHECK_FPU_FEATURE(dc, VIS1);
3722
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3723
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3724
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3725
                    gen_op_store_DT0_fpr(DFPREG(rd));
3726
                    break;
3727
                case 0x035: /* VIS I fmul8x16al */
3728
                    CHECK_FPU_FEATURE(dc, VIS1);
3729
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3730
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3731
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3732
                    gen_op_store_DT0_fpr(DFPREG(rd));
3733
                    break;
3734
                case 0x036: /* VIS I fmul8sux16 */
3735
                    CHECK_FPU_FEATURE(dc, VIS1);
3736
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3737
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3738
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3739
                    gen_op_store_DT0_fpr(DFPREG(rd));
3740
                    break;
3741
                case 0x037: /* VIS I fmul8ulx16 */
3742
                    CHECK_FPU_FEATURE(dc, VIS1);
3743
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3744
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3745
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3746
                    gen_op_store_DT0_fpr(DFPREG(rd));
3747
                    break;
3748
                case 0x038: /* VIS I fmuld8sux16 */
3749
                    CHECK_FPU_FEATURE(dc, VIS1);
3750
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3751
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3752
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3753
                    gen_op_store_DT0_fpr(DFPREG(rd));
3754
                    break;
3755
                case 0x039: /* VIS I fmuld8ulx16 */
3756
                    CHECK_FPU_FEATURE(dc, VIS1);
3757
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3758
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3759
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3760
                    gen_op_store_DT0_fpr(DFPREG(rd));
3761
                    break;
3762
                case 0x03a: /* VIS I fpack32 */
3763
                case 0x03b: /* VIS I fpack16 */
3764
                case 0x03d: /* VIS I fpackfix */
3765
                case 0x03e: /* VIS I pdist */
3766
                    // XXX
3767
                    goto illegal_insn;
3768
                case 0x048: /* VIS I faligndata */
3769
                    CHECK_FPU_FEATURE(dc, VIS1);
3770
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3771
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3772
                    tcg_gen_helper_0_0(helper_faligndata);
3773
                    gen_op_store_DT0_fpr(DFPREG(rd));
3774
                    break;
3775
                case 0x04b: /* VIS I fpmerge */
3776
                    CHECK_FPU_FEATURE(dc, VIS1);
3777
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3778
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3779
                    tcg_gen_helper_0_0(helper_fpmerge);
3780
                    gen_op_store_DT0_fpr(DFPREG(rd));
3781
                    break;
3782
                case 0x04c: /* VIS II bshuffle */
3783
                    // XXX
3784
                    goto illegal_insn;
3785
                case 0x04d: /* VIS I fexpand */
3786
                    CHECK_FPU_FEATURE(dc, VIS1);
3787
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3788
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3789
                    tcg_gen_helper_0_0(helper_fexpand);
3790
                    gen_op_store_DT0_fpr(DFPREG(rd));
3791
                    break;
3792
                case 0x050: /* VIS I fpadd16 */
3793
                    CHECK_FPU_FEATURE(dc, VIS1);
3794
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3795
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3796
                    tcg_gen_helper_0_0(helper_fpadd16);
3797
                    gen_op_store_DT0_fpr(DFPREG(rd));
3798
                    break;
3799
                case 0x051: /* VIS I fpadd16s */
3800
                    CHECK_FPU_FEATURE(dc, VIS1);
3801
                    gen_op_load_fpr_FT0(rs1);
3802
                    gen_op_load_fpr_FT1(rs2);
3803
                    tcg_gen_helper_0_0(helper_fpadd16s);
3804
                    gen_op_store_FT0_fpr(rd);
3805
                    break;
3806
                case 0x052: /* VIS I fpadd32 */
3807
                    CHECK_FPU_FEATURE(dc, VIS1);
3808
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3809
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3810
                    tcg_gen_helper_0_0(helper_fpadd32);
3811
                    gen_op_store_DT0_fpr(DFPREG(rd));
3812
                    break;
3813
                case 0x053: /* VIS I fpadd32s */
3814
                    CHECK_FPU_FEATURE(dc, VIS1);
3815
                    gen_op_load_fpr_FT0(rs1);
3816
                    gen_op_load_fpr_FT1(rs2);
3817
                    tcg_gen_helper_0_0(helper_fpadd32s);
3818
                    gen_op_store_FT0_fpr(rd);
3819
                    break;
3820
                case 0x054: /* VIS I fpsub16 */
3821
                    CHECK_FPU_FEATURE(dc, VIS1);
3822
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3823
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3824
                    tcg_gen_helper_0_0(helper_fpsub16);
3825
                    gen_op_store_DT0_fpr(DFPREG(rd));
3826
                    break;
3827
                case 0x055: /* VIS I fpsub16s */
3828
                    CHECK_FPU_FEATURE(dc, VIS1);
3829
                    gen_op_load_fpr_FT0(rs1);
3830
                    gen_op_load_fpr_FT1(rs2);
3831
                    tcg_gen_helper_0_0(helper_fpsub16s);
3832
                    gen_op_store_FT0_fpr(rd);
3833
                    break;
3834
                case 0x056: /* VIS I fpsub32 */
3835
                    CHECK_FPU_FEATURE(dc, VIS1);
3836
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3837
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3838
                    tcg_gen_helper_0_0(helper_fpadd32);
3839
                    gen_op_store_DT0_fpr(DFPREG(rd));
3840
                    break;
3841
                case 0x057: /* VIS I fpsub32s */
3842
                    CHECK_FPU_FEATURE(dc, VIS1);
3843
                    gen_op_load_fpr_FT0(rs1);
3844
                    gen_op_load_fpr_FT1(rs2);
3845
                    tcg_gen_helper_0_0(helper_fpsub32s);
3846
                    gen_op_store_FT0_fpr(rd);
3847
                    break;
3848
                case 0x060: /* VIS I fzero */
3849
                    CHECK_FPU_FEATURE(dc, VIS1);
3850
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3851
                    gen_op_store_DT0_fpr(DFPREG(rd));
3852
                    break;
3853
                case 0x061: /* VIS I fzeros */
3854
                    CHECK_FPU_FEATURE(dc, VIS1);
3855
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3856
                    gen_op_store_FT0_fpr(rd);
3857
                    break;
3858
                case 0x062: /* VIS I fnor */
3859
                    CHECK_FPU_FEATURE(dc, VIS1);
3860
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3861
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3862
                    tcg_gen_helper_0_0(helper_fnor);
3863
                    gen_op_store_DT0_fpr(DFPREG(rd));
3864
                    break;
3865
                case 0x063: /* VIS I fnors */
3866
                    CHECK_FPU_FEATURE(dc, VIS1);
3867
                    gen_op_load_fpr_FT0(rs1);
3868
                    gen_op_load_fpr_FT1(rs2);
3869
                    tcg_gen_helper_0_0(helper_fnors);
3870
                    gen_op_store_FT0_fpr(rd);
3871
                    break;
3872
                case 0x064: /* VIS I fandnot2 */
3873
                    CHECK_FPU_FEATURE(dc, VIS1);
3874
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3875
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3876
                    tcg_gen_helper_0_0(helper_fandnot);
3877
                    gen_op_store_DT0_fpr(DFPREG(rd));
3878
                    break;
3879
                case 0x065: /* VIS I fandnot2s */
3880
                    CHECK_FPU_FEATURE(dc, VIS1);
3881
                    gen_op_load_fpr_FT1(rs1);
3882
                    gen_op_load_fpr_FT0(rs2);
3883
                    tcg_gen_helper_0_0(helper_fandnots);
3884
                    gen_op_store_FT0_fpr(rd);
3885
                    break;
3886
                case 0x066: /* VIS I fnot2 */
3887
                    CHECK_FPU_FEATURE(dc, VIS1);
3888
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3889
                    tcg_gen_helper_0_0(helper_fnot);
3890
                    gen_op_store_DT0_fpr(DFPREG(rd));
3891
                    break;
3892
                case 0x067: /* VIS I fnot2s */
3893
                    CHECK_FPU_FEATURE(dc, VIS1);
3894
                    gen_op_load_fpr_FT1(rs2);
3895
                    tcg_gen_helper_0_0(helper_fnot);
3896
                    gen_op_store_FT0_fpr(rd);
3897
                    break;
3898
                case 0x068: /* VIS I fandnot1 */
3899
                    CHECK_FPU_FEATURE(dc, VIS1);
3900
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3901
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3902
                    tcg_gen_helper_0_0(helper_fandnot);
3903
                    gen_op_store_DT0_fpr(DFPREG(rd));
3904
                    break;
3905
                case 0x069: /* VIS I fandnot1s */
3906
                    CHECK_FPU_FEATURE(dc, VIS1);
3907
                    gen_op_load_fpr_FT0(rs1);
3908
                    gen_op_load_fpr_FT1(rs2);
3909
                    tcg_gen_helper_0_0(helper_fandnots);
3910
                    gen_op_store_FT0_fpr(rd);
3911
                    break;
3912
                case 0x06a: /* VIS I fnot1 */
3913
                    CHECK_FPU_FEATURE(dc, VIS1);
3914
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3915
                    tcg_gen_helper_0_0(helper_fnot);
3916
                    gen_op_store_DT0_fpr(DFPREG(rd));
3917
                    break;
3918
                case 0x06b: /* VIS I fnot1s */
3919
                    CHECK_FPU_FEATURE(dc, VIS1);
3920
                    gen_op_load_fpr_FT1(rs1);
3921
                    tcg_gen_helper_0_0(helper_fnot);
3922
                    gen_op_store_FT0_fpr(rd);
3923
                    break;
3924
                case 0x06c: /* VIS I fxor */
3925
                    CHECK_FPU_FEATURE(dc, VIS1);
3926
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3927
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3928
                    tcg_gen_helper_0_0(helper_fxor);
3929
                    gen_op_store_DT0_fpr(DFPREG(rd));
3930
                    break;
3931
                case 0x06d: /* VIS I fxors */
3932
                    CHECK_FPU_FEATURE(dc, VIS1);
3933
                    gen_op_load_fpr_FT0(rs1);
3934
                    gen_op_load_fpr_FT1(rs2);
3935
                    tcg_gen_helper_0_0(helper_fxors);
3936
                    gen_op_store_FT0_fpr(rd);
3937
                    break;
3938
                case 0x06e: /* VIS I fnand */
3939
                    CHECK_FPU_FEATURE(dc, VIS1);
3940
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3941
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3942
                    tcg_gen_helper_0_0(helper_fnand);
3943
                    gen_op_store_DT0_fpr(DFPREG(rd));
3944
                    break;
3945
                case 0x06f: /* VIS I fnands */
3946
                    CHECK_FPU_FEATURE(dc, VIS1);
3947
                    gen_op_load_fpr_FT0(rs1);
3948
                    gen_op_load_fpr_FT1(rs2);
3949
                    tcg_gen_helper_0_0(helper_fnands);
3950
                    gen_op_store_FT0_fpr(rd);
3951
                    break;
3952
                case 0x070: /* VIS I fand */
3953
                    CHECK_FPU_FEATURE(dc, VIS1);
3954
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3955
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3956
                    tcg_gen_helper_0_0(helper_fand);
3957
                    gen_op_store_DT0_fpr(DFPREG(rd));
3958
                    break;
3959
                case 0x071: /* VIS I fands */
3960
                    CHECK_FPU_FEATURE(dc, VIS1);
3961
                    gen_op_load_fpr_FT0(rs1);
3962
                    gen_op_load_fpr_FT1(rs2);
3963
                    tcg_gen_helper_0_0(helper_fands);
3964
                    gen_op_store_FT0_fpr(rd);
3965
                    break;
3966
                case 0x072: /* VIS I fxnor */
3967
                    CHECK_FPU_FEATURE(dc, VIS1);
3968
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3969
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3970
                    tcg_gen_helper_0_0(helper_fxnor);
3971
                    gen_op_store_DT0_fpr(DFPREG(rd));
3972
                    break;
3973
                case 0x073: /* VIS I fxnors */
3974
                    CHECK_FPU_FEATURE(dc, VIS1);
3975
                    gen_op_load_fpr_FT0(rs1);
3976
                    gen_op_load_fpr_FT1(rs2);
3977
                    tcg_gen_helper_0_0(helper_fxnors);
3978
                    gen_op_store_FT0_fpr(rd);
3979
                    break;
3980
                case 0x074: /* VIS I fsrc1 */
3981
                    CHECK_FPU_FEATURE(dc, VIS1);
3982
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3983
                    gen_op_store_DT0_fpr(DFPREG(rd));
3984
                    break;
3985
                case 0x075: /* VIS I fsrc1s */
3986
                    CHECK_FPU_FEATURE(dc, VIS1);
3987
                    gen_op_load_fpr_FT0(rs1);
3988
                    gen_op_store_FT0_fpr(rd);
3989
                    break;
3990
                case 0x076: /* VIS I fornot2 */
3991
                    CHECK_FPU_FEATURE(dc, VIS1);
3992
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3993
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3994
                    tcg_gen_helper_0_0(helper_fornot);
3995
                    gen_op_store_DT0_fpr(DFPREG(rd));
3996
                    break;
3997
                case 0x077: /* VIS I fornot2s */
3998
                    CHECK_FPU_FEATURE(dc, VIS1);
3999
                    gen_op_load_fpr_FT1(rs1);
4000
                    gen_op_load_fpr_FT0(rs2);
4001
                    tcg_gen_helper_0_0(helper_fornots);
4002
                    gen_op_store_FT0_fpr(rd);
4003
                    break;
4004
                case 0x078: /* VIS I fsrc2 */
4005
                    CHECK_FPU_FEATURE(dc, VIS1);
4006
                    gen_op_load_fpr_DT0(DFPREG(rs2));
4007
                    gen_op_store_DT0_fpr(DFPREG(rd));
4008
                    break;
4009
                case 0x079: /* VIS I fsrc2s */
4010
                    CHECK_FPU_FEATURE(dc, VIS1);
4011
                    gen_op_load_fpr_FT0(rs2);
4012
                    gen_op_store_FT0_fpr(rd);
4013
                    break;
4014
                case 0x07a: /* VIS I fornot1 */
4015
                    CHECK_FPU_FEATURE(dc, VIS1);
4016
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4017
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4018
                    tcg_gen_helper_0_0(helper_fornot);
4019
                    gen_op_store_DT0_fpr(DFPREG(rd));
4020
                    break;
4021
                case 0x07b: /* VIS I fornot1s */
4022
                    CHECK_FPU_FEATURE(dc, VIS1);
4023
                    gen_op_load_fpr_FT0(rs1);
4024
                    gen_op_load_fpr_FT1(rs2);
4025
                    tcg_gen_helper_0_0(helper_fornots);
4026
                    gen_op_store_FT0_fpr(rd);
4027
                    break;
4028
                case 0x07c: /* VIS I for */
4029
                    CHECK_FPU_FEATURE(dc, VIS1);
4030
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4031
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4032
                    tcg_gen_helper_0_0(helper_for);
4033
                    gen_op_store_DT0_fpr(DFPREG(rd));
4034
                    break;
4035
                case 0x07d: /* VIS I fors */
4036
                    CHECK_FPU_FEATURE(dc, VIS1);
4037
                    gen_op_load_fpr_FT0(rs1);
4038
                    gen_op_load_fpr_FT1(rs2);
4039
                    tcg_gen_helper_0_0(helper_fors);
4040
                    gen_op_store_FT0_fpr(rd);
4041
                    break;
4042
                case 0x07e: /* VIS I fone */
4043
                    CHECK_FPU_FEATURE(dc, VIS1);
4044
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
4045
                    gen_op_store_DT0_fpr(DFPREG(rd));
4046
                    break;
4047
                case 0x07f: /* VIS I fones */
4048
                    CHECK_FPU_FEATURE(dc, VIS1);
4049
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
4050
                    gen_op_store_FT0_fpr(rd);
4051
                    break;
4052
                case 0x080: /* VIS I shutdown */
4053
                case 0x081: /* VIS II siam */
4054
                    // XXX
4055
                    goto illegal_insn;
4056
                default:
4057
                    goto illegal_insn;
4058
                }
4059
#else
4060
                goto ncp_insn;
4061
#endif
4062
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4063
#ifdef TARGET_SPARC64
4064
                goto illegal_insn;
4065
#else
4066
                goto ncp_insn;
4067
#endif
4068
#ifdef TARGET_SPARC64
4069
            } else if (xop == 0x39) { /* V9 return */
4070
                TCGv r_const;
4071

    
4072
                save_state(dc, cpu_cond);
4073
                cpu_src1 = get_src1(insn, cpu_src1);
4074
                if (IS_IMM) {   /* immediate */
4075
                    rs2 = GET_FIELDs(insn, 19, 31);
4076
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4077
                } else {                /* register */
4078
                    rs2 = GET_FIELD(insn, 27, 31);
4079
                    if (rs2) {
4080
                        gen_movl_reg_TN(rs2, cpu_src2);
4081
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4082
                    } else
4083
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4084
                }
4085
                tcg_gen_helper_0_0(helper_restore);
4086
                gen_mov_pc_npc(dc, cpu_cond);
4087
                r_const = tcg_const_i32(3);
4088
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4089
                tcg_temp_free(r_const);
4090
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4091
                dc->npc = DYNAMIC_PC;
4092
                goto jmp_insn;
4093
#endif
4094
            } else {
4095
                cpu_src1 = get_src1(insn, cpu_src1);
4096
                if (IS_IMM) {   /* immediate */
4097
                    rs2 = GET_FIELDs(insn, 19, 31);
4098
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4099
                } else {                /* register */
4100
                    rs2 = GET_FIELD(insn, 27, 31);
4101
                    if (rs2) {
4102
                        gen_movl_reg_TN(rs2, cpu_src2);
4103
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4104
                    } else
4105
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4106
                }
4107
                switch (xop) {
4108
                case 0x38:      /* jmpl */
4109
                    {
4110
                        TCGv r_const;
4111

    
4112
                        r_const = tcg_const_tl(dc->pc);
4113
                        gen_movl_TN_reg(rd, r_const);
4114
                        tcg_temp_free(r_const);
4115
                        gen_mov_pc_npc(dc, cpu_cond);
4116
                        r_const = tcg_const_i32(3);
4117
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4118
                                           r_const);
4119
                        tcg_temp_free(r_const);
4120
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4121
                        dc->npc = DYNAMIC_PC;
4122
                    }
4123
                    goto jmp_insn;
4124
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4125
                case 0x39:      /* rett, V9 return */
4126
                    {
4127
                        TCGv r_const;
4128

    
4129
                        if (!supervisor(dc))
4130
                            goto priv_insn;
4131
                        gen_mov_pc_npc(dc, cpu_cond);
4132
                        r_const = tcg_const_i32(3);
4133
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4134
                                           r_const);
4135
                        tcg_temp_free(r_const);
4136
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4137
                        dc->npc = DYNAMIC_PC;
4138
                        tcg_gen_helper_0_0(helper_rett);
4139
                    }
4140
                    goto jmp_insn;
4141
#endif
4142
                case 0x3b: /* flush */
4143
                    if (!((dc)->features & CPU_FEATURE_FLUSH))
4144
                        goto unimp_flush;
4145
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
4146
                    break;
4147
                case 0x3c:      /* save */
4148
                    save_state(dc, cpu_cond);
4149
                    tcg_gen_helper_0_0(helper_save);
4150
                    gen_movl_TN_reg(rd, cpu_dst);
4151
                    break;
4152
                case 0x3d:      /* restore */
4153
                    save_state(dc, cpu_cond);
4154
                    tcg_gen_helper_0_0(helper_restore);
4155
                    gen_movl_TN_reg(rd, cpu_dst);
4156
                    break;
4157
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4158
                case 0x3e:      /* V9 done/retry */
4159
                    {
4160
                        switch (rd) {
4161
                        case 0:
4162
                            if (!supervisor(dc))
4163
                                goto priv_insn;
4164
                            dc->npc = DYNAMIC_PC;
4165
                            dc->pc = DYNAMIC_PC;
4166
                            tcg_gen_helper_0_0(helper_done);
4167
                            goto jmp_insn;
4168
                        case 1:
4169
                            if (!supervisor(dc))
4170
                                goto priv_insn;
4171
                            dc->npc = DYNAMIC_PC;
4172
                            dc->pc = DYNAMIC_PC;
4173
                            tcg_gen_helper_0_0(helper_retry);
4174
                            goto jmp_insn;
4175
                        default:
4176
                            goto illegal_insn;
4177
                        }
4178
                    }
4179
                    break;
4180
#endif
4181
                default:
4182
                    goto illegal_insn;
4183
                }
4184
            }
4185
            break;
4186
        }
4187
        break;
4188
    case 3:                     /* load/store instructions */
4189
        {
4190
            unsigned int xop = GET_FIELD(insn, 7, 12);
4191

    
4192
            cpu_src1 = get_src1(insn, cpu_src1);
4193
            if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4194
                rs2 = GET_FIELD(insn, 27, 31);
4195
                gen_movl_reg_TN(rs2, cpu_src2);
4196
                tcg_gen_mov_tl(cpu_addr, cpu_src1);
4197
            } else if (IS_IMM) {     /* immediate */
4198
                rs2 = GET_FIELDs(insn, 19, 31);
4199
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4200
            } else {            /* register */
4201
                rs2 = GET_FIELD(insn, 27, 31);
4202
                if (rs2 != 0) {
4203
                    gen_movl_reg_TN(rs2, cpu_src2);
4204
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4205
                } else
4206
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4207
            }
4208
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4209
                (xop > 0x17 && xop <= 0x1d ) ||
4210
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4211
                switch (xop) {
4212
                case 0x0:       /* load unsigned word */
4213
                    gen_address_mask(dc, cpu_addr);
4214
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4215
                    break;
4216
                case 0x1:       /* load unsigned byte */
4217
                    gen_address_mask(dc, cpu_addr);
4218
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4219
                    break;
4220
                case 0x2:       /* load unsigned halfword */
4221
                    gen_address_mask(dc, cpu_addr);
4222
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4223
                    break;
4224
                case 0x3:       /* load double word */
4225
                    if (rd & 1)
4226
                        goto illegal_insn;
4227
                    else {
4228
                        TCGv r_const;
4229

    
4230
                        save_state(dc, cpu_cond);
4231
                        r_const = tcg_const_i32(7);
4232
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4233
                                           r_const); // XXX remove
4234
                        tcg_temp_free(r_const);
4235
                        gen_address_mask(dc, cpu_addr);
4236
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4237
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4238
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4239
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4240
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4241
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4242
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4243
                    }
4244
                    break;
4245
                case 0x9:       /* load signed byte */
4246
                    gen_address_mask(dc, cpu_addr);
4247
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4248
                    break;
4249
                case 0xa:       /* load signed halfword */
4250
                    gen_address_mask(dc, cpu_addr);
4251
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4252
                    break;
4253
                case 0xd:       /* ldstub -- XXX: should be atomically */
4254
                    {
4255
                        TCGv r_const;
4256

    
4257
                        gen_address_mask(dc, cpu_addr);
4258
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4259
                        r_const = tcg_const_tl(0xff);
4260
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4261
                        tcg_temp_free(r_const);
4262
                    }
4263
                    break;
4264
                case 0x0f:      /* swap register with memory. Also
4265
                                   atomically */
4266
                    CHECK_IU_FEATURE(dc, SWAP);
4267
                    gen_movl_reg_TN(rd, cpu_val);
4268
                    gen_address_mask(dc, cpu_addr);
4269
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4270
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4271
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4272
                    break;
4273
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4274
                case 0x10:      /* load word alternate */
4275
#ifndef TARGET_SPARC64
4276
                    if (IS_IMM)
4277
                        goto illegal_insn;
4278
                    if (!supervisor(dc))
4279
                        goto priv_insn;
4280
#endif
4281
                    save_state(dc, cpu_cond);
4282
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4283
                    break;
4284
                case 0x11:      /* load unsigned byte alternate */
4285
#ifndef TARGET_SPARC64
4286
                    if (IS_IMM)
4287
                        goto illegal_insn;
4288
                    if (!supervisor(dc))
4289
                        goto priv_insn;
4290
#endif
4291
                    save_state(dc, cpu_cond);
4292
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4293
                    break;
4294
                case 0x12:      /* load unsigned halfword alternate */
4295
#ifndef TARGET_SPARC64
4296
                    if (IS_IMM)
4297
                        goto illegal_insn;
4298
                    if (!supervisor(dc))
4299
                        goto priv_insn;
4300
#endif
4301
                    save_state(dc, cpu_cond);
4302
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4303
                    break;
4304
                case 0x13:      /* load double word alternate */
4305
#ifndef TARGET_SPARC64
4306
                    if (IS_IMM)
4307
                        goto illegal_insn;
4308
                    if (!supervisor(dc))
4309
                        goto priv_insn;
4310
#endif
4311
                    if (rd & 1)
4312
                        goto illegal_insn;
4313
                    save_state(dc, cpu_cond);
4314
                    gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4315
                    goto skip_move;
4316
                case 0x19:      /* load signed byte alternate */
4317
#ifndef TARGET_SPARC64
4318
                    if (IS_IMM)
4319
                        goto illegal_insn;
4320
                    if (!supervisor(dc))
4321
                        goto priv_insn;
4322
#endif
4323
                    save_state(dc, cpu_cond);
4324
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4325
                    break;
4326
                case 0x1a:      /* load signed halfword alternate */
4327
#ifndef TARGET_SPARC64
4328
                    if (IS_IMM)
4329
                        goto illegal_insn;
4330
                    if (!supervisor(dc))
4331
                        goto priv_insn;
4332
#endif
4333
                    save_state(dc, cpu_cond);
4334
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4335
                    break;
4336
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4337
#ifndef TARGET_SPARC64
4338
                    if (IS_IMM)
4339
                        goto illegal_insn;
4340
                    if (!supervisor(dc))
4341
                        goto priv_insn;
4342
#endif
4343
                    save_state(dc, cpu_cond);
4344
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4345
                    break;
4346
                case 0x1f:      /* swap reg with alt. memory. Also
4347
                                   atomically */
4348
                    CHECK_IU_FEATURE(dc, SWAP);
4349
#ifndef TARGET_SPARC64
4350
                    if (IS_IMM)
4351
                        goto illegal_insn;
4352
                    if (!supervisor(dc))
4353
                        goto priv_insn;
4354
#endif
4355
                    save_state(dc, cpu_cond);
4356
                    gen_movl_reg_TN(rd, cpu_val);
4357
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4358
                    break;
4359

    
4360
#ifndef TARGET_SPARC64
4361
                case 0x30: /* ldc */
4362
                case 0x31: /* ldcsr */
4363
                case 0x33: /* lddc */
4364
                    goto ncp_insn;
4365
#endif
4366
#endif
4367
#ifdef TARGET_SPARC64
4368
                case 0x08: /* V9 ldsw */
4369
                    gen_address_mask(dc, cpu_addr);
4370
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4371
                    break;
4372
                case 0x0b: /* V9 ldx */
4373
                    gen_address_mask(dc, cpu_addr);
4374
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4375
                    break;
4376
                case 0x18: /* V9 ldswa */
4377
                    save_state(dc, cpu_cond);
4378
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4379
                    break;
4380
                case 0x1b: /* V9 ldxa */
4381
                    save_state(dc, cpu_cond);
4382
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4383
                    break;
4384
                case 0x2d: /* V9 prefetch, no effect */
4385
                    goto skip_move;
4386
                case 0x30: /* V9 ldfa */
4387
                    save_state(dc, cpu_cond);
4388
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4389
                    goto skip_move;
4390
                case 0x33: /* V9 lddfa */
4391
                    save_state(dc, cpu_cond);
4392
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4393
                    goto skip_move;
4394
                case 0x3d: /* V9 prefetcha, no effect */
4395
                    goto skip_move;
4396
                case 0x32: /* V9 ldqfa */
4397
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4398
                    save_state(dc, cpu_cond);
4399
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4400
                    goto skip_move;
4401
#endif
4402
                default:
4403
                    goto illegal_insn;
4404
                }
4405
                gen_movl_TN_reg(rd, cpu_val);
4406
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4407
            skip_move: ;
4408
#endif
4409
            } else if (xop >= 0x20 && xop < 0x24) {
4410
                if (gen_trap_ifnofpu(dc, cpu_cond))
4411
                    goto jmp_insn;
4412
                save_state(dc, cpu_cond);
4413
                switch (xop) {
4414
                case 0x20:      /* load fpreg */
4415
                    gen_address_mask(dc, cpu_addr);
4416
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4417
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4418
                                   offsetof(CPUState, fpr[rd]));
4419
                    break;
4420
                case 0x21:      /* load fsr */
4421
                    gen_address_mask(dc, cpu_addr);
4422
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4423
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4424
                                   offsetof(CPUState, ft0));
4425
                    tcg_gen_helper_0_0(helper_ldfsr);
4426
                    break;
4427
                case 0x22:      /* load quad fpreg */
4428
                    {
4429
                        TCGv r_const;
4430

    
4431
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4432
                        r_const = tcg_const_i32(dc->mem_idx);
4433
                        tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4434
                        tcg_temp_free(r_const);
4435
                        gen_op_store_QT0_fpr(QFPREG(rd));
4436
                    }
4437
                    break;
4438
                case 0x23:      /* load double fpreg */
4439
                    {
4440
                        TCGv r_const;
4441

    
4442
                        r_const = tcg_const_i32(dc->mem_idx);
4443
                        tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4444
                        tcg_temp_free(r_const);
4445
                        gen_op_store_DT0_fpr(DFPREG(rd));
4446
                    }
4447
                    break;
4448
                default:
4449
                    goto illegal_insn;
4450
                }
4451
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4452
                       xop == 0xe || xop == 0x1e) {
4453
                gen_movl_reg_TN(rd, cpu_val);
4454
                switch (xop) {
4455
                case 0x4: /* store word */
4456
                    gen_address_mask(dc, cpu_addr);
4457
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4458
                    break;
4459
                case 0x5: /* store byte */
4460
                    gen_address_mask(dc, cpu_addr);
4461
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4462
                    break;
4463
                case 0x6: /* store halfword */
4464
                    gen_address_mask(dc, cpu_addr);
4465
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4466
                    break;
4467
                case 0x7: /* store double word */
4468
                    if (rd & 1)
4469
                        goto illegal_insn;
4470
                    else {
4471
                        TCGv r_low, r_const;
4472

    
4473
                        save_state(dc, cpu_cond);
4474
                        gen_address_mask(dc, cpu_addr);
4475
                        r_const = tcg_const_i32(7);
4476
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4477
                                           r_const); // XXX remove
4478
                        tcg_temp_free(r_const);
4479
                        r_low = tcg_temp_new(TCG_TYPE_TL);
4480
                        gen_movl_reg_TN(rd + 1, r_low);
4481
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4482
                                           r_low);
4483
                        tcg_temp_free(r_low);
4484
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4485
                    }
4486
                    break;
4487
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4488
                case 0x14: /* store word alternate */
4489
#ifndef TARGET_SPARC64
4490
                    if (IS_IMM)
4491
                        goto illegal_insn;
4492
                    if (!supervisor(dc))
4493
                        goto priv_insn;
4494
#endif
4495
                    save_state(dc, cpu_cond);
4496
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4497
                    break;
4498
                case 0x15: /* store byte alternate */
4499
#ifndef TARGET_SPARC64
4500
                    if (IS_IMM)
4501
                        goto illegal_insn;
4502
                    if (!supervisor(dc))
4503
                        goto priv_insn;
4504
#endif
4505
                    save_state(dc, cpu_cond);
4506
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4507
                    break;
4508
                case 0x16: /* store halfword alternate */
4509
#ifndef TARGET_SPARC64
4510
                    if (IS_IMM)
4511
                        goto illegal_insn;
4512
                    if (!supervisor(dc))
4513
                        goto priv_insn;
4514
#endif
4515
                    save_state(dc, cpu_cond);
4516
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4517
                    break;
4518
                case 0x17: /* store double word alternate */
4519
#ifndef TARGET_SPARC64
4520
                    if (IS_IMM)
4521
                        goto illegal_insn;
4522
                    if (!supervisor(dc))
4523
                        goto priv_insn;
4524
#endif
4525
                    if (rd & 1)
4526
                        goto illegal_insn;
4527
                    else {
4528
                        save_state(dc, cpu_cond);
4529
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4530
                    }
4531
                    break;
4532
#endif
4533
#ifdef TARGET_SPARC64
4534
                case 0x0e: /* V9 stx */
4535
                    gen_address_mask(dc, cpu_addr);
4536
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4537
                    break;
4538
                case 0x1e: /* V9 stxa */
4539
                    save_state(dc, cpu_cond);
4540
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4541
                    break;
4542
#endif
4543
                default:
4544
                    goto illegal_insn;
4545
                }
4546
            } else if (xop > 0x23 && xop < 0x28) {
4547
                if (gen_trap_ifnofpu(dc, cpu_cond))
4548
                    goto jmp_insn;
4549
                save_state(dc, cpu_cond);
4550
                switch (xop) {
4551
                case 0x24: /* store fpreg */
4552
                    gen_address_mask(dc, cpu_addr);
4553
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4554
                                   offsetof(CPUState, fpr[rd]));
4555
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4556
                    break;
4557
                case 0x25: /* stfsr, V9 stxfsr */
4558
                    gen_address_mask(dc, cpu_addr);
4559
                    tcg_gen_helper_0_0(helper_stfsr);
4560
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4561
                                   offsetof(CPUState, ft0));
4562
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4563
                    break;
4564
                case 0x26:
4565
#ifdef TARGET_SPARC64
4566
                    /* V9 stqf, store quad fpreg */
4567
                    {
4568
                        TCGv r_const;
4569

    
4570
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4571
                        gen_op_load_fpr_QT0(QFPREG(rd));
4572
                        r_const = tcg_const_i32(dc->mem_idx);
4573
                        tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4574
                        tcg_temp_free(r_const);
4575
                    }
4576
                    break;
4577
#else /* !TARGET_SPARC64 */
4578
                    /* stdfq, store floating point queue */
4579
#if defined(CONFIG_USER_ONLY)
4580
                    goto illegal_insn;
4581
#else
4582
                    if (!supervisor(dc))
4583
                        goto priv_insn;
4584
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4585
                        goto jmp_insn;
4586
                    goto nfq_insn;
4587
#endif
4588
#endif
4589
                case 0x27: /* store double fpreg */
4590
                    {
4591
                        TCGv r_const;
4592

    
4593
                        gen_op_load_fpr_DT0(DFPREG(rd));
4594
                        r_const = tcg_const_i32(dc->mem_idx);
4595
                        tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4596
                        tcg_temp_free(r_const);
4597
                    }
4598
                    break;
4599
                default:
4600
                    goto illegal_insn;
4601
                }
4602
            } else if (xop > 0x33 && xop < 0x3f) {
4603
                save_state(dc, cpu_cond);
4604
                switch (xop) {
4605
#ifdef TARGET_SPARC64
4606
                case 0x34: /* V9 stfa */
4607
                    gen_op_load_fpr_FT0(rd);
4608
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4609
                    break;
4610
                case 0x36: /* V9 stqfa */
4611
                    {
4612
                        TCGv r_const;
4613

    
4614
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4615
                        r_const = tcg_const_i32(7);
4616
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4617
                                           r_const);
4618
                        tcg_temp_free(r_const);
4619
                        gen_op_load_fpr_QT0(QFPREG(rd));
4620
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4621
                    }
4622
                    break;
4623
                case 0x37: /* V9 stdfa */
4624
                    gen_op_load_fpr_DT0(DFPREG(rd));
4625
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4626
                    break;
4627
                case 0x3c: /* V9 casa */
4628
                    gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4629
                    gen_movl_TN_reg(rd, cpu_val);
4630
                    break;
4631
                case 0x3e: /* V9 casxa */
4632
                    gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4633
                    gen_movl_TN_reg(rd, cpu_val);
4634
                    break;
4635
#else
4636
                case 0x34: /* stc */
4637
                case 0x35: /* stcsr */
4638
                case 0x36: /* stdcq */
4639
                case 0x37: /* stdc */
4640
                    goto ncp_insn;
4641
#endif
4642
                default:
4643
                    goto illegal_insn;
4644
                }
4645
            }
4646
            else
4647
                goto illegal_insn;
4648
        }
4649
        break;
4650
    }
4651
    /* default case for non jump instructions */
4652
    if (dc->npc == DYNAMIC_PC) {
4653
        dc->pc = DYNAMIC_PC;
4654
        gen_op_next_insn();
4655
    } else if (dc->npc == JUMP_PC) {
4656
        /* we can do a static jump */
4657
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4658
        dc->is_br = 1;
4659
    } else {
4660
        dc->pc = dc->npc;
4661
        dc->npc = dc->npc + 4;
4662
    }
4663
 jmp_insn:
4664
    return;
4665
 illegal_insn:
4666
    {
4667
        TCGv r_const;
4668

    
4669
        save_state(dc, cpu_cond);
4670
        r_const = tcg_const_i32(TT_ILL_INSN);
4671
        tcg_gen_helper_0_1(raise_exception, r_const);
4672
        tcg_temp_free(r_const);
4673
        dc->is_br = 1;
4674
    }
4675
    return;
4676
 unimp_flush:
4677
    {
4678
        TCGv r_const;
4679

    
4680
        save_state(dc, cpu_cond);
4681
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4682
        tcg_gen_helper_0_1(raise_exception, r_const);
4683
        tcg_temp_free(r_const);
4684
        dc->is_br = 1;
4685
    }
4686
    return;
4687
#if !defined(CONFIG_USER_ONLY)
4688
 priv_insn:
4689
    {
4690
        TCGv r_const;
4691

    
4692
        save_state(dc, cpu_cond);
4693
        r_const = tcg_const_i32(TT_PRIV_INSN);
4694
        tcg_gen_helper_0_1(raise_exception, r_const);
4695
        tcg_temp_free(r_const);
4696
        dc->is_br = 1;
4697
    }
4698
    return;
4699
#endif
4700
 nfpu_insn:
4701
    save_state(dc, cpu_cond);
4702
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4703
    dc->is_br = 1;
4704
    return;
4705
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4706
 nfq_insn:
4707
    save_state(dc, cpu_cond);
4708
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4709
    dc->is_br = 1;
4710
    return;
4711
#endif
4712
#ifndef TARGET_SPARC64
4713
 ncp_insn:
4714
    {
4715
        TCGv r_const;
4716

    
4717
        save_state(dc, cpu_cond);
4718
        r_const = tcg_const_i32(TT_NCP_INSN);
4719
        tcg_gen_helper_0_1(raise_exception, r_const);
4720
        tcg_temp_free(r_const);
4721
        dc->is_br = 1;
4722
    }
4723
    return;
4724
#endif
4725
}
4726

    
4727
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4728
                                                  int spc, CPUSPARCState *env)
4729
{
4730
    target_ulong pc_start, last_pc;
4731
    uint16_t *gen_opc_end;
4732
    DisasContext dc1, *dc = &dc1;
4733
    int j, lj = -1;
4734
    int num_insns;
4735
    int max_insns;
4736

    
4737
    memset(dc, 0, sizeof(DisasContext));
4738
    dc->tb = tb;
4739
    pc_start = tb->pc;
4740
    dc->pc = pc_start;
4741
    last_pc = dc->pc;
4742
    dc->npc = (target_ulong) tb->cs_base;
4743
    dc->mem_idx = cpu_mmu_index(env);
4744
    dc->features = env->features;
4745
    if ((dc->features & CPU_FEATURE_FLOAT)) {
4746
        dc->fpu_enabled = cpu_fpu_enabled(env);
4747
#if defined(CONFIG_USER_ONLY)
4748
        dc->features |= CPU_FEATURE_FLOAT128;
4749
#endif
4750
    } else
4751
        dc->fpu_enabled = 0;
4752
#ifdef TARGET_SPARC64
4753
    dc->address_mask_32bit = env->pstate & PS_AM;
4754
#endif
4755
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4756

    
4757
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4758
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4759
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4760

    
4761
    cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4762

    
4763
    // loads and stores
4764
    cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4765
    cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4766

    
4767
    num_insns = 0;
4768
    max_insns = tb->cflags & CF_COUNT_MASK;
4769
    if (max_insns == 0)
4770
        max_insns = CF_COUNT_MASK;
4771
    gen_icount_start();
4772
    do {
4773
        if (env->nb_breakpoints > 0) {
4774
            for(j = 0; j < env->nb_breakpoints; j++) {
4775
                if (env->breakpoints[j] == dc->pc) {
4776
                    if (dc->pc != pc_start)
4777
                        save_state(dc, cpu_cond);
4778
                    tcg_gen_helper_0_0(helper_debug);
4779
                    tcg_gen_exit_tb(0);
4780
                    dc->is_br = 1;
4781
                    goto exit_gen_loop;
4782
                }
4783
            }
4784
        }
4785
        if (spc) {
4786
            if (loglevel > 0)
4787
                fprintf(logfile, "Search PC...\n");
4788
            j = gen_opc_ptr - gen_opc_buf;
4789
            if (lj < j) {
4790
                lj++;
4791
                while (lj < j)
4792
                    gen_opc_instr_start[lj++] = 0;
4793
                gen_opc_pc[lj] = dc->pc;
4794
                gen_opc_npc[lj] = dc->npc;
4795
                gen_opc_instr_start[lj] = 1;
4796
                gen_opc_icount[lj] = num_insns;
4797
            }
4798
        }
4799
        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4800
            gen_io_start();
4801
        last_pc = dc->pc;
4802
        disas_sparc_insn(dc);
4803
        num_insns++;
4804

    
4805
        if (dc->is_br)
4806
            break;
4807
        /* if the next PC is different, we abort now */
4808
        if (dc->pc != (last_pc + 4))
4809
            break;
4810
        /* if we reach a page boundary, we stop generation so that the
4811
           PC of a TT_TFAULT exception is always in the right page */
4812
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4813
            break;
4814
        /* if single step mode, we generate only one instruction and
4815
           generate an exception */
4816
        if (env->singlestep_enabled) {
4817
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4818
            tcg_gen_exit_tb(0);
4819
            break;
4820
        }
4821
    } while ((gen_opc_ptr < gen_opc_end) &&
4822
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4823
             num_insns < max_insns);
4824

    
4825
 exit_gen_loop:
4826
    tcg_temp_free(cpu_addr);
4827
    tcg_temp_free(cpu_val);
4828
    tcg_temp_free(cpu_dst);
4829
    tcg_temp_free(cpu_tmp64);
4830
    tcg_temp_free(cpu_tmp32);
4831
    tcg_temp_free(cpu_tmp0);
4832
    if (tb->cflags & CF_LAST_IO)
4833
        gen_io_end();
4834
    if (!dc->is_br) {
4835
        if (dc->pc != DYNAMIC_PC &&
4836
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4837
            /* static PC and NPC: we can use direct chaining */
4838
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4839
        } else {
4840
            if (dc->pc != DYNAMIC_PC)
4841
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4842
            save_npc(dc, cpu_cond);
4843
            tcg_gen_exit_tb(0);
4844
        }
4845
    }
4846
    gen_icount_end(tb, num_insns);
4847
    *gen_opc_ptr = INDEX_op_end;
4848
    if (spc) {
4849
        j = gen_opc_ptr - gen_opc_buf;
4850
        lj++;
4851
        while (lj <= j)
4852
            gen_opc_instr_start[lj++] = 0;
4853
#if 0
4854
        if (loglevel > 0) {
4855
            page_dump(logfile);
4856
        }
4857
#endif
4858
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4859
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4860
    } else {
4861
        tb->size = last_pc + 4 - pc_start;
4862
        tb->icount = num_insns;
4863
    }
4864
#ifdef DEBUG_DISAS
4865
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4866
        fprintf(logfile, "--------------\n");
4867
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4868
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4869
        fprintf(logfile, "\n");
4870
    }
4871
#endif
4872
}
4873

    
4874
void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4875
{
4876
    gen_intermediate_code_internal(tb, 0, env);
4877
}
4878

    
4879
void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4880
{
4881
    gen_intermediate_code_internal(tb, 1, env);
4882
}
4883

    
4884
void gen_intermediate_code_init(CPUSPARCState *env)
4885
{
4886
    unsigned int i;
4887
    static int inited;
4888
    static const char * const gregnames[8] = {
4889
        NULL, // g0 not used
4890
        "g1",
4891
        "g2",
4892
        "g3",
4893
        "g4",
4894
        "g5",
4895
        "g6",
4896
        "g7",
4897
    };
4898

    
4899
    /* init various static tables */
4900
    if (!inited) {
4901
        inited = 1;
4902

    
4903
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4904
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4905
                                         offsetof(CPUState, regwptr),
4906