Revision 9656f324 target-mips/cpu.h
| b/target-mips/cpu.h | ||
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| 411 | 411 |
/* We waste some space so we can handle shadow registers like TCs. */ |
| 412 | 412 |
TCState tcs[MIPS_SHADOW_SET_MAX]; |
| 413 | 413 |
/* Qemu */ |
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int interrupt_request; |
|
| 415 | 414 |
int error_code; |
| 416 |
int user_mode_only; /* user mode only simulation */ |
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| 417 | 415 |
uint32_t hflags; /* CPU State */ |
| 418 | 416 |
/* TMASK defines different execution modes */ |
| 419 | 417 |
#define MIPS_HFLAG_TMASK 0x01FF |
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