Revision 968a40f6 target-microblaze/translate.c
| b/target-microblaze/translate.c | ||
|---|---|---|
| 810 | 810 |
|
| 811 | 811 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */ |
| 812 | 812 |
sync_jmpstate(dc); |
| 813 |
if (dc->rd) |
|
| 813 |
|
|
| 814 |
/* Verify alignment if needed. */ |
|
| 815 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
|
|
| 816 |
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
|
| 817 |
tcg_const_tl(0), tcg_const_tl(size)); |
|
| 818 |
} |
|
| 819 |
|
|
| 820 |
if (dc->rd) {
|
|
| 814 | 821 |
gen_load(dc, cpu_R[dc->rd], *addr, size); |
| 815 |
else {
|
|
| 822 |
} else {
|
|
| 816 | 823 |
gen_load(dc, env_imm, *addr, size); |
| 817 | 824 |
} |
| 818 | 825 |
|
| ... | ... | |
| 847 | 854 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */ |
| 848 | 855 |
sync_jmpstate(dc); |
| 849 | 856 |
addr = compute_ldst_addr(dc, &t); |
| 857 |
|
|
| 858 |
/* Verify alignment if needed. */ |
|
| 859 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
|
|
| 860 |
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
|
| 861 |
tcg_const_tl(1), tcg_const_tl(size)); |
|
| 862 |
} |
|
| 863 |
|
|
| 850 | 864 |
gen_store(dc, *addr, cpu_R[dc->rd], size); |
| 851 | 865 |
if (addr == &t) |
| 852 | 866 |
tcg_temp_free(t); |
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