Revision 97aff481 hw/versatile_pci.c
| b/hw/versatile_pci.c | ||
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| 79 | 79 |
&pci_vpb_config_readl, |
| 80 | 80 |
}; |
| 81 | 81 |
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static int pci_vpb_irq; |
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| 83 |
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| 84 | 82 |
static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
| 85 | 83 |
{
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| 86 | 84 |
return irq_num; |
| ... | ... | |
| 88 | 86 |
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| 89 | 87 |
static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level) |
| 90 | 88 |
{
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qemu_set_irq(pic[pci_vpb_irq + irq_num], level);
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qemu_set_irq(pic[irq_num], level); |
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| 92 | 90 |
} |
| 93 | 91 |
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PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
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PCIBus *pci_vpb_init(qemu_irq *pic, int realview) |
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| 95 | 93 |
{
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| 96 | 94 |
PCIBus *s; |
| 97 | 95 |
PCIDevice *d; |
| 98 | 96 |
int mem_config; |
| 99 | 97 |
uint32_t base; |
| 100 | 98 |
const char * name; |
| 99 |
qemu_irq *irqs; |
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int i; |
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| 101 | 101 |
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pci_vpb_irq = irq; |
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irqs = qemu_mallocz(sizeof(qemu_irq) * 4); |
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for (i = 0; i < 4; i++) {
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irqs[i] = pic[i]; |
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} |
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| 103 | 106 |
if (realview) {
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base = 0x60000000; |
| 105 | 108 |
name = "RealView EB PCI Controller"; |
| ... | ... | |
| 107 | 110 |
base = 0x40000000; |
| 108 | 111 |
name = "Versatile/PB PCI Controller"; |
| 109 | 112 |
} |
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s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3, 4);
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s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, irqs, 11 << 3, 4);
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| 111 | 114 |
/* ??? Register memory space. */ |
| 112 | 115 |
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| 113 | 116 |
mem_config = cpu_register_io_memory(0, pci_vpb_config_read, |
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