Revision 97bf4851
| b/hw/cs4231.c | ||
|---|---|---|
| 23 | 23 |
*/ |
| 24 | 24 |
|
| 25 | 25 |
#include "sysbus.h" |
| 26 |
|
|
| 27 |
/* debug CS4231 */ |
|
| 28 |
//#define DEBUG_CS |
|
| 26 |
#include "trace.h" |
|
| 29 | 27 |
|
| 30 | 28 |
/* |
| 31 | 29 |
* In addition to Crystal CS4231 there is a DMA controller on Sparc. |
| ... | ... | |
| 46 | 44 |
#define CS_VER 0xa0 |
| 47 | 45 |
#define CS_CDC_VER 0x8a |
| 48 | 46 |
|
| 49 |
#ifdef DEBUG_CS |
|
| 50 |
#define DPRINTF(fmt, ...) \ |
|
| 51 |
do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 52 |
#else |
|
| 53 |
#define DPRINTF(fmt, ...) |
|
| 54 |
#endif |
|
| 55 |
|
|
| 56 | 47 |
static void cs_reset(DeviceState *d) |
| 57 | 48 |
{
|
| 58 | 49 |
CSState *s = container_of(d, CSState, busdev.qdev); |
| ... | ... | |
| 79 | 70 |
ret = s->dregs[CS_RAP(s)]; |
| 80 | 71 |
break; |
| 81 | 72 |
} |
| 82 |
DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
|
|
| 73 |
trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
|
|
| 83 | 74 |
break; |
| 84 | 75 |
default: |
| 85 | 76 |
ret = s->regs[saddr]; |
| 86 |
DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
|
|
| 77 |
trace_cs4231_mem_readl_reg(saddr, ret);
|
|
| 87 | 78 |
break; |
| 88 | 79 |
} |
| 89 | 80 |
return ret; |
| ... | ... | |
| 95 | 86 |
uint32_t saddr; |
| 96 | 87 |
|
| 97 | 88 |
saddr = addr >> 2; |
| 98 |
DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
|
|
| 89 |
trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
|
|
| 99 | 90 |
switch (saddr) {
|
| 100 | 91 |
case 1: |
| 101 |
DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
|
|
| 102 |
s->dregs[CS_RAP(s)], val); |
|
| 92 |
trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val); |
|
| 103 | 93 |
switch(CS_RAP(s)) {
|
| 104 | 94 |
case 11: |
| 105 | 95 |
case 25: // Read only |
| b/hw/eccmemctl.c | ||
|---|---|---|
| 23 | 23 |
*/ |
| 24 | 24 |
|
| 25 | 25 |
#include "sysbus.h" |
| 26 |
|
|
| 27 |
//#define DEBUG_ECC |
|
| 28 |
|
|
| 29 |
#ifdef DEBUG_ECC |
|
| 30 |
#define DPRINTF(fmt, ...) \ |
|
| 31 |
do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 32 |
#else |
|
| 33 |
#define DPRINTF(fmt, ...) |
|
| 34 |
#endif |
|
| 26 |
#include "trace.h" |
|
| 35 | 27 |
|
| 36 | 28 |
/* There are 3 versions of this chip used in SMP sun4m systems: |
| 37 | 29 |
* MCC (version 0, implementation 0) SS-600MP |
| ... | ... | |
| 148 | 140 |
s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
| 149 | 141 |
else if (s->version == ECC_SMC) |
| 150 | 142 |
s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
| 151 |
DPRINTF("Write memory enable %08x\n", val);
|
|
| 143 |
trace_ecc_mem_writel_mer(val);
|
|
| 152 | 144 |
break; |
| 153 | 145 |
case ECC_MDR: |
| 154 | 146 |
s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
| 155 |
DPRINTF("Write memory delay %08x\n", val);
|
|
| 147 |
trace_ecc_mem_writel_mdr(val);
|
|
| 156 | 148 |
break; |
| 157 | 149 |
case ECC_MFSR: |
| 158 | 150 |
s->regs[ECC_MFSR] = val; |
| 159 | 151 |
qemu_irq_lower(s->irq); |
| 160 |
DPRINTF("Write memory fault status %08x\n", val);
|
|
| 152 |
trace_ecc_mem_writel_mfsr(val);
|
|
| 161 | 153 |
break; |
| 162 | 154 |
case ECC_VCR: |
| 163 | 155 |
s->regs[ECC_VCR] = val; |
| 164 |
DPRINTF("Write slot configuration %08x\n", val);
|
|
| 156 |
trace_ecc_mem_writel_vcr(val);
|
|
| 165 | 157 |
break; |
| 166 | 158 |
case ECC_DR: |
| 167 | 159 |
s->regs[ECC_DR] = val; |
| 168 |
DPRINTF("Write diagnostic %08x\n", val);
|
|
| 160 |
trace_ecc_mem_writel_dr(val);
|
|
| 169 | 161 |
break; |
| 170 | 162 |
case ECC_ECR0: |
| 171 | 163 |
s->regs[ECC_ECR0] = val; |
| 172 |
DPRINTF("Write event count 1 %08x\n", val);
|
|
| 164 |
trace_ecc_mem_writel_ecr0(val);
|
|
| 173 | 165 |
break; |
| 174 | 166 |
case ECC_ECR1: |
| 175 | 167 |
s->regs[ECC_ECR0] = val; |
| 176 |
DPRINTF("Write event count 2 %08x\n", val);
|
|
| 168 |
trace_ecc_mem_writel_ecr1(val);
|
|
| 177 | 169 |
break; |
| 178 | 170 |
} |
| 179 | 171 |
} |
| ... | ... | |
| 186 | 178 |
switch (addr >> 2) {
|
| 187 | 179 |
case ECC_MER: |
| 188 | 180 |
ret = s->regs[ECC_MER]; |
| 189 |
DPRINTF("Read memory enable %08x\n", ret);
|
|
| 181 |
trace_ecc_mem_readl_mer(ret);
|
|
| 190 | 182 |
break; |
| 191 | 183 |
case ECC_MDR: |
| 192 | 184 |
ret = s->regs[ECC_MDR]; |
| 193 |
DPRINTF("Read memory delay %08x\n", ret);
|
|
| 185 |
trace_ecc_mem_readl_mdr(ret);
|
|
| 194 | 186 |
break; |
| 195 | 187 |
case ECC_MFSR: |
| 196 | 188 |
ret = s->regs[ECC_MFSR]; |
| 197 |
DPRINTF("Read memory fault status %08x\n", ret);
|
|
| 189 |
trace_ecc_mem_readl_mfsr(ret);
|
|
| 198 | 190 |
break; |
| 199 | 191 |
case ECC_VCR: |
| 200 | 192 |
ret = s->regs[ECC_VCR]; |
| 201 |
DPRINTF("Read slot configuration %08x\n", ret);
|
|
| 193 |
trace_ecc_mem_readl_vcr(ret);
|
|
| 202 | 194 |
break; |
| 203 | 195 |
case ECC_MFAR0: |
| 204 | 196 |
ret = s->regs[ECC_MFAR0]; |
| 205 |
DPRINTF("Read memory fault address 0 %08x\n", ret);
|
|
| 197 |
trace_ecc_mem_readl_mfar0(ret);
|
|
| 206 | 198 |
break; |
| 207 | 199 |
case ECC_MFAR1: |
| 208 | 200 |
ret = s->regs[ECC_MFAR1]; |
| 209 |
DPRINTF("Read memory fault address 1 %08x\n", ret);
|
|
| 201 |
trace_ecc_mem_readl_mfar1(ret);
|
|
| 210 | 202 |
break; |
| 211 | 203 |
case ECC_DR: |
| 212 | 204 |
ret = s->regs[ECC_DR]; |
| 213 |
DPRINTF("Read diagnostic %08x\n", ret);
|
|
| 205 |
trace_ecc_mem_readl_dr(ret);
|
|
| 214 | 206 |
break; |
| 215 | 207 |
case ECC_ECR0: |
| 216 | 208 |
ret = s->regs[ECC_ECR0]; |
| 217 |
DPRINTF("Read event count 1 %08x\n", ret);
|
|
| 209 |
trace_ecc_mem_readl_ecr0(ret);
|
|
| 218 | 210 |
break; |
| 219 | 211 |
case ECC_ECR1: |
| 220 | 212 |
ret = s->regs[ECC_ECR0]; |
| 221 |
DPRINTF("Read event count 2 %08x\n", ret);
|
|
| 213 |
trace_ecc_mem_readl_ecr1(ret);
|
|
| 222 | 214 |
break; |
| 223 | 215 |
} |
| 224 | 216 |
return ret; |
| ... | ... | |
| 241 | 233 |
{
|
| 242 | 234 |
ECCState *s = opaque; |
| 243 | 235 |
|
| 244 |
DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
|
|
| 236 |
trace_ecc_diag_mem_writeb(addr, val);
|
|
| 245 | 237 |
s->diag[addr & ECC_DIAG_MASK] = val; |
| 246 | 238 |
} |
| 247 | 239 |
|
| ... | ... | |
| 250 | 242 |
ECCState *s = opaque; |
| 251 | 243 |
uint32_t ret = s->diag[(int)addr]; |
| 252 | 244 |
|
| 253 |
DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
|
|
| 245 |
trace_ecc_diag_mem_readb(addr, ret);
|
|
| 254 | 246 |
return ret; |
| 255 | 247 |
} |
| 256 | 248 |
|
| b/hw/lance.c | ||
|---|---|---|
| 40 | 40 |
#include "qemu-timer.h" |
| 41 | 41 |
#include "qemu_socket.h" |
| 42 | 42 |
#include "sun4m.h" |
| 43 |
|
|
| 44 | 43 |
#include "pcnet.h" |
| 44 |
#include "trace.h" |
|
| 45 | 45 |
|
| 46 | 46 |
typedef struct {
|
| 47 | 47 |
SysBusDevice busdev; |
| ... | ... | |
| 59 | 59 |
uint32_t val) |
| 60 | 60 |
{
|
| 61 | 61 |
SysBusPCNetState *d = opaque; |
| 62 |
#ifdef PCNET_DEBUG_IO |
|
| 63 |
printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
|
|
| 64 |
val & 0xffff); |
|
| 65 |
#endif |
|
| 62 |
|
|
| 63 |
trace_lance_mem_writew(addr, val & 0xffff); |
|
| 66 | 64 |
pcnet_ioport_writew(&d->state, addr, val & 0xffff); |
| 67 | 65 |
} |
| 68 | 66 |
|
| ... | ... | |
| 72 | 70 |
uint32_t val; |
| 73 | 71 |
|
| 74 | 72 |
val = pcnet_ioport_readw(&d->state, addr); |
| 75 |
#ifdef PCNET_DEBUG_IO |
|
| 76 |
printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
|
|
| 77 |
val & 0xffff); |
|
| 78 |
#endif |
|
| 79 |
|
|
| 73 |
trace_lance_mem_readw(addr, val & 0xffff); |
|
| 80 | 74 |
return val & 0xffff; |
| 81 | 75 |
} |
| 82 | 76 |
|
| b/hw/slavio_intctl.c | ||
|---|---|---|
| 25 | 25 |
#include "sun4m.h" |
| 26 | 26 |
#include "monitor.h" |
| 27 | 27 |
#include "sysbus.h" |
| 28 |
#include "trace.h" |
|
| 28 | 29 |
|
| 29 | 30 |
//#define DEBUG_IRQ_COUNT |
| 30 |
//#define DEBUG_IRQ |
|
| 31 |
|
|
| 32 |
#ifdef DEBUG_IRQ |
|
| 33 |
#define DPRINTF(fmt, ...) \ |
|
| 34 |
do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 35 |
#else |
|
| 36 |
#define DPRINTF(fmt, ...) |
|
| 37 |
#endif |
|
| 38 | 31 |
|
| 39 | 32 |
/* |
| 40 | 33 |
* Registers of interrupt controller in sun4m. |
| ... | ... | |
| 97 | 90 |
ret = 0; |
| 98 | 91 |
break; |
| 99 | 92 |
} |
| 100 |
DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
|
|
| 93 |
trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
|
|
| 101 | 94 |
|
| 102 | 95 |
return ret; |
| 103 | 96 |
} |
| ... | ... | |
| 109 | 102 |
uint32_t saddr; |
| 110 | 103 |
|
| 111 | 104 |
saddr = addr >> 2; |
| 112 |
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
|
|
| 105 |
trace_slavio_intctl_mem_writel(s->cpu, addr, val);
|
|
| 113 | 106 |
switch (saddr) {
|
| 114 | 107 |
case 1: // clear pending softints |
| 115 | 108 |
val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; |
| 116 | 109 |
s->intreg_pending &= ~val; |
| 117 | 110 |
slavio_check_interrupts(s->master, 1); |
| 118 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
|
|
| 119 |
s->intreg_pending); |
|
| 111 |
trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); |
|
| 120 | 112 |
break; |
| 121 | 113 |
case 2: // set softint |
| 122 | 114 |
val &= CPU_SOFTIRQ_MASK; |
| 123 | 115 |
s->intreg_pending |= val; |
| 124 | 116 |
slavio_check_interrupts(s->master, 1); |
| 125 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
|
|
| 126 |
s->intreg_pending); |
|
| 117 |
trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); |
|
| 127 | 118 |
break; |
| 128 | 119 |
default: |
| 129 | 120 |
break; |
| ... | ... | |
| 163 | 154 |
ret = 0; |
| 164 | 155 |
break; |
| 165 | 156 |
} |
| 166 |
DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
|
|
| 157 |
trace_slavio_intctlm_mem_readl(addr, ret);
|
|
| 167 | 158 |
|
| 168 | 159 |
return ret; |
| 169 | 160 |
} |
| ... | ... | |
| 175 | 166 |
uint32_t saddr; |
| 176 | 167 |
|
| 177 | 168 |
saddr = addr >> 2; |
| 178 |
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
|
|
| 169 |
trace_slavio_intctlm_mem_writel(addr, val);
|
|
| 179 | 170 |
switch (saddr) {
|
| 180 | 171 |
case 2: // clear (enable) |
| 181 | 172 |
// Force clear unused bits |
| 182 | 173 |
val &= MASTER_IRQ_MASK; |
| 183 | 174 |
s->intregm_disabled &= ~val; |
| 184 |
DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
|
|
| 185 |
s->intregm_disabled); |
|
| 175 |
trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); |
|
| 186 | 176 |
slavio_check_interrupts(s, 1); |
| 187 | 177 |
break; |
| 188 | 178 |
case 3: // set (disable; doesn't affect pending) |
| ... | ... | |
| 190 | 180 |
val &= MASTER_IRQ_MASK; |
| 191 | 181 |
s->intregm_disabled |= val; |
| 192 | 182 |
slavio_check_interrupts(s, 1); |
| 193 |
DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
|
|
| 194 |
s->intregm_disabled); |
|
| 183 |
trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); |
|
| 195 | 184 |
break; |
| 196 | 185 |
case 4: |
| 197 | 186 |
s->target_cpu = val & (MAX_CPUS - 1); |
| 198 | 187 |
slavio_check_interrupts(s, 1); |
| 199 |
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
|
| 188 |
trace_slavio_intctlm_mem_writel_target(s->target_cpu);
|
|
| 200 | 189 |
break; |
| 201 | 190 |
default: |
| 202 | 191 |
break; |
| ... | ... | |
| 264 | 253 |
|
| 265 | 254 |
pending &= ~s->intregm_disabled; |
| 266 | 255 |
|
| 267 |
DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
|
|
| 256 |
trace_slavio_check_interrupts(pending, s->intregm_disabled);
|
|
| 268 | 257 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 269 | 258 |
pil_pending = 0; |
| 270 | 259 |
|
| ... | ... | |
| 327 | 316 |
uint32_t pil = intbit_to_level[irq]; |
| 328 | 317 |
unsigned int i; |
| 329 | 318 |
|
| 330 |
DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
|
|
| 331 |
level); |
|
| 319 |
trace_slavio_set_irq(s->target_cpu, irq, pil, level); |
|
| 332 | 320 |
if (pil > 0) {
|
| 333 | 321 |
if (level) {
|
| 334 | 322 |
#ifdef DEBUG_IRQ_COUNT |
| ... | ... | |
| 356 | 344 |
{
|
| 357 | 345 |
SLAVIO_INTCTLState *s = opaque; |
| 358 | 346 |
|
| 359 |
DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
|
|
| 347 |
trace_slavio_set_timer_irq_cpu(cpu, level);
|
|
| 360 | 348 |
|
| 361 | 349 |
if (level) {
|
| 362 | 350 |
s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; |
| b/hw/slavio_misc.c | ||
|---|---|---|
| 24 | 24 |
|
| 25 | 25 |
#include "sysemu.h" |
| 26 | 26 |
#include "sysbus.h" |
| 27 |
|
|
| 28 |
/* debug misc */ |
|
| 29 |
//#define DEBUG_MISC |
|
| 27 |
#include "trace.h" |
|
| 30 | 28 |
|
| 31 | 29 |
/* |
| 32 | 30 |
* This is the auxio port, chip control and system control part of |
| ... | ... | |
| 36 | 34 |
* This also includes the PMC CPU idle controller. |
| 37 | 35 |
*/ |
| 38 | 36 |
|
| 39 |
#ifdef DEBUG_MISC |
|
| 40 |
#define MISC_DPRINTF(fmt, ...) \ |
|
| 41 |
do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 42 |
#else |
|
| 43 |
#define MISC_DPRINTF(fmt, ...) |
|
| 44 |
#endif |
|
| 45 |
|
|
| 46 | 37 |
typedef struct MiscState {
|
| 47 | 38 |
SysBusDevice busdev; |
| 48 | 39 |
qemu_irq irq; |
| ... | ... | |
| 79 | 70 |
MiscState *s = opaque; |
| 80 | 71 |
|
| 81 | 72 |
if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
|
| 82 |
MISC_DPRINTF("Raise IRQ\n");
|
|
| 73 |
trace_slavio_misc_update_irq_raise();
|
|
| 83 | 74 |
qemu_irq_raise(s->irq); |
| 84 | 75 |
} else {
|
| 85 |
MISC_DPRINTF("Lower IRQ\n");
|
|
| 76 |
trace_slavio_misc_update_irq_lower();
|
|
| 86 | 77 |
qemu_irq_lower(s->irq); |
| 87 | 78 |
} |
| 88 | 79 |
} |
| ... | ... | |
| 99 | 90 |
{
|
| 100 | 91 |
MiscState *s = opaque; |
| 101 | 92 |
|
| 102 |
MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
|
|
| 93 |
trace_slavio_set_power_fail(power_failing, s->config);
|
|
| 103 | 94 |
if (power_failing && (s->config & CFG_PWRINTEN)) {
|
| 104 | 95 |
s->aux2 |= AUX2_PWRFAIL; |
| 105 | 96 |
} else {
|
| ... | ... | |
| 113 | 104 |
{
|
| 114 | 105 |
MiscState *s = opaque; |
| 115 | 106 |
|
| 116 |
MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
|
|
| 107 |
trace_slavio_cfg_mem_writeb(val & 0xff);
|
|
| 117 | 108 |
s->config = val & 0xff; |
| 118 | 109 |
slavio_misc_update_irq(s); |
| 119 | 110 |
} |
| ... | ... | |
| 124 | 115 |
uint32_t ret = 0; |
| 125 | 116 |
|
| 126 | 117 |
ret = s->config; |
| 127 |
MISC_DPRINTF("Read config %2.2x\n", ret);
|
|
| 118 |
trace_slavio_cfg_mem_readb(ret);
|
|
| 128 | 119 |
return ret; |
| 129 | 120 |
} |
| 130 | 121 |
|
| ... | ... | |
| 145 | 136 |
{
|
| 146 | 137 |
MiscState *s = opaque; |
| 147 | 138 |
|
| 148 |
MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
|
|
| 139 |
trace_slavio_diag_mem_writeb(val & 0xff);
|
|
| 149 | 140 |
s->diag = val & 0xff; |
| 150 | 141 |
} |
| 151 | 142 |
|
| ... | ... | |
| 155 | 146 |
uint32_t ret = 0; |
| 156 | 147 |
|
| 157 | 148 |
ret = s->diag; |
| 158 |
MISC_DPRINTF("Read diag %2.2x\n", ret);
|
|
| 149 |
trace_slavio_diag_mem_readb(ret);
|
|
| 159 | 150 |
return ret; |
| 160 | 151 |
} |
| 161 | 152 |
|
| ... | ... | |
| 176 | 167 |
{
|
| 177 | 168 |
MiscState *s = opaque; |
| 178 | 169 |
|
| 179 |
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
|
|
| 170 |
trace_slavio_mdm_mem_writeb(val & 0xff);
|
|
| 180 | 171 |
s->mctrl = val & 0xff; |
| 181 | 172 |
} |
| 182 | 173 |
|
| ... | ... | |
| 186 | 177 |
uint32_t ret = 0; |
| 187 | 178 |
|
| 188 | 179 |
ret = s->mctrl; |
| 189 |
MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
|
| 180 |
trace_slavio_mdm_mem_readb(ret);
|
|
| 190 | 181 |
return ret; |
| 191 | 182 |
} |
| 192 | 183 |
|
| ... | ... | |
| 207 | 198 |
{
|
| 208 | 199 |
MiscState *s = opaque; |
| 209 | 200 |
|
| 210 |
MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
|
|
| 201 |
trace_slavio_aux1_mem_writeb(val & 0xff);
|
|
| 211 | 202 |
if (val & AUX1_TC) {
|
| 212 | 203 |
// Send a pulse to floppy terminal count line |
| 213 | 204 |
if (s->fdc_tc) {
|
| ... | ... | |
| 225 | 216 |
uint32_t ret = 0; |
| 226 | 217 |
|
| 227 | 218 |
ret = s->aux1; |
| 228 |
MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
|
| 229 |
|
|
| 219 |
trace_slavio_aux1_mem_readb(ret); |
|
| 230 | 220 |
return ret; |
| 231 | 221 |
} |
| 232 | 222 |
|
| ... | ... | |
| 248 | 238 |
MiscState *s = opaque; |
| 249 | 239 |
|
| 250 | 240 |
val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
| 251 |
MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
|
| 241 |
trace_slavio_aux2_mem_writeb(val & 0xff);
|
|
| 252 | 242 |
val |= s->aux2 & AUX2_PWRFAIL; |
| 253 | 243 |
if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
| 254 | 244 |
val &= AUX2_PWROFF; |
| ... | ... | |
| 264 | 254 |
uint32_t ret = 0; |
| 265 | 255 |
|
| 266 | 256 |
ret = s->aux2; |
| 267 |
MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
|
| 268 |
|
|
| 257 |
trace_slavio_aux2_mem_readb(ret); |
|
| 269 | 258 |
return ret; |
| 270 | 259 |
} |
| 271 | 260 |
|
| ... | ... | |
| 285 | 274 |
{
|
| 286 | 275 |
APCState *s = opaque; |
| 287 | 276 |
|
| 288 |
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
|
|
| 277 |
trace_apc_mem_writeb(val & 0xff);
|
|
| 289 | 278 |
qemu_irq_raise(s->cpu_halt); |
| 290 | 279 |
} |
| 291 | 280 |
|
| ... | ... | |
| 293 | 282 |
{
|
| 294 | 283 |
uint32_t ret = 0; |
| 295 | 284 |
|
| 296 |
MISC_DPRINTF("Read power management %2.2x\n", ret);
|
|
| 285 |
trace_apc_mem_readb(ret);
|
|
| 297 | 286 |
return ret; |
| 298 | 287 |
} |
| 299 | 288 |
|
| ... | ... | |
| 321 | 310 |
default: |
| 322 | 311 |
break; |
| 323 | 312 |
} |
| 324 |
MISC_DPRINTF("Read system control %08x\n", ret);
|
|
| 313 |
trace_slavio_sysctrl_mem_readl(ret);
|
|
| 325 | 314 |
return ret; |
| 326 | 315 |
} |
| 327 | 316 |
|
| ... | ... | |
| 330 | 319 |
{
|
| 331 | 320 |
MiscState *s = opaque; |
| 332 | 321 |
|
| 333 |
MISC_DPRINTF("Write system control %08x\n", val);
|
|
| 322 |
trace_slavio_sysctrl_mem_writel(val);
|
|
| 334 | 323 |
switch (addr) {
|
| 335 | 324 |
case 0: |
| 336 | 325 |
if (val & SYS_RESET) {
|
| ... | ... | |
| 367 | 356 |
default: |
| 368 | 357 |
break; |
| 369 | 358 |
} |
| 370 |
MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
|
|
| 359 |
trace_slavio_led_mem_readw(ret);
|
|
| 371 | 360 |
return ret; |
| 372 | 361 |
} |
| 373 | 362 |
|
| ... | ... | |
| 376 | 365 |
{
|
| 377 | 366 |
MiscState *s = opaque; |
| 378 | 367 |
|
| 379 |
MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
|
|
| 368 |
trace_slavio_led_mem_readw(val & 0xffff);
|
|
| 380 | 369 |
switch (addr) {
|
| 381 | 370 |
case 0: |
| 382 | 371 |
s->leds = val; |
| b/hw/slavio_timer.c | ||
|---|---|---|
| 25 | 25 |
#include "sun4m.h" |
| 26 | 26 |
#include "qemu-timer.h" |
| 27 | 27 |
#include "sysbus.h" |
| 28 |
|
|
| 29 |
//#define DEBUG_TIMER |
|
| 30 |
|
|
| 31 |
#ifdef DEBUG_TIMER |
|
| 32 |
#define DPRINTF(fmt, ...) \ |
|
| 33 |
do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 34 |
#else |
|
| 35 |
#define DPRINTF(fmt, ...) do {} while (0)
|
|
| 36 |
#endif |
|
| 28 |
#include "trace.h" |
|
| 37 | 29 |
|
| 38 | 30 |
/* |
| 39 | 31 |
* Registers of hardware timer in sun4m. |
| ... | ... | |
| 112 | 104 |
} |
| 113 | 105 |
count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
| 114 | 106 |
|
| 115 |
DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
|
|
| 116 |
t->count); |
|
| 107 |
trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
|
| 117 | 108 |
t->count = count & TIMER_COUNT_MASK32; |
| 118 | 109 |
t->counthigh = count >> 32; |
| 119 | 110 |
} |
| ... | ... | |
| 126 | 117 |
CPUTimerState *t = &s->cputimer[tc->timer_index]; |
| 127 | 118 |
|
| 128 | 119 |
slavio_timer_get_out(t); |
| 129 |
DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
|
|
| 120 |
trace_slavio_timer_irq(t->counthigh, t->count);
|
|
| 130 | 121 |
/* if limit is 0 (free-run), there will be no match */ |
| 131 | 122 |
if (t->limit != 0) {
|
| 132 | 123 |
t->reached = TIMER_REACHED; |
| ... | ... | |
| 188 | 179 |
ret = s->cputimer_mode; |
| 189 | 180 |
break; |
| 190 | 181 |
default: |
| 191 |
DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
|
|
| 182 |
trace_slavio_timer_mem_readl_invalid(addr);
|
|
| 192 | 183 |
ret = 0; |
| 193 | 184 |
break; |
| 194 | 185 |
} |
| 195 |
DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
|
|
| 196 |
|
|
| 186 |
trace_slavio_timer_mem_readl(addr, ret); |
|
| 197 | 187 |
return ret; |
| 198 | 188 |
} |
| 199 | 189 |
|
| ... | ... | |
| 206 | 196 |
unsigned int timer_index = tc->timer_index; |
| 207 | 197 |
CPUTimerState *t = &s->cputimer[timer_index]; |
| 208 | 198 |
|
| 209 |
DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
|
|
| 199 |
trace_slavio_timer_mem_writel(addr, val);
|
|
| 210 | 200 |
saddr = addr >> 2; |
| 211 | 201 |
switch (saddr) {
|
| 212 | 202 |
case TIMER_LIMIT: |
| ... | ... | |
| 218 | 208 |
t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); |
| 219 | 209 |
t->reached = 0; |
| 220 | 210 |
count = ((uint64_t)t->counthigh << 32) | t->count; |
| 221 |
DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
|
|
| 222 |
timer_index, count); |
|
| 211 |
trace_slavio_timer_mem_writel_limit(timer_index, count); |
|
| 223 | 212 |
ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
| 224 | 213 |
} else {
|
| 225 | 214 |
// set limit, reset counter |
| ... | ... | |
| 244 | 233 |
t->count = val & TIMER_MAX_COUNT64; |
| 245 | 234 |
t->reached = 0; |
| 246 | 235 |
count = ((uint64_t)t->counthigh) << 32 | t->count; |
| 247 |
DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
|
|
| 248 |
timer_index, count); |
|
| 236 |
trace_slavio_timer_mem_writel_limit(timer_index, count); |
|
| 249 | 237 |
ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
| 250 |
} else |
|
| 251 |
DPRINTF("not user timer\n");
|
|
| 238 |
} else {
|
|
| 239 |
trace_slavio_timer_mem_writel_counter_invalid(); |
|
| 240 |
} |
|
| 252 | 241 |
break; |
| 253 | 242 |
case TIMER_COUNTER_NORST: |
| 254 | 243 |
// set limit without resetting counter |
| ... | ... | |
| 263 | 252 |
if (slavio_timer_is_user(tc)) {
|
| 264 | 253 |
// start/stop user counter |
| 265 | 254 |
if ((val & 1) && !t->running) {
|
| 266 |
DPRINTF("processor %d user timer started\n",
|
|
| 267 |
timer_index); |
|
| 255 |
trace_slavio_timer_mem_writel_status_start(timer_index); |
|
| 268 | 256 |
ptimer_run(t->timer, 0); |
| 269 | 257 |
t->running = 1; |
| 270 | 258 |
} else if (!(val & 1) && t->running) {
|
| 271 |
DPRINTF("processor %d user timer stopped\n",
|
|
| 272 |
timer_index); |
|
| 259 |
trace_slavio_timer_mem_writel_status_stop(timer_index); |
|
| 273 | 260 |
ptimer_stop(t->timer); |
| 274 | 261 |
t->running = 0; |
| 275 | 262 |
} |
| ... | ... | |
| 298 | 285 |
// set this processors user timer bit in config |
| 299 | 286 |
// register |
| 300 | 287 |
s->cputimer_mode |= processor; |
| 301 |
DPRINTF("processor %d changed from counter to user "
|
|
| 302 |
"timer\n", timer_index); |
|
| 288 |
trace_slavio_timer_mem_writel_mode_user(timer_index); |
|
| 303 | 289 |
} else { // user timer -> counter
|
| 304 | 290 |
// stop the user timer if it is running |
| 305 | 291 |
if (curr_timer->running) {
|
| ... | ... | |
| 311 | 297 |
// clear this processors user timer bit in config |
| 312 | 298 |
// register |
| 313 | 299 |
s->cputimer_mode &= ~processor; |
| 314 |
DPRINTF("processor %d changed from user timer to "
|
|
| 315 |
"counter\n", timer_index); |
|
| 300 |
trace_slavio_timer_mem_writel_mode_counter(timer_index); |
|
| 316 | 301 |
} |
| 317 | 302 |
} |
| 318 | 303 |
} |
| 319 | 304 |
} else {
|
| 320 |
DPRINTF("not system timer\n");
|
|
| 305 |
trace_slavio_timer_mem_writel_mode_invalid();
|
|
| 321 | 306 |
} |
| 322 | 307 |
break; |
| 323 | 308 |
default: |
| 324 |
DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
|
|
| 309 |
trace_slavio_timer_mem_writel_invalid(addr);
|
|
| 325 | 310 |
break; |
| 326 | 311 |
} |
| 327 | 312 |
} |
| b/hw/sparc32_dma.c | ||
|---|---|---|
| 29 | 29 |
#include "sparc32_dma.h" |
| 30 | 30 |
#include "sun4m.h" |
| 31 | 31 |
#include "sysbus.h" |
| 32 |
|
|
| 33 |
/* debug DMA */ |
|
| 34 |
//#define DEBUG_DMA |
|
| 32 |
#include "trace.h" |
|
| 35 | 33 |
|
| 36 | 34 |
/* |
| 37 | 35 |
* This is the DMA controller part of chip STP2000 (Master I/O), also |
| ... | ... | |
| 41 | 39 |
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt |
| 42 | 40 |
*/ |
| 43 | 41 |
|
| 44 |
#ifdef DEBUG_DMA |
|
| 45 |
#define DPRINTF(fmt, ...) \ |
|
| 46 |
do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 47 |
#else |
|
| 48 |
#define DPRINTF(fmt, ...) |
|
| 49 |
#endif |
|
| 50 |
|
|
| 51 | 42 |
#define DMA_REGS 4 |
| 52 | 43 |
#define DMA_SIZE (4 * sizeof(uint32_t)) |
| 53 | 44 |
/* We need the mask, because one instance of the device is not page |
| ... | ... | |
| 88 | 79 |
DMAState *s = opaque; |
| 89 | 80 |
int i; |
| 90 | 81 |
|
| 91 |
DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
|
|
| 92 |
s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
|
| 93 | 82 |
addr |= s->dmaregs[3]; |
| 83 |
trace_ledma_memory_read(addr); |
|
| 94 | 84 |
if (do_bswap) {
|
| 95 | 85 |
sparc_iommu_memory_read(s->iommu, addr, buf, len); |
| 96 | 86 |
} else {
|
| ... | ... | |
| 110 | 100 |
int l, i; |
| 111 | 101 |
uint16_t tmp_buf[32]; |
| 112 | 102 |
|
| 113 |
DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
|
|
| 114 |
s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
|
| 115 | 103 |
addr |= s->dmaregs[3]; |
| 104 |
trace_ledma_memory_write(addr); |
|
| 116 | 105 |
if (do_bswap) {
|
| 117 | 106 |
sparc_iommu_memory_write(s->iommu, addr, buf, len); |
| 118 | 107 |
} else {
|
| ... | ... | |
| 139 | 128 |
if (level) {
|
| 140 | 129 |
s->dmaregs[0] |= DMA_INTR; |
| 141 | 130 |
if (s->dmaregs[0] & DMA_INTREN) {
|
| 142 |
DPRINTF("Raise IRQ\n");
|
|
| 131 |
trace_sparc32_dma_set_irq_raise();
|
|
| 143 | 132 |
qemu_irq_raise(s->irq); |
| 144 | 133 |
} |
| 145 | 134 |
} else {
|
| 146 | 135 |
if (s->dmaregs[0] & DMA_INTR) {
|
| 147 | 136 |
s->dmaregs[0] &= ~DMA_INTR; |
| 148 | 137 |
if (s->dmaregs[0] & DMA_INTREN) {
|
| 149 |
DPRINTF("Lower IRQ\n");
|
|
| 138 |
trace_sparc32_dma_set_irq_lower();
|
|
| 150 | 139 |
qemu_irq_lower(s->irq); |
| 151 | 140 |
} |
| 152 | 141 |
} |
| ... | ... | |
| 157 | 146 |
{
|
| 158 | 147 |
DMAState *s = opaque; |
| 159 | 148 |
|
| 160 |
DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
|
|
| 161 |
s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
|
| 149 |
trace_espdma_memory_read(s->dmaregs[1]); |
|
| 162 | 150 |
sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); |
| 163 | 151 |
s->dmaregs[1] += len; |
| 164 | 152 |
} |
| ... | ... | |
| 167 | 155 |
{
|
| 168 | 156 |
DMAState *s = opaque; |
| 169 | 157 |
|
| 170 |
DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
|
|
| 171 |
s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
|
| 158 |
trace_espdma_memory_write(s->dmaregs[1]); |
|
| 172 | 159 |
sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); |
| 173 | 160 |
s->dmaregs[1] += len; |
| 174 | 161 |
} |
| ... | ... | |
| 179 | 166 |
uint32_t saddr; |
| 180 | 167 |
|
| 181 | 168 |
saddr = (addr & DMA_MASK) >> 2; |
| 182 |
DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
|
|
| 183 |
s->dmaregs[saddr]); |
|
| 184 |
|
|
| 169 |
trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); |
|
| 185 | 170 |
return s->dmaregs[saddr]; |
| 186 | 171 |
} |
| 187 | 172 |
|
| ... | ... | |
| 191 | 176 |
uint32_t saddr; |
| 192 | 177 |
|
| 193 | 178 |
saddr = (addr & DMA_MASK) >> 2; |
| 194 |
DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
|
|
| 195 |
s->dmaregs[saddr], val); |
|
| 179 |
trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); |
|
| 196 | 180 |
switch (saddr) {
|
| 197 | 181 |
case 0: |
| 198 | 182 |
if (val & DMA_INTREN) {
|
| 199 | 183 |
if (s->dmaregs[0] & DMA_INTR) {
|
| 200 |
DPRINTF("Raise IRQ\n");
|
|
| 184 |
trace_sparc32_dma_set_irq_raise();
|
|
| 201 | 185 |
qemu_irq_raise(s->irq); |
| 202 | 186 |
} |
| 203 | 187 |
} else {
|
| 204 | 188 |
if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
|
| 205 |
DPRINTF("Lower IRQ\n");
|
|
| 189 |
trace_sparc32_dma_set_irq_lower();
|
|
| 206 | 190 |
qemu_irq_lower(s->irq); |
| 207 | 191 |
} |
| 208 | 192 |
} |
| ... | ... | |
| 215 | 199 |
val = DMA_DRAIN_FIFO; |
| 216 | 200 |
|
| 217 | 201 |
if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
|
| 218 |
DPRINTF("Raise DMA enable\n");
|
|
| 202 |
trace_sparc32_dma_enable_raise();
|
|
| 219 | 203 |
qemu_irq_raise(s->gpio[GPIO_DMA]); |
| 220 | 204 |
} else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
|
| 221 |
DPRINTF("Lower DMA enable\n");
|
|
| 205 |
trace_sparc32_dma_enable_lower();
|
|
| 222 | 206 |
qemu_irq_lower(s->gpio[GPIO_DMA]); |
| 223 | 207 |
} |
| 224 | 208 |
|
| b/hw/sun4m.c | ||
|---|---|---|
| 41 | 41 |
#include "loader.h" |
| 42 | 42 |
#include "elf.h" |
| 43 | 43 |
#include "blockdev.h" |
| 44 |
|
|
| 45 |
//#define DEBUG_IRQ |
|
| 44 |
#include "trace.h" |
|
| 46 | 45 |
|
| 47 | 46 |
/* |
| 48 | 47 |
* Sun4m architecture was used in the following machines: |
| ... | ... | |
| 72 | 71 |
* See for example: http://www.sunhelp.org/faq/sunref1.html |
| 73 | 72 |
*/ |
| 74 | 73 |
|
| 75 |
#ifdef DEBUG_IRQ |
|
| 76 |
#define DPRINTF(fmt, ...) \ |
|
| 77 |
do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 78 |
#else |
|
| 79 |
#define DPRINTF(fmt, ...) |
|
| 80 |
#endif |
|
| 81 |
|
|
| 82 | 74 |
#define KERNEL_LOAD_ADDR 0x00004000 |
| 83 | 75 |
#define CMDLINE_ADDR 0x007ff000 |
| 84 | 76 |
#define INITRD_LOAD_ADDR 0x00800000 |
| ... | ... | |
| 248 | 240 |
|
| 249 | 241 |
env->interrupt_index = TT_EXTINT | i; |
| 250 | 242 |
if (old_interrupt != env->interrupt_index) {
|
| 251 |
DPRINTF("Set CPU IRQ %d\n", i);
|
|
| 243 |
trace_sun4m_cpu_interrupt(i);
|
|
| 252 | 244 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 253 | 245 |
} |
| 254 | 246 |
break; |
| 255 | 247 |
} |
| 256 | 248 |
} |
| 257 | 249 |
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
|
| 258 |
DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
|
|
| 250 |
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
|
|
| 259 | 251 |
env->interrupt_index = 0; |
| 260 | 252 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 261 | 253 |
} |
| ... | ... | |
| 266 | 258 |
CPUState *env = opaque; |
| 267 | 259 |
|
| 268 | 260 |
if (level) {
|
| 269 |
DPRINTF("Raise CPU IRQ %d\n", irq);
|
|
| 261 |
trace_sun4m_cpu_set_irq_raise(irq);
|
|
| 270 | 262 |
env->halted = 0; |
| 271 | 263 |
env->pil_in |= 1 << irq; |
| 272 | 264 |
cpu_check_irqs(env); |
| 273 | 265 |
} else {
|
| 274 |
DPRINTF("Lower CPU IRQ %d\n", irq);
|
|
| 266 |
trace_sun4m_cpu_set_irq_lower(irq);
|
|
| 275 | 267 |
env->pil_in &= ~(1 << irq); |
| 276 | 268 |
cpu_check_irqs(env); |
| 277 | 269 |
} |
| b/hw/sun4m_iommu.c | ||
|---|---|---|
| 24 | 24 |
|
| 25 | 25 |
#include "sun4m.h" |
| 26 | 26 |
#include "sysbus.h" |
| 27 |
|
|
| 28 |
/* debug iommu */ |
|
| 29 |
//#define DEBUG_IOMMU |
|
| 30 |
|
|
| 31 |
#ifdef DEBUG_IOMMU |
|
| 32 |
#define DPRINTF(fmt, ...) \ |
|
| 33 |
do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
|
|
| 34 |
#else |
|
| 35 |
#define DPRINTF(fmt, ...) |
|
| 36 |
#endif |
|
| 27 |
#include "trace.h" |
|
| 37 | 28 |
|
| 38 | 29 |
/* |
| 39 | 30 |
* I/O MMU used by Sun4m systems |
| ... | ... | |
| 160 | 151 |
qemu_irq_lower(s->irq); |
| 161 | 152 |
break; |
| 162 | 153 |
} |
| 163 |
DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
|
|
| 154 |
trace_sun4m_iommu_mem_readl(saddr, ret);
|
|
| 164 | 155 |
return ret; |
| 165 | 156 |
} |
| 166 | 157 |
|
| ... | ... | |
| 171 | 162 |
target_phys_addr_t saddr; |
| 172 | 163 |
|
| 173 | 164 |
saddr = addr >> 2; |
| 174 |
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
|
|
| 165 |
trace_sun4m_iommu_mem_writel(saddr, val);
|
|
| 175 | 166 |
switch (saddr) {
|
| 176 | 167 |
case IOMMU_CTRL: |
| 177 | 168 |
switch (val & IOMMU_CTRL_RNGE) {
|
| ... | ... | |
| 201 | 192 |
s->iostart = 0xffffffff80000000ULL; |
| 202 | 193 |
break; |
| 203 | 194 |
} |
| 204 |
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
|
|
| 195 |
trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
|
|
| 205 | 196 |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
| 206 | 197 |
break; |
| 207 | 198 |
case IOMMU_BASE: |
| 208 | 199 |
s->regs[saddr] = val & IOMMU_BASE_MASK; |
| 209 | 200 |
break; |
| 210 | 201 |
case IOMMU_TLBFLUSH: |
| 211 |
DPRINTF("tlb flush %x\n", val);
|
|
| 202 |
trace_sun4m_iommu_mem_writel_tlbflush(val);
|
|
| 212 | 203 |
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
| 213 | 204 |
break; |
| 214 | 205 |
case IOMMU_PGFLUSH: |
| 215 |
DPRINTF("page flush %x\n", val);
|
|
| 206 |
trace_sun4m_iommu_mem_writel_pgflush(val);
|
|
| 216 | 207 |
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
| 217 | 208 |
break; |
| 218 | 209 |
case IOMMU_AFAR: |
| ... | ... | |
| 262 | 253 |
{
|
| 263 | 254 |
uint32_t ret; |
| 264 | 255 |
target_phys_addr_t iopte; |
| 265 |
#ifdef DEBUG_IOMMU |
|
| 266 | 256 |
target_phys_addr_t pa = addr; |
| 267 |
#endif |
|
| 268 | 257 |
|
| 269 | 258 |
iopte = s->regs[IOMMU_BASE] << 4; |
| 270 | 259 |
addr &= ~s->iostart; |
| 271 | 260 |
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
| 272 | 261 |
cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); |
| 273 | 262 |
tswap32s(&ret); |
| 274 |
DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
|
|
| 275 |
", *pte = %x\n", pa, iopte, ret); |
|
| 276 |
|
|
| 263 |
trace_sun4m_iommu_page_get_flags(pa, iopte, ret); |
|
| 277 | 264 |
return ret; |
| 278 | 265 |
} |
| 279 | 266 |
|
| ... | ... | |
| 283 | 270 |
target_phys_addr_t pa; |
| 284 | 271 |
|
| 285 | 272 |
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
| 286 |
DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
|
|
| 287 |
" (iopte = %x)\n", addr, pa, pte); |
|
| 288 |
|
|
| 273 |
trace_sun4m_iommu_translate_pa(addr, pa, pte); |
|
| 289 | 274 |
return pa; |
| 290 | 275 |
} |
| 291 | 276 |
|
| 292 | 277 |
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
| 293 | 278 |
int is_write) |
| 294 | 279 |
{
|
| 295 |
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
|
|
| 280 |
trace_sun4m_iommu_bad_addr(addr);
|
|
| 296 | 281 |
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
| 297 | 282 |
IOMMU_AFSR_FAV; |
| 298 | 283 |
if (!is_write) |
| b/trace-events | ||
|---|---|---|
| 81 | 81 |
disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" |
| 82 | 82 |
disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" |
| 83 | 83 |
disable apic_set_irq(int apic_irq_delivered) "coalescing %d" |
| 84 |
|
|
| 85 |
# hw/cs4231.c |
|
| 86 |
disable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x" |
|
| 87 |
disable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x" |
|
| 88 |
disable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x" |
|
| 89 |
disable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x" |
|
| 90 |
|
|
| 91 |
# hw/eccmemctl.c |
|
| 92 |
disable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x" |
|
| 93 |
disable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x" |
|
| 94 |
disable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x" |
|
| 95 |
disable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x" |
|
| 96 |
disable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x" |
|
| 97 |
disable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x" |
|
| 98 |
disable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x" |
|
| 99 |
disable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x" |
|
| 100 |
disable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x" |
|
| 101 |
disable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x" |
|
| 102 |
disable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x" |
|
| 103 |
disable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x" |
|
| 104 |
disable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x" |
|
| 105 |
disable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x" |
|
| 106 |
disable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x" |
|
| 107 |
disable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x" |
|
| 108 |
disable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x" |
|
| 109 |
disable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x" |
|
| 110 |
|
|
| 111 |
# hw/lance.c |
|
| 112 |
disable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x" |
|
| 113 |
disable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x" |
|
| 114 |
|
|
| 115 |
# hw/slavio_intctl.c |
|
| 116 |
disable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" |
|
| 117 |
disable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" |
|
| 118 |
disable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" |
|
| 119 |
disable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" |
|
| 120 |
disable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" |
|
| 121 |
disable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" |
|
| 122 |
disable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" |
|
| 123 |
disable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" |
|
| 124 |
disable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" |
|
| 125 |
disable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" |
|
| 126 |
disable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" |
|
| 127 |
disable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" |
|
| 128 |
|
|
| 129 |
# hw/slavio_misc.c |
|
| 130 |
disable slavio_misc_update_irq_raise(void) "Raise IRQ" |
|
| 131 |
disable slavio_misc_update_irq_lower(void) "Lower IRQ" |
|
| 132 |
disable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" |
|
| 133 |
disable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x" |
|
| 134 |
disable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x" |
|
| 135 |
disable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x" |
|
| 136 |
disable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x" |
|
| 137 |
disable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x" |
|
| 138 |
disable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x" |
|
| 139 |
disable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x" |
|
| 140 |
disable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x" |
|
| 141 |
disable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x" |
|
| 142 |
disable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x" |
|
| 143 |
disable apc_mem_writeb(uint32_t val) "Write power management %02x" |
|
| 144 |
disable apc_mem_readb(uint32_t ret) "Read power management %02x" |
|
| 145 |
disable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x" |
|
| 146 |
disable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x" |
|
| 147 |
disable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x" |
|
| 148 |
disable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x" |
|
| 149 |
|
|
| 150 |
# hw/slavio_timer.c |
|
| 151 |
disable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" |
|
| 152 |
disable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" |
|
| 153 |
disable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64"" |
|
| 154 |
disable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" |
|
| 155 |
disable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" |
|
| 156 |
disable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64"" |
|
| 157 |
disable slavio_timer_mem_writel_counter_invalid(void) "not user timer" |
|
| 158 |
disable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" |
|
| 159 |
disable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" |
|
| 160 |
disable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" |
|
| 161 |
disable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" |
|
| 162 |
disable slavio_timer_mem_writel_mode_invalid(void) "not system timer" |
|
| 163 |
disable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64"" |
|
| 164 |
|
|
| 165 |
# hw/sparc32_dma.c |
|
| 166 |
disable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64"" |
|
| 167 |
disable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64"" |
|
| 168 |
disable sparc32_dma_set_irq_raise(void) "Raise IRQ" |
|
| 169 |
disable sparc32_dma_set_irq_lower(void) "Lower IRQ" |
|
| 170 |
disable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" |
|
| 171 |
disable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" |
|
| 172 |
disable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" |
|
| 173 |
disable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" |
|
| 174 |
disable sparc32_dma_enable_raise(void) "Raise DMA enable" |
|
| 175 |
disable sparc32_dma_enable_lower(void) "Lower DMA enable" |
|
| 176 |
|
|
| 177 |
# hw/sun4m.c |
|
| 178 |
disable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" |
|
| 179 |
disable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" |
|
| 180 |
disable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" |
|
| 181 |
disable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" |
|
| 182 |
|
|
| 183 |
# hw/sun4m_iommu.c |
|
| 184 |
disable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" |
|
| 185 |
disable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" |
|
| 186 |
disable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64"" |
|
| 187 |
disable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" |
|
| 188 |
disable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" |
|
| 189 |
disable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" |
|
| 190 |
disable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" |
|
| 191 |
disable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64"" |
|
Also available in: Unified diff