Revision 97bf4851 hw/eccmemctl.c
| b/hw/eccmemctl.c | ||
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*/ |
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#include "sysbus.h" |
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//#define DEBUG_ECC |
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#ifdef DEBUG_ECC |
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#define DPRINTF(fmt, ...) \ |
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do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
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#else |
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#define DPRINTF(fmt, ...) |
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#endif |
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#include "trace.h" |
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/* There are 3 versions of this chip used in SMP sun4m systems: |
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* MCC (version 0, implementation 0) SS-600MP |
| ... | ... | |
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s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
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else if (s->version == ECC_SMC) |
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s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
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DPRINTF("Write memory enable %08x\n", val);
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trace_ecc_mem_writel_mer(val);
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break; |
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case ECC_MDR: |
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s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
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DPRINTF("Write memory delay %08x\n", val);
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trace_ecc_mem_writel_mdr(val);
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break; |
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case ECC_MFSR: |
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s->regs[ECC_MFSR] = val; |
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qemu_irq_lower(s->irq); |
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DPRINTF("Write memory fault status %08x\n", val);
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trace_ecc_mem_writel_mfsr(val);
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break; |
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case ECC_VCR: |
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s->regs[ECC_VCR] = val; |
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DPRINTF("Write slot configuration %08x\n", val);
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trace_ecc_mem_writel_vcr(val);
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break; |
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case ECC_DR: |
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s->regs[ECC_DR] = val; |
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DPRINTF("Write diagnostic %08x\n", val);
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trace_ecc_mem_writel_dr(val);
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break; |
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case ECC_ECR0: |
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s->regs[ECC_ECR0] = val; |
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DPRINTF("Write event count 1 %08x\n", val);
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trace_ecc_mem_writel_ecr0(val);
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break; |
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case ECC_ECR1: |
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s->regs[ECC_ECR0] = val; |
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DPRINTF("Write event count 2 %08x\n", val);
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trace_ecc_mem_writel_ecr1(val);
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break; |
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} |
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} |
| ... | ... | |
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switch (addr >> 2) {
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case ECC_MER: |
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ret = s->regs[ECC_MER]; |
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DPRINTF("Read memory enable %08x\n", ret);
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trace_ecc_mem_readl_mer(ret);
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break; |
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case ECC_MDR: |
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ret = s->regs[ECC_MDR]; |
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DPRINTF("Read memory delay %08x\n", ret);
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trace_ecc_mem_readl_mdr(ret);
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break; |
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case ECC_MFSR: |
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ret = s->regs[ECC_MFSR]; |
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DPRINTF("Read memory fault status %08x\n", ret);
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trace_ecc_mem_readl_mfsr(ret);
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break; |
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case ECC_VCR: |
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ret = s->regs[ECC_VCR]; |
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DPRINTF("Read slot configuration %08x\n", ret);
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trace_ecc_mem_readl_vcr(ret);
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break; |
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case ECC_MFAR0: |
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ret = s->regs[ECC_MFAR0]; |
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DPRINTF("Read memory fault address 0 %08x\n", ret);
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trace_ecc_mem_readl_mfar0(ret);
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break; |
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case ECC_MFAR1: |
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ret = s->regs[ECC_MFAR1]; |
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DPRINTF("Read memory fault address 1 %08x\n", ret);
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trace_ecc_mem_readl_mfar1(ret);
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break; |
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case ECC_DR: |
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ret = s->regs[ECC_DR]; |
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DPRINTF("Read diagnostic %08x\n", ret);
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trace_ecc_mem_readl_dr(ret);
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break; |
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case ECC_ECR0: |
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ret = s->regs[ECC_ECR0]; |
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DPRINTF("Read event count 1 %08x\n", ret);
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trace_ecc_mem_readl_ecr0(ret);
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break; |
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case ECC_ECR1: |
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ret = s->regs[ECC_ECR0]; |
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DPRINTF("Read event count 2 %08x\n", ret);
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trace_ecc_mem_readl_ecr1(ret);
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break; |
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} |
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return ret; |
| ... | ... | |
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{
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ECCState *s = opaque; |
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DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
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trace_ecc_diag_mem_writeb(addr, val);
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s->diag[addr & ECC_DIAG_MASK] = val; |
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} |
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| ... | ... | |
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ECCState *s = opaque; |
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uint32_t ret = s->diag[(int)addr]; |
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DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
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trace_ecc_diag_mem_readb(addr, ret);
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return ret; |
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} |
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