Revision 97bf4851 hw/slavio_timer.c
| b/hw/slavio_timer.c | ||
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#include "sun4m.h" |
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#include "qemu-timer.h" |
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#include "sysbus.h" |
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//#define DEBUG_TIMER |
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#ifdef DEBUG_TIMER |
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#define DPRINTF(fmt, ...) \ |
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
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#else |
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif |
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#include "trace.h" |
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/* |
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* Registers of hardware timer in sun4m. |
| ... | ... | |
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} |
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count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
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DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
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t->count); |
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trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
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t->count = count & TIMER_COUNT_MASK32; |
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t->counthigh = count >> 32; |
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} |
| ... | ... | |
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CPUTimerState *t = &s->cputimer[tc->timer_index]; |
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slavio_timer_get_out(t); |
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DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
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trace_slavio_timer_irq(t->counthigh, t->count);
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/* if limit is 0 (free-run), there will be no match */ |
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if (t->limit != 0) {
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t->reached = TIMER_REACHED; |
| ... | ... | |
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ret = s->cputimer_mode; |
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break; |
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default: |
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DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
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trace_slavio_timer_mem_readl_invalid(addr);
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ret = 0; |
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break; |
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} |
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DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
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trace_slavio_timer_mem_readl(addr, ret); |
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return ret; |
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} |
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|
| ... | ... | |
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unsigned int timer_index = tc->timer_index; |
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CPUTimerState *t = &s->cputimer[timer_index]; |
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DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
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trace_slavio_timer_mem_writel(addr, val);
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saddr = addr >> 2; |
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switch (saddr) {
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case TIMER_LIMIT: |
| ... | ... | |
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t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); |
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t->reached = 0; |
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count = ((uint64_t)t->counthigh << 32) | t->count; |
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DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
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timer_index, count); |
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trace_slavio_timer_mem_writel_limit(timer_index, count); |
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ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
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} else {
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// set limit, reset counter |
| ... | ... | |
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t->count = val & TIMER_MAX_COUNT64; |
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t->reached = 0; |
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count = ((uint64_t)t->counthigh) << 32 | t->count; |
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DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
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timer_index, count); |
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trace_slavio_timer_mem_writel_limit(timer_index, count); |
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ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
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} else |
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DPRINTF("not user timer\n");
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} else {
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trace_slavio_timer_mem_writel_counter_invalid(); |
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} |
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break; |
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case TIMER_COUNTER_NORST: |
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// set limit without resetting counter |
| ... | ... | |
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if (slavio_timer_is_user(tc)) {
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// start/stop user counter |
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if ((val & 1) && !t->running) {
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DPRINTF("processor %d user timer started\n",
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timer_index); |
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trace_slavio_timer_mem_writel_status_start(timer_index); |
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ptimer_run(t->timer, 0); |
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t->running = 1; |
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} else if (!(val & 1) && t->running) {
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DPRINTF("processor %d user timer stopped\n",
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timer_index); |
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trace_slavio_timer_mem_writel_status_stop(timer_index); |
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ptimer_stop(t->timer); |
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t->running = 0; |
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} |
| ... | ... | |
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// set this processors user timer bit in config |
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// register |
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s->cputimer_mode |= processor; |
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DPRINTF("processor %d changed from counter to user "
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"timer\n", timer_index); |
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trace_slavio_timer_mem_writel_mode_user(timer_index); |
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} else { // user timer -> counter
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// stop the user timer if it is running |
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if (curr_timer->running) {
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| ... | ... | |
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// clear this processors user timer bit in config |
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// register |
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s->cputimer_mode &= ~processor; |
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DPRINTF("processor %d changed from user timer to "
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"counter\n", timer_index); |
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trace_slavio_timer_mem_writel_mode_counter(timer_index); |
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} |
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} |
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} |
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} else {
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DPRINTF("not system timer\n");
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trace_slavio_timer_mem_writel_mode_invalid();
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} |
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break; |
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default: |
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DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
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trace_slavio_timer_mem_writel_invalid(addr);
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break; |
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} |
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} |
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