Revision 97bf4851 hw/sparc32_dma.c
| b/hw/sparc32_dma.c | ||
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#include "sparc32_dma.h" |
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#include "sun4m.h" |
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#include "sysbus.h" |
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/* debug DMA */ |
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//#define DEBUG_DMA |
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#include "trace.h" |
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/* |
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* This is the DMA controller part of chip STP2000 (Master I/O), also |
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt |
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*/ |
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#ifdef DEBUG_DMA |
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#define DPRINTF(fmt, ...) \ |
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do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
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#else |
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#define DPRINTF(fmt, ...) |
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#endif |
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#define DMA_REGS 4 |
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#define DMA_SIZE (4 * sizeof(uint32_t)) |
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/* We need the mask, because one instance of the device is not page |
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DMAState *s = opaque; |
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int i; |
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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addr |= s->dmaregs[3]; |
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trace_ledma_memory_read(addr); |
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if (do_bswap) {
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sparc_iommu_memory_read(s->iommu, addr, buf, len); |
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} else {
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int l, i; |
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uint16_t tmp_buf[32]; |
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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addr |= s->dmaregs[3]; |
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trace_ledma_memory_write(addr); |
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if (do_bswap) {
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sparc_iommu_memory_write(s->iommu, addr, buf, len); |
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} else {
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if (level) {
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s->dmaregs[0] |= DMA_INTR; |
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if (s->dmaregs[0] & DMA_INTREN) {
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DPRINTF("Raise IRQ\n");
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trace_sparc32_dma_set_irq_raise();
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qemu_irq_raise(s->irq); |
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} |
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} else {
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if (s->dmaregs[0] & DMA_INTR) {
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s->dmaregs[0] &= ~DMA_INTR; |
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if (s->dmaregs[0] & DMA_INTREN) {
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DPRINTF("Lower IRQ\n");
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trace_sparc32_dma_set_irq_lower();
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qemu_irq_lower(s->irq); |
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} |
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} |
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{
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DMAState *s = opaque; |
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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trace_espdma_memory_read(s->dmaregs[1]); |
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sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[1] += len; |
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} |
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{
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DMAState *s = opaque; |
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
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trace_espdma_memory_write(s->dmaregs[1]); |
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sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); |
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s->dmaregs[1] += len; |
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} |
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uint32_t saddr; |
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saddr = (addr & DMA_MASK) >> 2; |
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DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
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s->dmaregs[saddr]); |
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trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); |
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return s->dmaregs[saddr]; |
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} |
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uint32_t saddr; |
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saddr = (addr & DMA_MASK) >> 2; |
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DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
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s->dmaregs[saddr], val); |
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trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); |
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switch (saddr) {
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case 0: |
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if (val & DMA_INTREN) {
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if (s->dmaregs[0] & DMA_INTR) {
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DPRINTF("Raise IRQ\n");
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trace_sparc32_dma_set_irq_raise();
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qemu_irq_raise(s->irq); |
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} |
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} else {
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if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
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DPRINTF("Lower IRQ\n");
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trace_sparc32_dma_set_irq_lower();
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qemu_irq_lower(s->irq); |
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} |
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} |
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val = DMA_DRAIN_FIFO; |
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if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
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DPRINTF("Raise DMA enable\n");
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trace_sparc32_dma_enable_raise();
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qemu_irq_raise(s->gpio[GPIO_DMA]); |
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} else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
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DPRINTF("Lower DMA enable\n");
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trace_sparc32_dma_enable_lower();
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qemu_irq_lower(s->gpio[GPIO_DMA]); |
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} |
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