Revision 97bf4851 hw/sun4m_iommu.c

b/hw/sun4m_iommu.c
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#include "sun4m.h"
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#include "sysbus.h"
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/* debug iommu */
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//#define DEBUG_IOMMU
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#ifdef DEBUG_IOMMU
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#define DPRINTF(fmt, ...)                                       \
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    do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#include "trace.h"
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/*
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 * I/O MMU used by Sun4m systems
......
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        qemu_irq_lower(s->irq);
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        break;
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    }
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    DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
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    trace_sun4m_iommu_mem_readl(saddr, ret);
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    return ret;
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}
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......
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    target_phys_addr_t saddr;
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    saddr = addr >> 2;
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    DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
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    trace_sun4m_iommu_mem_writel(saddr, val);
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    switch (saddr) {
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    case IOMMU_CTRL:
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        switch (val & IOMMU_CTRL_RNGE) {
......
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            s->iostart = 0xffffffff80000000ULL;
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            break;
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        }
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        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
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        trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
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        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
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        break;
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    case IOMMU_BASE:
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        s->regs[saddr] = val & IOMMU_BASE_MASK;
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        break;
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    case IOMMU_TLBFLUSH:
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        DPRINTF("tlb flush %x\n", val);
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        trace_sun4m_iommu_mem_writel_tlbflush(val);
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        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
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        break;
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    case IOMMU_PGFLUSH:
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        DPRINTF("page flush %x\n", val);
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        trace_sun4m_iommu_mem_writel_pgflush(val);
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        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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        break;
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    case IOMMU_AFAR:
......
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{
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    uint32_t ret;
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    target_phys_addr_t iopte;
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#ifdef DEBUG_IOMMU
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    target_phys_addr_t pa = addr;
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#endif
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    iopte = s->regs[IOMMU_BASE] << 4;
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    addr &= ~s->iostart;
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    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
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    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
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    tswap32s(&ret);
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    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
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            ", *pte = %x\n", pa, iopte, ret);
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    trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
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    return ret;
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}
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......
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    target_phys_addr_t pa;
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    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
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    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
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            " (iopte = %x)\n", addr, pa, pte);
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    trace_sun4m_iommu_translate_pa(addr, pa, pte);
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    return pa;
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}
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static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
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                           int is_write)
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{
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    DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
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    trace_sun4m_iommu_bad_addr(addr);
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    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
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        IOMMU_AFSR_FAV;
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    if (!is_write)

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