Revision 983fe826 target-arm/helper.c

b/target-arm/helper.c
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#include "helpers.h"
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#include "qemu-common.h"
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#include "host-utils.h"
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#include "hw/loader.h"
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static uint32_t cortexa9_cp15_c0_c1[8] =
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{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
......
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#else
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    /* SVC mode with interrupts disabled.  */
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    env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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    env->regs[15] = 0;
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    /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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       clear at reset.  */
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    if (IS_M(env))
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       clear at reset.  Initial SP and PC are loaded from ROM.  */
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    if (IS_M(env)) {
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        uint32_t pc;
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        uint8_t *rom;
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        env->uncached_cpsr &= ~CPSR_I;
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        rom = rom_ptr(0);
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        if (rom) {
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            /* We should really use ldl_phys here, in case the guest
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               modified flash and reset itself.  However images
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               loaded via -kenrel have not been copied yet, so load the
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               values directly from there.  */
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            env->regs[13] = ldl_p(rom);
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            pc = ldl_p(rom + 4);
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            env->thumb = pc & 1;
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            env->regs[15] = pc & ~1;
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        }
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    }
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    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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    env->cp15.c2_base_mask = 0xffffc000u;
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#endif
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    env->regs[15] = 0;
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    tlb_flush(env, 1);
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}
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......
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    type = env->regs[15];
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    if (env->v7m.exception != 0)
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        armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
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        armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
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    /* Switch to the target stack.  */
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    switch_v7m_sp(env, (type & 4) != 0);
......
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       one we're raising.  */
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    switch (env->exception_index) {
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    case EXCP_UDEF:
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        armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
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        return;
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    case EXCP_SWI:
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        env->regs[15] += 2;
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        armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
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        return;
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    case EXCP_PREFETCH_ABORT:
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    case EXCP_DATA_ABORT:
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        armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
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        return;
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    case EXCP_BKPT:
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        if (semihosting_enabled) {
......
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                return;
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            }
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        }
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        armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
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        return;
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    case EXCP_IRQ:
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        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
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        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
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        break;
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    case EXCP_EXCEPTION_EXIT:
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        do_v7m_exception_exit(env);

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