Revision 986a2998
| b/gdbstub.c | ||
|---|---|---|
| 489 | 489 |
return put_packet_binary(s, buf, strlen(buf)); |
| 490 | 490 |
} |
| 491 | 491 |
|
| 492 |
/* The GDB remote protocol transfers values in target byte order. This means |
|
| 493 |
we can use the raw memory access routines to access the value buffer. |
|
| 494 |
Conveniently, these also handle the case where the buffer is mis-aligned. |
|
| 495 |
*/ |
|
| 496 |
#define GET_REG8(val) do { \
|
|
| 497 |
stb_p(mem_buf, val); \ |
|
| 498 |
return 1; \ |
|
| 499 |
} while(0) |
|
| 500 |
#define GET_REG16(val) do { \
|
|
| 501 |
stw_p(mem_buf, val); \ |
|
| 502 |
return 2; \ |
|
| 503 |
} while(0) |
|
| 504 |
#define GET_REG32(val) do { \
|
|
| 505 |
stl_p(mem_buf, val); \ |
|
| 506 |
return 4; \ |
|
| 507 |
} while(0) |
|
| 508 |
#define GET_REG64(val) do { \
|
|
| 509 |
stq_p(mem_buf, val); \ |
|
| 510 |
return 8; \ |
|
| 511 |
} while(0) |
|
| 512 |
|
|
| 513 |
#if TARGET_LONG_BITS == 64 |
|
| 514 |
#define GET_REGL(val) GET_REG64(val) |
|
| 515 |
#define ldtul_p(addr) ldq_p(addr) |
|
| 516 |
#else |
|
| 517 |
#define GET_REGL(val) GET_REG32(val) |
|
| 518 |
#define ldtul_p(addr) ldl_p(addr) |
|
| 519 |
#endif |
|
| 520 |
|
|
| 521 | 492 |
#if defined(TARGET_I386) |
| 522 | 493 |
|
| 523 | 494 |
#include "target-i386/gdbstub.c" |
| b/include/exec/gdbstub.h | ||
|---|---|---|
| 39 | 39 |
#endif |
| 40 | 40 |
} |
| 41 | 41 |
|
| 42 |
/* The GDB remote protocol transfers values in target byte order. This means |
|
| 43 |
* we can use the raw memory access routines to access the value buffer. |
|
| 44 |
* Conveniently, these also handle the case where the buffer is mis-aligned. |
|
| 45 |
*/ |
|
| 46 |
|
|
| 47 |
static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val) |
|
| 48 |
{
|
|
| 49 |
stb_p(mem_buf, val); |
|
| 50 |
return 1; |
|
| 51 |
} |
|
| 52 |
|
|
| 53 |
static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val) |
|
| 54 |
{
|
|
| 55 |
stw_p(mem_buf, val); |
|
| 56 |
return 2; |
|
| 57 |
} |
|
| 58 |
|
|
| 59 |
static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val) |
|
| 60 |
{
|
|
| 61 |
stl_p(mem_buf, val); |
|
| 62 |
return 4; |
|
| 63 |
} |
|
| 64 |
|
|
| 65 |
static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val) |
|
| 66 |
{
|
|
| 67 |
stq_p(mem_buf, val); |
|
| 68 |
return 8; |
|
| 69 |
} |
|
| 70 |
|
|
| 71 |
#if TARGET_LONG_BITS == 64 |
|
| 72 |
#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val) |
|
| 73 |
#define ldtul_p(addr) ldq_p(addr) |
|
| 74 |
#else |
|
| 75 |
#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val) |
|
| 76 |
#define ldtul_p(addr) ldl_p(addr) |
|
| 77 |
#endif |
|
| 78 |
|
|
| 42 | 79 |
#endif |
| 43 | 80 |
|
| 44 | 81 |
#ifdef CONFIG_USER_ONLY |
| b/target-alpha/gdbstub.c | ||
|---|---|---|
| 49 | 49 |
default: |
| 50 | 50 |
return 0; |
| 51 | 51 |
} |
| 52 |
GET_REGL(val);
|
|
| 52 |
return gdb_get_regl(mem_buf, val);
|
|
| 53 | 53 |
} |
| 54 | 54 |
|
| 55 | 55 |
static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n) |
| b/target-arm/gdbstub.c | ||
|---|---|---|
| 28 | 28 |
{
|
| 29 | 29 |
if (n < 16) {
|
| 30 | 30 |
/* Core integer register. */ |
| 31 |
GET_REG32(env->regs[n]);
|
|
| 31 |
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
| 32 | 32 |
} |
| 33 | 33 |
if (n < 24) {
|
| 34 | 34 |
/* FPA registers. */ |
| ... | ... | |
| 44 | 44 |
if (gdb_has_xml) {
|
| 45 | 45 |
return 0; |
| 46 | 46 |
} |
| 47 |
GET_REG32(0);
|
|
| 47 |
return gdb_get_reg32(mem_buf, 0);
|
|
| 48 | 48 |
case 25: |
| 49 | 49 |
/* CPSR */ |
| 50 |
GET_REG32(cpsr_read(env));
|
|
| 50 |
return gdb_get_reg32(mem_buf, cpsr_read(env));
|
|
| 51 | 51 |
} |
| 52 | 52 |
/* Unknown register. */ |
| 53 | 53 |
return 0; |
| b/target-cris/gdbstub.c | ||
|---|---|---|
| 22 | 22 |
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n) |
| 23 | 23 |
{
|
| 24 | 24 |
if (n < 15) {
|
| 25 |
GET_REG32(env->regs[n]);
|
|
| 25 |
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
| 26 | 26 |
} |
| 27 | 27 |
|
| 28 | 28 |
if (n == 15) {
|
| 29 |
GET_REG32(env->pc);
|
|
| 29 |
return gdb_get_reg32(mem_buf, env->pc);
|
|
| 30 | 30 |
} |
| 31 | 31 |
|
| 32 | 32 |
if (n < 32) {
|
| 33 | 33 |
switch (n) {
|
| 34 | 34 |
case 16: |
| 35 |
GET_REG8(env->pregs[n - 16]);
|
|
| 35 |
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
|
|
| 36 | 36 |
case 17: |
| 37 |
GET_REG8(env->pregs[n - 16]);
|
|
| 37 |
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
|
|
| 38 | 38 |
case 20: |
| 39 | 39 |
case 21: |
| 40 |
GET_REG16(env->pregs[n - 16]);
|
|
| 40 |
return gdb_get_reg16(mem_buf, env->pregs[n - 16]);
|
|
| 41 | 41 |
default: |
| 42 | 42 |
if (n >= 23) {
|
| 43 |
GET_REG32(env->pregs[n - 16]);
|
|
| 43 |
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
|
|
| 44 | 44 |
} |
| 45 | 45 |
break; |
| 46 | 46 |
} |
| ... | ... | |
| 58 | 58 |
|
| 59 | 59 |
srs = env->pregs[PR_SRS]; |
| 60 | 60 |
if (n < 16) {
|
| 61 |
GET_REG32(env->regs[n]);
|
|
| 61 |
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
| 62 | 62 |
} |
| 63 | 63 |
|
| 64 | 64 |
if (n >= 21 && n < 32) {
|
| 65 |
GET_REG32(env->pregs[n - 16]);
|
|
| 65 |
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
|
|
| 66 | 66 |
} |
| 67 | 67 |
if (n >= 33 && n < 49) {
|
| 68 |
GET_REG32(env->sregs[srs][n - 33]);
|
|
| 68 |
return gdb_get_reg32(mem_buf, env->sregs[srs][n - 33]);
|
|
| 69 | 69 |
} |
| 70 | 70 |
switch (n) {
|
| 71 | 71 |
case 16: |
| 72 |
GET_REG8(env->pregs[0]);
|
|
| 72 |
return gdb_get_reg8(mem_buf, env->pregs[0]);
|
|
| 73 | 73 |
case 17: |
| 74 |
GET_REG8(env->pregs[1]);
|
|
| 74 |
return gdb_get_reg8(mem_buf, env->pregs[1]);
|
|
| 75 | 75 |
case 18: |
| 76 |
GET_REG32(env->pregs[2]);
|
|
| 76 |
return gdb_get_reg32(mem_buf, env->pregs[2]);
|
|
| 77 | 77 |
case 19: |
| 78 |
GET_REG8(srs);
|
|
| 78 |
return gdb_get_reg8(mem_buf, srs);
|
|
| 79 | 79 |
case 20: |
| 80 |
GET_REG16(env->pregs[4]);
|
|
| 80 |
return gdb_get_reg16(mem_buf, env->pregs[4]);
|
|
| 81 | 81 |
case 32: |
| 82 |
GET_REG32(env->pc);
|
|
| 82 |
return gdb_get_reg32(mem_buf, env->pc);
|
|
| 83 | 83 |
} |
| 84 | 84 |
|
| 85 | 85 |
return 0; |
| b/target-i386/gdbstub.c | ||
|---|---|---|
| 39 | 39 |
{
|
| 40 | 40 |
if (n < CPU_NB_REGS) {
|
| 41 | 41 |
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
|
| 42 |
GET_REG64(env->regs[gpr_map[n]]);
|
|
| 42 |
return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
|
|
| 43 | 43 |
} else if (n < CPU_NB_REGS32) {
|
| 44 |
GET_REG32(env->regs[gpr_map32[n]]);
|
|
| 44 |
return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
|
|
| 45 | 45 |
} |
| 46 | 46 |
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
|
| 47 | 47 |
#ifdef USE_X86LDOUBLE |
| ... | ... | |
| 63 | 63 |
switch (n) {
|
| 64 | 64 |
case IDX_IP_REG: |
| 65 | 65 |
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
|
| 66 |
GET_REG64(env->eip);
|
|
| 66 |
return gdb_get_reg64(mem_buf, env->eip);
|
|
| 67 | 67 |
} else {
|
| 68 |
GET_REG32(env->eip);
|
|
| 68 |
return gdb_get_reg32(mem_buf, env->eip);
|
|
| 69 | 69 |
} |
| 70 | 70 |
case IDX_FLAGS_REG: |
| 71 |
GET_REG32(env->eflags);
|
|
| 71 |
return gdb_get_reg32(mem_buf, env->eflags);
|
|
| 72 | 72 |
|
| 73 | 73 |
case IDX_SEG_REGS: |
| 74 |
GET_REG32(env->segs[R_CS].selector);
|
|
| 74 |
return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
|
|
| 75 | 75 |
case IDX_SEG_REGS + 1: |
| 76 |
GET_REG32(env->segs[R_SS].selector);
|
|
| 76 |
return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
|
|
| 77 | 77 |
case IDX_SEG_REGS + 2: |
| 78 |
GET_REG32(env->segs[R_DS].selector);
|
|
| 78 |
return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
|
|
| 79 | 79 |
case IDX_SEG_REGS + 3: |
| 80 |
GET_REG32(env->segs[R_ES].selector);
|
|
| 80 |
return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
|
|
| 81 | 81 |
case IDX_SEG_REGS + 4: |
| 82 |
GET_REG32(env->segs[R_FS].selector);
|
|
| 82 |
return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
|
|
| 83 | 83 |
case IDX_SEG_REGS + 5: |
| 84 |
GET_REG32(env->segs[R_GS].selector);
|
|
| 84 |
return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
|
|
| 85 | 85 |
|
| 86 | 86 |
case IDX_FP_REGS + 8: |
| 87 |
GET_REG32(env->fpuc);
|
|
| 87 |
return gdb_get_reg32(mem_buf, env->fpuc);
|
|
| 88 | 88 |
case IDX_FP_REGS + 9: |
| 89 |
GET_REG32((env->fpus & ~0x3800) |
|
|
| 90 |
(env->fpstt & 0x7) << 11); |
|
| 89 |
return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
|
|
| 90 |
(env->fpstt & 0x7) << 11);
|
|
| 91 | 91 |
case IDX_FP_REGS + 10: |
| 92 |
GET_REG32(0); /* ftag */
|
|
| 92 |
return gdb_get_reg32(mem_buf, 0); /* ftag */
|
|
| 93 | 93 |
case IDX_FP_REGS + 11: |
| 94 |
GET_REG32(0); /* fiseg */
|
|
| 94 |
return gdb_get_reg32(mem_buf, 0); /* fiseg */
|
|
| 95 | 95 |
case IDX_FP_REGS + 12: |
| 96 |
GET_REG32(0); /* fioff */
|
|
| 96 |
return gdb_get_reg32(mem_buf, 0); /* fioff */
|
|
| 97 | 97 |
case IDX_FP_REGS + 13: |
| 98 |
GET_REG32(0); /* foseg */
|
|
| 98 |
return gdb_get_reg32(mem_buf, 0); /* foseg */
|
|
| 99 | 99 |
case IDX_FP_REGS + 14: |
| 100 |
GET_REG32(0); /* fooff */
|
|
| 100 |
return gdb_get_reg32(mem_buf, 0); /* fooff */
|
|
| 101 | 101 |
case IDX_FP_REGS + 15: |
| 102 |
GET_REG32(0); /* fop */
|
|
| 102 |
return gdb_get_reg32(mem_buf, 0); /* fop */
|
|
| 103 | 103 |
|
| 104 | 104 |
case IDX_MXCSR_REG: |
| 105 |
GET_REG32(env->mxcsr);
|
|
| 105 |
return gdb_get_reg32(mem_buf, env->mxcsr);
|
|
| 106 | 106 |
} |
| 107 | 107 |
} |
| 108 | 108 |
return 0; |
| b/target-lm32/gdbstub.c | ||
|---|---|---|
| 22 | 22 |
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n) |
| 23 | 23 |
{
|
| 24 | 24 |
if (n < 32) {
|
| 25 |
GET_REG32(env->regs[n]);
|
|
| 25 |
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
| 26 | 26 |
} else {
|
| 27 | 27 |
switch (n) {
|
| 28 | 28 |
case 32: |
| 29 |
GET_REG32(env->pc);
|
|
| 29 |
return gdb_get_reg32(mem_buf, env->pc);
|
|
| 30 | 30 |
/* FIXME: put in right exception ID */ |
| 31 | 31 |
case 33: |
| 32 |
GET_REG32(0);
|
|
| 32 |
return gdb_get_reg32(mem_buf, 0);
|
|
| 33 | 33 |
case 34: |
| 34 |
GET_REG32(env->eba);
|
|
| 34 |
return gdb_get_reg32(mem_buf, env->eba);
|
|
| 35 | 35 |
case 35: |
| 36 |
GET_REG32(env->deba);
|
|
| 36 |
return gdb_get_reg32(mem_buf, env->deba);
|
|
| 37 | 37 |
case 36: |
| 38 |
GET_REG32(env->ie);
|
|
| 38 |
return gdb_get_reg32(mem_buf, env->ie);
|
|
| 39 | 39 |
case 37: |
| 40 |
GET_REG32(lm32_pic_get_im(env->pic_state));
|
|
| 40 |
return gdb_get_reg32(mem_buf, lm32_pic_get_im(env->pic_state));
|
|
| 41 | 41 |
case 38: |
| 42 |
GET_REG32(lm32_pic_get_ip(env->pic_state));
|
|
| 42 |
return gdb_get_reg32(mem_buf, lm32_pic_get_ip(env->pic_state));
|
|
| 43 | 43 |
} |
| 44 | 44 |
} |
| 45 | 45 |
return 0; |
| b/target-m68k/gdbstub.c | ||
|---|---|---|
| 22 | 22 |
{
|
| 23 | 23 |
if (n < 8) {
|
| 24 | 24 |
/* D0-D7 */ |
| 25 |
GET_REG32(env->dregs[n]);
|
|
| 25 |
return gdb_get_reg32(mem_buf, env->dregs[n]);
|
|
| 26 | 26 |
} else if (n < 16) {
|
| 27 | 27 |
/* A0-A7 */ |
| 28 |
GET_REG32(env->aregs[n - 8]);
|
|
| 28 |
return gdb_get_reg32(mem_buf, env->aregs[n - 8]);
|
|
| 29 | 29 |
} else {
|
| 30 | 30 |
switch (n) {
|
| 31 | 31 |
case 16: |
| 32 |
GET_REG32(env->sr);
|
|
| 32 |
return gdb_get_reg32(mem_buf, env->sr);
|
|
| 33 | 33 |
case 17: |
| 34 |
GET_REG32(env->pc);
|
|
| 34 |
return gdb_get_reg32(mem_buf, env->pc);
|
|
| 35 | 35 |
} |
| 36 | 36 |
} |
| 37 | 37 |
/* FP registers not included here because they vary between |
| b/target-microblaze/gdbstub.c | ||
|---|---|---|
| 21 | 21 |
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n) |
| 22 | 22 |
{
|
| 23 | 23 |
if (n < 32) {
|
| 24 |
GET_REG32(env->regs[n]);
|
|
| 24 |
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
| 25 | 25 |
} else {
|
| 26 |
GET_REG32(env->sregs[n - 32]);
|
|
| 26 |
return gdb_get_reg32(mem_buf, env->sregs[n - 32]);
|
|
| 27 | 27 |
} |
| 28 | 28 |
return 0; |
| 29 | 29 |
} |
| b/target-mips/gdbstub.c | ||
|---|---|---|
| 21 | 21 |
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n) |
| 22 | 22 |
{
|
| 23 | 23 |
if (n < 32) {
|
| 24 |
GET_REGL(env->active_tc.gpr[n]);
|
|
| 24 |
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
|
|
| 25 | 25 |
} |
| 26 | 26 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
|
| 27 | 27 |
if (n >= 38 && n < 70) {
|
| 28 | 28 |
if (env->CP0_Status & (1 << CP0St_FR)) {
|
| 29 |
GET_REGL(env->active_fpu.fpr[n - 38].d); |
|
| 29 |
return gdb_get_regl(mem_buf, |
|
| 30 |
env->active_fpu.fpr[n - 38].d); |
|
| 30 | 31 |
} else {
|
| 31 |
GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); |
|
| 32 |
return gdb_get_regl(mem_buf, |
|
| 33 |
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); |
|
| 32 | 34 |
} |
| 33 | 35 |
} |
| 34 | 36 |
switch (n) {
|
| 35 | 37 |
case 70: |
| 36 |
GET_REGL((int32_t)env->active_fpu.fcr31);
|
|
| 38 |
return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
|
|
| 37 | 39 |
case 71: |
| 38 |
GET_REGL((int32_t)env->active_fpu.fcr0);
|
|
| 40 |
return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
|
|
| 39 | 41 |
} |
| 40 | 42 |
} |
| 41 | 43 |
switch (n) {
|
| 42 | 44 |
case 32: |
| 43 |
GET_REGL((int32_t)env->CP0_Status);
|
|
| 45 |
return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
|
|
| 44 | 46 |
case 33: |
| 45 |
GET_REGL(env->active_tc.LO[0]);
|
|
| 47 |
return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
|
|
| 46 | 48 |
case 34: |
| 47 |
GET_REGL(env->active_tc.HI[0]);
|
|
| 49 |
return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
|
|
| 48 | 50 |
case 35: |
| 49 |
GET_REGL(env->CP0_BadVAddr);
|
|
| 51 |
return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
|
|
| 50 | 52 |
case 36: |
| 51 |
GET_REGL((int32_t)env->CP0_Cause);
|
|
| 53 |
return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
|
|
| 52 | 54 |
case 37: |
| 53 |
GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); |
|
| 55 |
return gdb_get_regl(mem_buf, env->active_tc.PC | |
|
| 56 |
!!(env->hflags & MIPS_HFLAG_M16)); |
|
| 54 | 57 |
case 72: |
| 55 |
GET_REGL(0); /* fp */
|
|
| 58 |
return gdb_get_regl(mem_buf, 0); /* fp */
|
|
| 56 | 59 |
case 89: |
| 57 |
GET_REGL((int32_t)env->CP0_PRid);
|
|
| 60 |
return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
|
|
| 58 | 61 |
} |
| 59 | 62 |
if (n >= 73 && n <= 88) {
|
| 60 | 63 |
/* 16 embedded regs. */ |
| 61 |
GET_REGL(0);
|
|
| 64 |
return gdb_get_regl(mem_buf, 0);
|
|
| 62 | 65 |
} |
| 63 | 66 |
|
| 64 | 67 |
return 0; |
| b/target-openrisc/gdbstub.c | ||
|---|---|---|
| 21 | 21 |
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) |
| 22 | 22 |
{
|
| 23 | 23 |
if (n < 32) {
|
| 24 |
GET_REG32(env->gpr[n]);
|
|
| 24 |
return gdb_get_reg32(mem_buf, env->gpr[n]);
|
|
| 25 | 25 |
} else {
|
| 26 | 26 |
switch (n) {
|
| 27 | 27 |
case 32: /* PPC */ |
| 28 |
GET_REG32(env->ppc);
|
|
| 28 |
return gdb_get_reg32(mem_buf, env->ppc);
|
|
| 29 | 29 |
|
| 30 | 30 |
case 33: /* NPC */ |
| 31 |
GET_REG32(env->npc);
|
|
| 31 |
return gdb_get_reg32(mem_buf, env->npc);
|
|
| 32 | 32 |
|
| 33 | 33 |
case 34: /* SR */ |
| 34 |
GET_REG32(env->sr);
|
|
| 34 |
return gdb_get_reg32(mem_buf, env->sr);
|
|
| 35 | 35 |
|
| 36 | 36 |
default: |
| 37 | 37 |
break; |
| b/target-ppc/gdbstub.c | ||
|---|---|---|
| 29 | 29 |
{
|
| 30 | 30 |
if (n < 32) {
|
| 31 | 31 |
/* gprs */ |
| 32 |
GET_REGL(env->gpr[n]);
|
|
| 32 |
return gdb_get_regl(mem_buf, env->gpr[n]);
|
|
| 33 | 33 |
} else if (n < 64) {
|
| 34 | 34 |
/* fprs */ |
| 35 | 35 |
if (gdb_has_xml) {
|
| ... | ... | |
| 40 | 40 |
} else {
|
| 41 | 41 |
switch (n) {
|
| 42 | 42 |
case 64: |
| 43 |
GET_REGL(env->nip);
|
|
| 43 |
return gdb_get_regl(mem_buf, env->nip);
|
|
| 44 | 44 |
case 65: |
| 45 |
GET_REGL(env->msr);
|
|
| 45 |
return gdb_get_regl(mem_buf, env->msr);
|
|
| 46 | 46 |
case 66: |
| 47 | 47 |
{
|
| 48 | 48 |
uint32_t cr = 0; |
| ... | ... | |
| 50 | 50 |
for (i = 0; i < 8; i++) {
|
| 51 | 51 |
cr |= env->crf[i] << (32 - ((i + 1) * 4)); |
| 52 | 52 |
} |
| 53 |
GET_REG32(cr);
|
|
| 53 |
return gdb_get_reg32(mem_buf, cr);
|
|
| 54 | 54 |
} |
| 55 | 55 |
case 67: |
| 56 |
GET_REGL(env->lr);
|
|
| 56 |
return gdb_get_regl(mem_buf, env->lr);
|
|
| 57 | 57 |
case 68: |
| 58 |
GET_REGL(env->ctr);
|
|
| 58 |
return gdb_get_regl(mem_buf, env->ctr);
|
|
| 59 | 59 |
case 69: |
| 60 |
GET_REGL(env->xer);
|
|
| 60 |
return gdb_get_regl(mem_buf, env->xer);
|
|
| 61 | 61 |
case 70: |
| 62 | 62 |
{
|
| 63 | 63 |
if (gdb_has_xml) {
|
| 64 | 64 |
return 0; |
| 65 | 65 |
} |
| 66 |
GET_REG32(env->fpscr);
|
|
| 66 |
return gdb_get_reg32(mem_buf, env->fpscr);
|
|
| 67 | 67 |
} |
| 68 | 68 |
} |
| 69 | 69 |
} |
| b/target-s390x/gdbstub.c | ||
|---|---|---|
| 27 | 27 |
case S390_PSWM_REGNUM: |
| 28 | 28 |
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); |
| 29 | 29 |
val = deposit64(env->psw.mask, 44, 2, cc_op); |
| 30 |
GET_REGL(val);
|
|
| 30 |
return gdb_get_regl(mem_buf, val);
|
|
| 31 | 31 |
case S390_PSWA_REGNUM: |
| 32 |
GET_REGL(env->psw.addr);
|
|
| 32 |
return gdb_get_regl(mem_buf, env->psw.addr);
|
|
| 33 | 33 |
case S390_R0_REGNUM ... S390_R15_REGNUM: |
| 34 |
GET_REGL(env->regs[n-S390_R0_REGNUM]);
|
|
| 34 |
return gdb_get_regl(mem_buf, env->regs[n-S390_R0_REGNUM]);
|
|
| 35 | 35 |
case S390_A0_REGNUM ... S390_A15_REGNUM: |
| 36 |
GET_REG32(env->aregs[n-S390_A0_REGNUM]);
|
|
| 36 |
return gdb_get_reg32(mem_buf, env->aregs[n-S390_A0_REGNUM]);
|
|
| 37 | 37 |
case S390_FPC_REGNUM: |
| 38 |
GET_REG32(env->fpc);
|
|
| 38 |
return gdb_get_reg32(mem_buf, env->fpc);
|
|
| 39 | 39 |
case S390_F0_REGNUM ... S390_F15_REGNUM: |
| 40 |
GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
|
|
| 40 |
return gdb_get_reg64(mem_buf, env->fregs[n-S390_F0_REGNUM].ll);
|
|
| 41 | 41 |
} |
| 42 | 42 |
|
| 43 | 43 |
return 0; |
| b/target-sh4/gdbstub.c | ||
|---|---|---|
| 26 | 26 |
switch (n) {
|
| 27 | 27 |
case 0 ... 7: |
| 28 | 28 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
| 29 |
GET_REGL(env->gregs[n + 16]);
|
|
| 29 |
return gdb_get_regl(mem_buf, env->gregs[n + 16]);
|
|
| 30 | 30 |
} else {
|
| 31 |
GET_REGL(env->gregs[n]);
|
|
| 31 |
return gdb_get_regl(mem_buf, env->gregs[n]);
|
|
| 32 | 32 |
} |
| 33 | 33 |
case 8 ... 15: |
| 34 |
GET_REGL(env->gregs[n]);
|
|
| 34 |
return gdb_get_regl(mem_buf, env->gregs[n]);
|
|
| 35 | 35 |
case 16: |
| 36 |
GET_REGL(env->pc);
|
|
| 36 |
return gdb_get_regl(mem_buf, env->pc);
|
|
| 37 | 37 |
case 17: |
| 38 |
GET_REGL(env->pr);
|
|
| 38 |
return gdb_get_regl(mem_buf, env->pr);
|
|
| 39 | 39 |
case 18: |
| 40 |
GET_REGL(env->gbr);
|
|
| 40 |
return gdb_get_regl(mem_buf, env->gbr);
|
|
| 41 | 41 |
case 19: |
| 42 |
GET_REGL(env->vbr);
|
|
| 42 |
return gdb_get_regl(mem_buf, env->vbr);
|
|
| 43 | 43 |
case 20: |
| 44 |
GET_REGL(env->mach);
|
|
| 44 |
return gdb_get_regl(mem_buf, env->mach);
|
|
| 45 | 45 |
case 21: |
| 46 |
GET_REGL(env->macl);
|
|
| 46 |
return gdb_get_regl(mem_buf, env->macl);
|
|
| 47 | 47 |
case 22: |
| 48 |
GET_REGL(env->sr);
|
|
| 48 |
return gdb_get_regl(mem_buf, env->sr);
|
|
| 49 | 49 |
case 23: |
| 50 |
GET_REGL(env->fpul);
|
|
| 50 |
return gdb_get_regl(mem_buf, env->fpul);
|
|
| 51 | 51 |
case 24: |
| 52 |
GET_REGL(env->fpscr);
|
|
| 52 |
return gdb_get_regl(mem_buf, env->fpscr);
|
|
| 53 | 53 |
case 25 ... 40: |
| 54 | 54 |
if (env->fpscr & FPSCR_FR) {
|
| 55 | 55 |
stfl_p(mem_buf, env->fregs[n - 9]); |
| ... | ... | |
| 58 | 58 |
} |
| 59 | 59 |
return 4; |
| 60 | 60 |
case 41: |
| 61 |
GET_REGL(env->ssr);
|
|
| 61 |
return gdb_get_regl(mem_buf, env->ssr);
|
|
| 62 | 62 |
case 42: |
| 63 |
GET_REGL(env->spc);
|
|
| 63 |
return gdb_get_regl(mem_buf, env->spc);
|
|
| 64 | 64 |
case 43 ... 50: |
| 65 |
GET_REGL(env->gregs[n - 43]);
|
|
| 65 |
return gdb_get_regl(mem_buf, env->gregs[n - 43]);
|
|
| 66 | 66 |
case 51 ... 58: |
| 67 |
GET_REGL(env->gregs[n - (51 - 16)]);
|
|
| 67 |
return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]);
|
|
| 68 | 68 |
} |
| 69 | 69 |
|
| 70 | 70 |
return 0; |
| b/target-sparc/gdbstub.c | ||
|---|---|---|
| 19 | 19 |
*/ |
| 20 | 20 |
|
| 21 | 21 |
#ifdef TARGET_ABI32 |
| 22 |
#define GET_REGA(val) GET_REG32(val)
|
|
| 22 |
#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
|
|
| 23 | 23 |
#else |
| 24 |
#define GET_REGA(val) GET_REGL(val)
|
|
| 24 |
#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
|
|
| 25 | 25 |
#endif |
| 26 | 26 |
|
| 27 | 27 |
static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n) |
| 28 | 28 |
{
|
| 29 | 29 |
if (n < 8) {
|
| 30 | 30 |
/* g0..g7 */ |
| 31 |
GET_REGA(env->gregs[n]);
|
|
| 31 |
return gdb_get_rega(mem_buf, env->gregs[n]);
|
|
| 32 | 32 |
} |
| 33 | 33 |
if (n < 32) {
|
| 34 | 34 |
/* register window */ |
| 35 |
GET_REGA(env->regwptr[n - 8]);
|
|
| 35 |
return gdb_get_rega(mem_buf, env->regwptr[n - 8]);
|
|
| 36 | 36 |
} |
| 37 | 37 |
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) |
| 38 | 38 |
if (n < 64) {
|
| 39 | 39 |
/* fprs */ |
| 40 | 40 |
if (n & 1) {
|
| 41 |
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
|
|
| 41 |
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
|
|
| 42 | 42 |
} else {
|
| 43 |
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
|
|
| 43 |
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
|
|
| 44 | 44 |
} |
| 45 | 45 |
} |
| 46 | 46 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */ |
| 47 | 47 |
switch (n) {
|
| 48 | 48 |
case 64: |
| 49 |
GET_REGA(env->y);
|
|
| 49 |
return gdb_get_rega(mem_buf, env->y);
|
|
| 50 | 50 |
case 65: |
| 51 |
GET_REGA(cpu_get_psr(env));
|
|
| 51 |
return gdb_get_rega(mem_buf, cpu_get_psr(env));
|
|
| 52 | 52 |
case 66: |
| 53 |
GET_REGA(env->wim);
|
|
| 53 |
return gdb_get_rega(mem_buf, env->wim);
|
|
| 54 | 54 |
case 67: |
| 55 |
GET_REGA(env->tbr);
|
|
| 55 |
return gdb_get_rega(mem_buf, env->tbr);
|
|
| 56 | 56 |
case 68: |
| 57 |
GET_REGA(env->pc);
|
|
| 57 |
return gdb_get_rega(mem_buf, env->pc);
|
|
| 58 | 58 |
case 69: |
| 59 |
GET_REGA(env->npc);
|
|
| 59 |
return gdb_get_rega(mem_buf, env->npc);
|
|
| 60 | 60 |
case 70: |
| 61 |
GET_REGA(env->fsr);
|
|
| 61 |
return gdb_get_rega(mem_buf, env->fsr);
|
|
| 62 | 62 |
case 71: |
| 63 |
GET_REGA(0); /* csr */
|
|
| 63 |
return gdb_get_rega(mem_buf, 0); /* csr */
|
|
| 64 | 64 |
default: |
| 65 |
GET_REGA(0);
|
|
| 65 |
return gdb_get_rega(mem_buf, 0);
|
|
| 66 | 66 |
} |
| 67 | 67 |
#else |
| 68 | 68 |
if (n < 64) {
|
| 69 | 69 |
/* f0-f31 */ |
| 70 | 70 |
if (n & 1) {
|
| 71 |
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
|
|
| 71 |
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
|
|
| 72 | 72 |
} else {
|
| 73 |
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
|
|
| 73 |
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
|
|
| 74 | 74 |
} |
| 75 | 75 |
} |
| 76 | 76 |
if (n < 80) {
|
| 77 | 77 |
/* f32-f62 (double width, even numbers only) */ |
| 78 |
GET_REG64(env->fpr[(n - 32) / 2].ll);
|
|
| 78 |
return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
|
|
| 79 | 79 |
} |
| 80 | 80 |
switch (n) {
|
| 81 | 81 |
case 80: |
| 82 |
GET_REGL(env->pc);
|
|
| 82 |
return gdb_get_regl(mem_buf, env->pc);
|
|
| 83 | 83 |
case 81: |
| 84 |
GET_REGL(env->npc);
|
|
| 84 |
return gdb_get_regl(mem_buf, env->npc);
|
|
| 85 | 85 |
case 82: |
| 86 |
GET_REGL((cpu_get_ccr(env) << 32) |
|
|
| 87 |
((env->asi & 0xff) << 24) | |
|
| 88 |
((env->pstate & 0xfff) << 8) | |
|
| 89 |
cpu_get_cwp64(env)); |
|
| 86 |
return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |
|
|
| 87 |
((env->asi & 0xff) << 24) |
|
|
| 88 |
((env->pstate & 0xfff) << 8) |
|
|
| 89 |
cpu_get_cwp64(env));
|
|
| 90 | 90 |
case 83: |
| 91 |
GET_REGL(env->fsr);
|
|
| 91 |
return gdb_get_regl(mem_buf, env->fsr);
|
|
| 92 | 92 |
case 84: |
| 93 |
GET_REGL(env->fprs);
|
|
| 93 |
return gdb_get_regl(mem_buf, env->fprs);
|
|
| 94 | 94 |
case 85: |
| 95 |
GET_REGL(env->y);
|
|
| 95 |
return gdb_get_regl(mem_buf, env->y);
|
|
| 96 | 96 |
} |
| 97 | 97 |
#endif |
| 98 | 98 |
return 0; |
| b/target-xtensa/gdbstub.c | ||
|---|---|---|
| 28 | 28 |
|
| 29 | 29 |
switch (reg->type) {
|
| 30 | 30 |
case 9: /*pc*/ |
| 31 |
GET_REG32(env->pc);
|
|
| 31 |
return gdb_get_reg32(mem_buf, env->pc);
|
|
| 32 | 32 |
|
| 33 | 33 |
case 1: /*ar*/ |
| 34 | 34 |
xtensa_sync_phys_from_window(env); |
| 35 |
GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]); |
|
| 35 |
return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff) |
|
| 36 |
% env->config->nareg]); |
|
| 36 | 37 |
|
| 37 | 38 |
case 2: /*SR*/ |
| 38 |
GET_REG32(env->sregs[reg->targno & 0xff]);
|
|
| 39 |
return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
|
|
| 39 | 40 |
|
| 40 | 41 |
case 3: /*UR*/ |
| 41 |
GET_REG32(env->uregs[reg->targno & 0xff]);
|
|
| 42 |
return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
|
|
| 42 | 43 |
|
| 43 | 44 |
case 4: /*f*/ |
| 44 |
GET_REG32(float32_val(env->fregs[reg->targno & 0x0f])); |
|
| 45 |
return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno |
|
| 46 |
& 0x0f])); |
|
| 45 | 47 |
|
| 46 | 48 |
case 8: /*a*/ |
| 47 |
GET_REG32(env->regs[reg->targno & 0x0f]);
|
|
| 49 |
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
|
|
| 48 | 50 |
|
| 49 | 51 |
default: |
| 50 | 52 |
qemu_log("%s from reg %d of unsupported type %d\n",
|
Also available in: Unified diff