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/*
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 *  SH4 emulation
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 *
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 *  Copyright (c) 2005 Samuel Tardieu
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "hw/sh_intc.h"
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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  env->exception_index = -1;
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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                             int mmu_idx, int is_softmmu)
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{
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    env->tea = address;
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    env->exception_index = 0;
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    switch (rw) {
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    case 0:
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        env->tea = address;
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        env->exception_index = 0x0a0;
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        break;
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    case 1:
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        env->tea = address;
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        env->exception_index = 0x0c0;
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        break;
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    }
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    return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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    return addr;
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}
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#else /* !CONFIG_USER_ONLY */
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#define MMU_OK                   0
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#define MMU_ITLB_MISS            (-1)
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#define MMU_ITLB_MULTIPLE        (-2)
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#define MMU_ITLB_VIOLATION       (-3)
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#define MMU_DTLB_MISS_READ       (-4)
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#define MMU_DTLB_MISS_WRITE      (-5)
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#define MMU_DTLB_INITIAL_WRITE   (-6)
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#define MMU_DTLB_VIOLATION_READ  (-7)
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#define MMU_DTLB_VIOLATION_WRITE (-8)
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#define MMU_DTLB_MULTIPLE        (-9)
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#define MMU_DTLB_MISS            (-10)
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void do_interrupt(CPUState * env)
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{
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    int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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    int do_exp, irq_vector = env->exception_index;
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    /* prioritize exceptions over interrupts */
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    do_exp = env->exception_index != -1;
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    do_irq = do_irq && (env->exception_index == -1);
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    if (env->sr & SR_BL) {
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        if (do_exp && env->exception_index != 0x1e0) {
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            env->exception_index = 0x000; /* masked exception -> reset */
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        }
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        if (do_irq && !env->intr_at_halt) {
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            return; /* masked */
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        }
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        env->intr_at_halt = 0;
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    }
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    if (do_irq) {
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        irq_vector = sh_intc_get_pending_vector(env->intc_handle,
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                                                (env->sr >> 4) & 0xf);
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        if (irq_vector == -1) {
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            return; /* masked */
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        }
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    }
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    if (loglevel & CPU_LOG_INT) {
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        const char *expname;
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        switch (env->exception_index) {
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        case 0x0e0:
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            expname = "addr_error";
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            break;
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        case 0x040:
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            expname = "tlb_miss";
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            break;
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        case 0x0a0:
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            expname = "tlb_violation";
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            break;
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        case 0x180:
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            expname = "illegal_instruction";
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            break;
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        case 0x1a0:
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            expname = "slot_illegal_instruction";
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            break;
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        case 0x800:
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            expname = "fpu_disable";
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            break;
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        case 0x820:
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            expname = "slot_fpu";
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            break;
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        case 0x100:
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            expname = "data_write";
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            break;
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        case 0x060:
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            expname = "dtlb_miss_write";
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            break;
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        case 0x0c0:
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            expname = "dtlb_violation_write";
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            break;
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        case 0x120:
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            expname = "fpu_exception";
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            break;
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        case 0x080:
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            expname = "initial_page_write";
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            break;
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        case 0x160:
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            expname = "trapa";
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            break;
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        default:
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            expname = do_irq ? "interrupt" : "???";
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            break;
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        }
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        fprintf(logfile, "exception 0x%03x [%s] raised\n",
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                irq_vector, expname);
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        cpu_dump_state(env, logfile, fprintf, 0);
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    }
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    env->ssr = env->sr;
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    env->spc = env->pc;
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    env->sgr = env->gregs[15];
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    env->sr |= SR_BL | SR_MD | SR_RB;
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    if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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        /* Branch instruction should be executed again before delay slot. */
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        env->spc -= 2;
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        /* Clear flags for exception/interrupt routine. */
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        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
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    }
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    if (env->flags & DELAY_SLOT_CLEARME)
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        env->flags = 0;
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    if (do_exp) {
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        env->expevt = env->exception_index;
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        switch (env->exception_index) {
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        case 0x000:
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        case 0x020:
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        case 0x140:
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            env->sr &= ~SR_FD;
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            env->sr |= 0xf << 4; /* IMASK */
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            env->pc = 0xa0000000;
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            break;
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        case 0x040:
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        case 0x060:
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            env->pc = env->vbr + 0x400;
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            break;
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        case 0x160:
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            env->spc += 2; /* special case for TRAPA */
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            /* fall through */
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        default:
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            env->pc = env->vbr + 0x100;
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            break;
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        }
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        return;
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    }
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    if (do_irq) {
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        env->intevt = irq_vector;
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        env->pc = env->vbr + 0x600;
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        return;
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    }
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}
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static void update_itlb_use(CPUState * env, int itlbnb)
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{
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    uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
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    switch (itlbnb) {
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    case 0:
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        and_mask = 0x1f;
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        break;
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    case 1:
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        and_mask = 0xe7;
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        or_mask = 0x80;
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        break;
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    case 2:
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        and_mask = 0xfb;
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        or_mask = 0x50;
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        break;
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    case 3:
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        or_mask = 0x2c;
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        break;
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    }
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    env->mmucr &= (and_mask << 24) | 0x00ffffff;
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    env->mmucr |= (or_mask << 24);
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}
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static int itlb_replacement(CPUState * env)
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{
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    if ((env->mmucr & 0xe0000000) == 0xe0000000)
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        return 0;
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    if ((env->mmucr & 0x98000000) == 0x18000000)
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        return 1;
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    if ((env->mmucr & 0x54000000) == 0x04000000)
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        return 2;
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    if ((env->mmucr & 0x2c000000) == 0x00000000)
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        return 3;
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    assert(0);
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}
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/* Find the corresponding entry in the right TLB
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   Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address,
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                          tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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    int match = MMU_DTLB_MISS;
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    uint32_t start, end;
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    uint8_t asid;
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    int i;
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    asid = env->pteh & 0xff;
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    for (i = 0; i < nbtlb; i++) {
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        if (!entries[i].v)
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            continue;                /* Invalid entry */
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        if (use_asid && entries[i].asid != asid)
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            continue;                /* Bad ASID */
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#if 0
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        switch (entries[i].sz) {
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        case 0:
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            size = 1024;        /* 1kB */
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            break;
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        case 1:
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            size = 4 * 1024;        /* 4kB */
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            break;
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        case 2:
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            size = 64 * 1024;        /* 64kB */
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            break;
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        case 3:
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            size = 1024 * 1024;        /* 1MB */
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            break;
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        default:
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            assert(0);
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        }
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#endif
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        start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
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        end = start + entries[i].size - 1;
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        if (address >= start && address <= end) {        /* Match */
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            if (match != MMU_DTLB_MISS)
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                return MMU_DTLB_MULTIPLE;        /* Multiple match */
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            match = i;
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        }
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    }
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    return match;
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}
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static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
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                                 const tlb_t * needle)
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{
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    int i;
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    for (i = 0; i < nbtlb; i++)
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        if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
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            return 1;
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    return 0;
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}
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static void increment_urc(CPUState * env)
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{
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    uint8_t urb, urc;
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    /* Increment URC */
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    urb = ((env->mmucr) >> 18) & 0x3f;
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    urc = ((env->mmucr) >> 10) & 0x3f;
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    urc++;
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    if (urc == urb || urc == UTLB_SIZE - 1)
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        urc = 0;
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    env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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}
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/* Find itlb entry - update itlb from utlb if necessary and asked for
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   Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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   Update the itlb from utlb if update is not 0
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*/
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int find_itlb_entry(CPUState * env, target_ulong address,
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                    int use_asid, int update)
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{
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    int e, n;
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    e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
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    if (e == MMU_DTLB_MULTIPLE)
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        e = MMU_ITLB_MULTIPLE;
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    else if (e == MMU_DTLB_MISS && update) {
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        e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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        if (e >= 0) {
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            tlb_t * ientry;
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            n = itlb_replacement(env);
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            ientry = &env->itlb[n];
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            if (ientry->v) {
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                if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
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                    tlb_flush_page(env, ientry->vpn << 10);
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            }
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            *ientry = env->utlb[e];
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            e = n;
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        } else if (e == MMU_DTLB_MISS)
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            e = MMU_ITLB_MISS;
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    } else if (e == MMU_DTLB_MISS)
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        e = MMU_ITLB_MISS;
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    if (e >= 0)
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        update_itlb_use(env, e);
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    return e;
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}
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/* Find utlb entry
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   Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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{
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    /* per utlb access */
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    increment_urc(env);
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    /* Return entry */
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    return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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}
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/* Match address against MMU
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   Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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   MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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   MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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   MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
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*/
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static int get_mmu_address(CPUState * env, target_ulong * physical,
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                           int *prot, target_ulong address,
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                           int rw, int access_type)
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{
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    int use_asid, is_code, n;
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    tlb_t *matching = NULL;
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    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
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    is_code = env->pc == address;        /* Hack */
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    /* Use a hack to find if this is an instruction or data access */
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    if (env->pc == address && !(rw & PAGE_WRITE)) {
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        n = find_itlb_entry(env, address, use_asid, 1);
371 fdf9b3e8 bellard
        if (n >= 0) {
372 fdf9b3e8 bellard
            matching = &env->itlb[n];
373 fdf9b3e8 bellard
            if ((env->sr & SR_MD) & !(matching->pr & 2))
374 fdf9b3e8 bellard
                n = MMU_ITLB_VIOLATION;
375 fdf9b3e8 bellard
            else
376 fdf9b3e8 bellard
                *prot = PAGE_READ;
377 fdf9b3e8 bellard
        }
378 fdf9b3e8 bellard
    } else {
379 fdf9b3e8 bellard
        n = find_utlb_entry(env, address, use_asid);
380 fdf9b3e8 bellard
        if (n >= 0) {
381 fdf9b3e8 bellard
            matching = &env->utlb[n];
382 fdf9b3e8 bellard
            switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
383 fdf9b3e8 bellard
            case 0:                /* 000 */
384 fdf9b3e8 bellard
            case 2:                /* 010 */
385 fdf9b3e8 bellard
                n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
386 fdf9b3e8 bellard
                    MMU_DTLB_VIOLATION_READ;
387 fdf9b3e8 bellard
                break;
388 fdf9b3e8 bellard
            case 1:                /* 001 */
389 fdf9b3e8 bellard
            case 4:                /* 100 */
390 fdf9b3e8 bellard
            case 5:                /* 101 */
391 fdf9b3e8 bellard
                if (rw & PAGE_WRITE)
392 fdf9b3e8 bellard
                    n = MMU_DTLB_VIOLATION_WRITE;
393 fdf9b3e8 bellard
                else
394 fdf9b3e8 bellard
                    *prot = PAGE_READ;
395 fdf9b3e8 bellard
                break;
396 fdf9b3e8 bellard
            case 3:                /* 011 */
397 fdf9b3e8 bellard
            case 6:                /* 110 */
398 fdf9b3e8 bellard
            case 7:                /* 111 */
399 fdf9b3e8 bellard
                *prot = rw & (PAGE_READ | PAGE_WRITE);
400 fdf9b3e8 bellard
                break;
401 fdf9b3e8 bellard
            }
402 fdf9b3e8 bellard
        } else if (n == MMU_DTLB_MISS) {
403 fdf9b3e8 bellard
            n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
404 fdf9b3e8 bellard
                MMU_DTLB_MISS_READ;
405 fdf9b3e8 bellard
        }
406 fdf9b3e8 bellard
    }
407 fdf9b3e8 bellard
    if (n >= 0) {
408 fdf9b3e8 bellard
        *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
409 fdf9b3e8 bellard
            (address & (matching->size - 1));
410 fdf9b3e8 bellard
        if ((rw & PAGE_WRITE) & !matching->d)
411 fdf9b3e8 bellard
            n = MMU_DTLB_INITIAL_WRITE;
412 fdf9b3e8 bellard
        else
413 fdf9b3e8 bellard
            n = MMU_OK;
414 fdf9b3e8 bellard
    }
415 fdf9b3e8 bellard
    return n;
416 fdf9b3e8 bellard
}
417 fdf9b3e8 bellard
418 fdf9b3e8 bellard
int get_physical_address(CPUState * env, target_ulong * physical,
419 fdf9b3e8 bellard
                         int *prot, target_ulong address,
420 fdf9b3e8 bellard
                         int rw, int access_type)
421 fdf9b3e8 bellard
{
422 fdf9b3e8 bellard
    /* P1, P2 and P4 areas do not use translation */
423 fdf9b3e8 bellard
    if ((address >= 0x80000000 && address < 0xc0000000) ||
424 fdf9b3e8 bellard
        address >= 0xe0000000) {
425 fdf9b3e8 bellard
        if (!(env->sr & SR_MD)
426 fdf9b3e8 bellard
            && (address < 0xe0000000 || address > 0xe4000000)) {
427 fdf9b3e8 bellard
            /* Unauthorized access in user mode (only store queues are available) */
428 fdf9b3e8 bellard
            fprintf(stderr, "Unauthorized access\n");
429 fdf9b3e8 bellard
            return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
430 fdf9b3e8 bellard
                MMU_DTLB_MISS_READ;
431 fdf9b3e8 bellard
        }
432 29e179bc aurel32
        if (address >= 0x80000000 && address < 0xc0000000) {
433 29e179bc aurel32
            /* Mask upper 3 bits for P1 and P2 areas */
434 29e179bc aurel32
            *physical = address & 0x1fffffff;
435 29e179bc aurel32
        } else if (address >= 0xfc000000) {
436 29e179bc aurel32
            /*
437 29e179bc aurel32
             * Mask upper 3 bits for control registers in P4 area,
438 29e179bc aurel32
             * to unify access to control registers via P0-P3 area.
439 29e179bc aurel32
             * The addresses for cache store queue, TLB address array
440 29e179bc aurel32
             * are not masked.
441 29e179bc aurel32
             */
442 29e179bc aurel32
        *physical = address & 0x1fffffff;
443 29e179bc aurel32
        } else {
444 29e179bc aurel32
            /* access to cache store queue, or TLB address array. */
445 29e179bc aurel32
            *physical = address;
446 29e179bc aurel32
        }
447 fdf9b3e8 bellard
        *prot = PAGE_READ | PAGE_WRITE;
448 fdf9b3e8 bellard
        return MMU_OK;
449 fdf9b3e8 bellard
    }
450 fdf9b3e8 bellard
451 fdf9b3e8 bellard
    /* If MMU is disabled, return the corresponding physical page */
452 fdf9b3e8 bellard
    if (!env->mmucr & MMUCR_AT) {
453 fdf9b3e8 bellard
        *physical = address & 0x1FFFFFFF;
454 fdf9b3e8 bellard
        *prot = PAGE_READ | PAGE_WRITE;
455 fdf9b3e8 bellard
        return MMU_OK;
456 fdf9b3e8 bellard
    }
457 fdf9b3e8 bellard
458 fdf9b3e8 bellard
    /* We need to resort to the MMU */
459 fdf9b3e8 bellard
    return get_mmu_address(env, physical, prot, address, rw, access_type);
460 fdf9b3e8 bellard
}
461 fdf9b3e8 bellard
462 fdf9b3e8 bellard
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
463 6ebbf390 j_mayer
                             int mmu_idx, int is_softmmu)
464 fdf9b3e8 bellard
{
465 fdf9b3e8 bellard
    target_ulong physical, page_offset, page_size;
466 fdf9b3e8 bellard
    int prot, ret, access_type;
467 fdf9b3e8 bellard
468 ea2b542a aurel32
    switch (rw) {
469 ea2b542a aurel32
    case 0:
470 ea2b542a aurel32
        rw = PAGE_READ;
471 ea2b542a aurel32
        break;
472 ea2b542a aurel32
    case 1:
473 ea2b542a aurel32
        rw = PAGE_WRITE;
474 ea2b542a aurel32
        break;
475 ea2b542a aurel32
    case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
476 ea2b542a aurel32
        rw = PAGE_READ;
477 ea2b542a aurel32
        break;
478 ea2b542a aurel32
    default:
479 ea2b542a aurel32
        /* fatal error */
480 ea2b542a aurel32
        assert(0);
481 ea2b542a aurel32
    }
482 ea2b542a aurel32
483 fdf9b3e8 bellard
    /* XXXXX */
484 fdf9b3e8 bellard
#if 0
485 6ebbf390 j_mayer
    fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
486 6ebbf390 j_mayer
            __func__, env->pc, address, rw, mmu_idx, is_softmmu);
487 fdf9b3e8 bellard
#endif
488 fdf9b3e8 bellard
489 fdf9b3e8 bellard
    access_type = ACCESS_INT;
490 fdf9b3e8 bellard
    ret =
491 fdf9b3e8 bellard
        get_physical_address(env, &physical, &prot, address, rw,
492 fdf9b3e8 bellard
                             access_type);
493 fdf9b3e8 bellard
494 fdf9b3e8 bellard
    if (ret != MMU_OK) {
495 fdf9b3e8 bellard
        env->tea = address;
496 fdf9b3e8 bellard
        switch (ret) {
497 fdf9b3e8 bellard
        case MMU_ITLB_MISS:
498 fdf9b3e8 bellard
        case MMU_DTLB_MISS_READ:
499 fdf9b3e8 bellard
            env->exception_index = 0x040;
500 fdf9b3e8 bellard
            break;
501 fdf9b3e8 bellard
        case MMU_DTLB_MULTIPLE:
502 fdf9b3e8 bellard
        case MMU_ITLB_MULTIPLE:
503 fdf9b3e8 bellard
            env->exception_index = 0x140;
504 fdf9b3e8 bellard
            break;
505 fdf9b3e8 bellard
        case MMU_ITLB_VIOLATION:
506 fdf9b3e8 bellard
            env->exception_index = 0x0a0;
507 fdf9b3e8 bellard
            break;
508 fdf9b3e8 bellard
        case MMU_DTLB_MISS_WRITE:
509 fdf9b3e8 bellard
            env->exception_index = 0x060;
510 fdf9b3e8 bellard
            break;
511 fdf9b3e8 bellard
        case MMU_DTLB_INITIAL_WRITE:
512 fdf9b3e8 bellard
            env->exception_index = 0x080;
513 fdf9b3e8 bellard
            break;
514 fdf9b3e8 bellard
        case MMU_DTLB_VIOLATION_READ:
515 fdf9b3e8 bellard
            env->exception_index = 0x0a0;
516 fdf9b3e8 bellard
            break;
517 fdf9b3e8 bellard
        case MMU_DTLB_VIOLATION_WRITE:
518 fdf9b3e8 bellard
            env->exception_index = 0x0c0;
519 fdf9b3e8 bellard
            break;
520 fdf9b3e8 bellard
        default:
521 fdf9b3e8 bellard
            assert(0);
522 fdf9b3e8 bellard
        }
523 fdf9b3e8 bellard
        return 1;
524 fdf9b3e8 bellard
    }
525 fdf9b3e8 bellard
526 fdf9b3e8 bellard
    page_size = TARGET_PAGE_SIZE;
527 fdf9b3e8 bellard
    page_offset =
528 fdf9b3e8 bellard
        (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
529 fdf9b3e8 bellard
    address = (address & TARGET_PAGE_MASK) + page_offset;
530 fdf9b3e8 bellard
    physical = (physical & TARGET_PAGE_MASK) + page_offset;
531 fdf9b3e8 bellard
532 6ebbf390 j_mayer
    return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
533 fdf9b3e8 bellard
}
534 355fb23d pbrook
535 9b3c35e0 j_mayer
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
536 355fb23d pbrook
{
537 355fb23d pbrook
    target_ulong physical;
538 355fb23d pbrook
    int prot;
539 355fb23d pbrook
540 355fb23d pbrook
    get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
541 355fb23d pbrook
    return physical;
542 355fb23d pbrook
}
543 355fb23d pbrook
544 ea2b542a aurel32
void cpu_load_tlb(CPUState * env)
545 ea2b542a aurel32
{
546 ea2b542a aurel32
    int n = cpu_mmucr_urc(env->mmucr);
547 ea2b542a aurel32
    tlb_t * entry = &env->utlb[n];
548 ea2b542a aurel32
549 06afe2c8 aurel32
    if (entry->v) {
550 06afe2c8 aurel32
        /* Overwriting valid entry in utlb. */
551 06afe2c8 aurel32
        target_ulong address = entry->vpn << 10;
552 06afe2c8 aurel32
        if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
553 06afe2c8 aurel32
            tlb_flush_page(env, address);
554 06afe2c8 aurel32
        }
555 06afe2c8 aurel32
    }
556 06afe2c8 aurel32
557 06afe2c8 aurel32
    /* per utlb access cannot implemented. */
558 06afe2c8 aurel32
    increment_urc(env);
559 06afe2c8 aurel32
560 ea2b542a aurel32
    /* Take values into cpu status from registers. */
561 ea2b542a aurel32
    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
562 ea2b542a aurel32
    entry->vpn  = cpu_pteh_vpn(env->pteh);
563 ea2b542a aurel32
    entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
564 ea2b542a aurel32
    entry->ppn  = cpu_ptel_ppn(env->ptel);
565 ea2b542a aurel32
    entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
566 ea2b542a aurel32
    switch (entry->sz) {
567 ea2b542a aurel32
    case 0: /* 00 */
568 ea2b542a aurel32
        entry->size = 1024; /* 1K */
569 ea2b542a aurel32
        break;
570 ea2b542a aurel32
    case 1: /* 01 */
571 ea2b542a aurel32
        entry->size = 1024 * 4; /* 4K */
572 ea2b542a aurel32
        break;
573 ea2b542a aurel32
    case 2: /* 10 */
574 ea2b542a aurel32
        entry->size = 1024 * 64; /* 64K */
575 ea2b542a aurel32
        break;
576 ea2b542a aurel32
    case 3: /* 11 */
577 ea2b542a aurel32
        entry->size = 1024 * 1024; /* 1M */
578 ea2b542a aurel32
        break;
579 ea2b542a aurel32
    default:
580 ea2b542a aurel32
        assert(0);
581 ea2b542a aurel32
        break;
582 ea2b542a aurel32
    }
583 ea2b542a aurel32
    entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
584 ea2b542a aurel32
    entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
585 ea2b542a aurel32
    entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
586 ea2b542a aurel32
    entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
587 ea2b542a aurel32
    entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
588 ea2b542a aurel32
    entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
589 ea2b542a aurel32
    entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
590 ea2b542a aurel32
}
591 ea2b542a aurel32
592 29e179bc aurel32
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
593 29e179bc aurel32
                                    uint32_t mem_value)
594 29e179bc aurel32
{
595 29e179bc aurel32
    int associate = addr & 0x0000080;
596 29e179bc aurel32
    uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
597 29e179bc aurel32
    uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
598 29e179bc aurel32
    uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
599 29e179bc aurel32
    uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
600 29e179bc aurel32
601 29e179bc aurel32
    if (associate) {
602 29e179bc aurel32
        int i;
603 29e179bc aurel32
        tlb_t * utlb_match_entry = NULL;
604 29e179bc aurel32
        int needs_tlb_flush = 0;
605 29e179bc aurel32
606 29e179bc aurel32
        /* search UTLB */
607 29e179bc aurel32
        for (i = 0; i < UTLB_SIZE; i++) {
608 29e179bc aurel32
            tlb_t * entry = &s->utlb[i];
609 29e179bc aurel32
            if (!entry->v)
610 29e179bc aurel32
                continue;
611 29e179bc aurel32
612 29e179bc aurel32
            if (entry->vpn == vpn && entry->asid == asid) {
613 29e179bc aurel32
                if (utlb_match_entry) {
614 29e179bc aurel32
                    /* Multiple TLB Exception */
615 29e179bc aurel32
                    s->exception_index = 0x140;
616 29e179bc aurel32
                    s->tea = addr;
617 29e179bc aurel32
                    break;
618 29e179bc aurel32
                }
619 29e179bc aurel32
                if (entry->v && !v)
620 29e179bc aurel32
                    needs_tlb_flush = 1;
621 29e179bc aurel32
                entry->v = v;
622 29e179bc aurel32
                entry->d = d;
623 29e179bc aurel32
                utlb_match_entry = entry;
624 29e179bc aurel32
            }
625 29e179bc aurel32
            increment_urc(s); /* per utlb access */
626 29e179bc aurel32
        }
627 29e179bc aurel32
628 29e179bc aurel32
        /* search ITLB */
629 29e179bc aurel32
        for (i = 0; i < ITLB_SIZE; i++) {
630 29e179bc aurel32
            tlb_t * entry = &s->itlb[i];
631 29e179bc aurel32
            if (entry->vpn == vpn && entry->asid == asid) {
632 29e179bc aurel32
                if (entry->v && !v)
633 29e179bc aurel32
                    needs_tlb_flush = 1;
634 29e179bc aurel32
                if (utlb_match_entry)
635 29e179bc aurel32
                    *entry = *utlb_match_entry;
636 29e179bc aurel32
                else
637 29e179bc aurel32
                    entry->v = v;
638 29e179bc aurel32
                break;
639 29e179bc aurel32
            }
640 29e179bc aurel32
        }
641 29e179bc aurel32
642 29e179bc aurel32
        if (needs_tlb_flush)
643 29e179bc aurel32
            tlb_flush_page(s, vpn << 10);
644 29e179bc aurel32
        
645 29e179bc aurel32
    } else {
646 29e179bc aurel32
        int index = (addr & 0x00003f00) >> 8;
647 29e179bc aurel32
        tlb_t * entry = &s->utlb[index];
648 29e179bc aurel32
        if (entry->v) {
649 29e179bc aurel32
            /* Overwriting valid entry in utlb. */
650 29e179bc aurel32
            target_ulong address = entry->vpn << 10;
651 29e179bc aurel32
            if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
652 29e179bc aurel32
                tlb_flush_page(s, address);
653 29e179bc aurel32
            }
654 29e179bc aurel32
        }
655 29e179bc aurel32
        entry->asid = asid;
656 29e179bc aurel32
        entry->vpn = vpn;
657 29e179bc aurel32
        entry->d = d;
658 29e179bc aurel32
        entry->v = v;
659 29e179bc aurel32
        increment_urc(s);
660 29e179bc aurel32
    }
661 29e179bc aurel32
}
662 29e179bc aurel32
663 355fb23d pbrook
#endif