kvm: Rename kvm_arch_process_irqchip_events to async_events
We will broaden the scope of this function on x86 beyond irqchip events.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: ppc: Fix breakage of kvm_arch_pre_run/process_irqchip_events
Commit 7a39fe5882 failed to convert the right arch function.
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Merge remote branch 'qemu-kvm/uq/master' into staging
Handle icount for powerpc tbl/tbu/decr load and store.
Handle option '-icount X' on powerpc targets.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
kvm: Drop return values from kvm_arch_pre/post_run
We do not check them, and the only arch with non-empty implementationsalways returns 0 (this is also true for qemu-kvm).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Alexander Graf <agraf@suse.de>...
kvm: Provide sigbus services arch-independently
Provide arch-independent kvm_on_sigbus* stubs to remove the #ifdef'eryfrom cpus.c. This patch also fixes --disable-kvm build by providing themissing kvm_on_sigbus_vcpu kvm-stub.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
aliguori: fix build with !defined(KVM_CAP_ASYNC_PF)
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: Consolidate must-have capability checks
Instead of splattering the code with #ifdefs and runtime checks forcapabilities we cannot work without anyway, provide central testinfrastructure for verifying their availability both at build andruntime.
kvm: Drop smp_cpus argument from init functions
No longer used.
kvm: Stop on all fatal exit reasons
Ensure that we stop the guest whenever we face a fatal or unknown exitreason. If we stop, we also have to enforce a cpu loop exit.
ppc: Correct BookE tlb reads
Call the tlb read helper (and not the write helper) for tlbreads.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-ppc: fix wrong NaN tests
Some tests in FPU emulation code were wrongly using float64_is_nan()before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wronglyusing float64_is_quiet_nan() after. Fix them by using float64_is_any_nan()instead.
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix sNaN propagation
The current FPU code returns 0.0 if one of the operand is asignaling NaN and the VXSNAN exception is disabled.
fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNANexception as the operand should be propagated instead of a new...
target-ppc: use float32_is_any_nan()
Use the new function float32_is_any_nan() instead offloat32_is_quiet_nan() || float32_is_signaling_nan().
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix default qNaN
On PPC the default qNaN doesn't have the sign bit set.
target-ppc: remove PRECISE_EMULATION define
The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and notsomething easily tunable. Remove it and non-precise emulation code asit doesn't make a noticeable difference in speed. People wanting speed...
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
Fix translation of unary PPC/SPE instructions (efdneg etc.).
Signed-off-by: Mike Pall <mike-lp10@luajit.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: kvm: fix signedness warning
I get a warning on a signed comparison with an unsigned variable, solet's make the variable signed and be happy.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
ppc: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced warnings:/src/qemu/target-ppc/op_helper.c: In function 'helper_icbi':/src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]...
ppc: remove video.x
Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.
Remove video.x MoL hacks.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ppc: Minor 40x MMU fixes
Signed-off-by: John Clark <clarkjc@runbox.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
powerpc: Add a virtex5 ml507 refdesign board
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>
powerpc: Add a ppc-440x5 Xilinx model
Add a powerpc 440x5 with the model ID on the Xilinx virtex5.Connect the 440x5 to the 40x interrupt logic.
powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linuxon virtex5 boards.
PPC: Suppress gcc warnings with -Wtype-limits
The hack added by c5b76b381081680633e2e0a91216507430409fb2 was notenough to avoid warnings with gcc flag -Wtype-limits. Add a new macroto fix both problems.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSRvalue that is rather simple. If we leave out the HV case, it's almostalways 0.
To reflect this, let's redesign the way that MSR value gets calculated....
PPC: Enable hint bits for lwarx/ldarx
The lwarx and ldarx instructions have a bit to give some hint to theCPU which is safe to ignore. We currently refuse to accept any instructionwith that bit set, as it used to be declared MBZ.
Let's remove the reserved bit and make the instruction work as expected....
powerpc: Avoid TLB related log spamming
Invalid TLB entries are normal and should not spam the log.
KVM: PPC: Add level based interrupt logic
KVM on PowerPC used to have completely broken interrupt logic. Usually,interrupts work by having a PIC that pulls a line up/down, so the CPU knowsthat an interrupt is active. This line stays active until some action is...
PPC: Add PV hypercall transport through fw_cfg
On KVM for PPC we need to tell the guest which instructions to use whendoing a hypercall. The clean way to do this is to go through an ioctlfrom userspace and passing it on to the guest using the device tree....
target-ppc: fix power mode checking on 7400/7410
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC7400 and 7410 support it.
target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bitsof the 64-bit register when passing 32-bit arguments. Othersrequire the value to be properly sign-extended for the type.I.e. "int32_t" must be sign-extended and "uint32_t" must be...
target-ppc: remove useless line
This line was a bit clear.The next lines set or reset this bit (LE) depending of another bit (ILE).So the first line is useless.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processorsbecause some interrupt specifics bits of SRR1 are copied to MSR.
SRR1 is a save of MSR during interrupt.During RFI, MSR must be restored from SRR1....
Fix %lld or %llx printf format use
PPC/KVM: make iothread work
When running with --enable-io-thread the timer we have doesn't help,because it doesn't wake up the CPU thread. So instead we need toactually kick it.
While at it I refined the logic a bit to not dumbly trigger a timerevery 500ms, but rather do it more often after an interrupt got injected....
Do not stop VM if emulation failed in userspace.
Continue vcpu execution in case emulation failure happened while vcpuwas in userspace. In this case #UD will be injected into the guestallowing guest OS to kill offending process and continue.
Signed-off-by: Gleb Natapov <gleb@redhat.com>...
kvm: enable smp > 1
Process INIT/SIPI requests and enable -smp > 1.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Avi Kivity <avi@redhat.com>
target-ppc: Remove duplicate cpu log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.
PPC: avoid function pointer type mismatch, spotted by clang
Fixes clang errors: CC ppc-softmmu/translate.o/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) {...
target-ppc: generic PowerPC TBL
Time base SPRs TBL/TBU should be accessible in user/priv modes for readingas specified in POWER ISA documentation. Therefore SPRs permissions werechanged in gen_tbl function.
Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>...
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-ppc: fix evsrwu and evsrws (second try)
target-ppc: fix evsrwu and evsrws
target-ppc: fix evslw instruction
KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load relatedsynchronization points in favor of four(!) generic hooks:
- cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave)...
Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if thiscode is never executed. Don't print an error message on the console,but keep the message in the log for debugging purposes....
target-ppc: stop translation after a trap instruction
target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,not extracted, and so used the wrong shift amounts to sign-extend or padwith zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bitposition. Because of this, the SPE evcmp* family of instructions wouldstore values in the result condition register that were also off by onebit position....
PPC: tell the guest about the time base frequency
Our guest systems need to know by how much the timebase increases every second,so there usually is a "timebase-frequency" property in the cpu leaf of thedevice tree.
This property is missing in OpenBIOS....
PPC: Fix large pages
We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviouslythat breaks, so let's just ignore 1TB SLB entries for now and instead do16MB pages correctly.
This fixes PPC64 Linux boot with -m above 256.
Signed-off-by: Alexander Graf <agraf@suse.de>...
PPC: Add timer when running KVM
For some odd reason we sometimes hang inside KVM forever. I'd guess it'sa race condition where we actually have a level triggered interrupt, butthe infrastructure can't expose that yet, so the guest ACKs it, goes tosleep and never gets notified that there's still an interrupt pending....
target-ppc: change DCR helpers to target_long arguments
The recent transition to always have the DCR helper functions take 32 bitvalues broke the PPC64 target, as target_long became 64 bits there.
This patch changes DCR helpers to target_long arguments, and cast the values...
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused byzone protection bits.
ppc-40x: Correct decoding of zone protection bits.
The 40x MMU has 15 zones in the ZPR register.
ppc-40x: Correct check for Endian swapping TLB entries.
Bailout on 40x TLB entries with endianess swapping only if the entryis valid.
ppc-40x: Get TLB attributes from TLBLO.
The ZSEL was incorrectly beeing decoded from TLBHI. Decode it fromTLBLO instead.
PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t topass it along the stacks.
This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, makingit compile without --disable-werror
PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBLshould return a 64-bit value on 64 bit implementations.
PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed usingtwo separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.
On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full64 bits as return value. If we only take the lower ones, fine. But Linux...
target-ppc: fix ppc32 kvm build
My segment sync patch broke compilation on PPC32, because it was trying tosync the SLB even though ppc32 CPUs don't have an SLB.
So let's only sync it when we're on a PP64 one!
target-ppc: Get MMU state on register sync
While x86 only needs to sync cr0-4 to know all about its MMU state and enableqemu to resolve virtual to physical addresses, we need to sync all of thesegment registers on PPC to know which mapping we're in.
So let's grab the segment register contents to be able to use the "x" monitor...
kvm: Add arch reset handler
Will be required by succeeding changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm ppc: Remove unused label
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
user: move CPU reset call to main.c for x86/PPC/Sparc
PPC: rename cpu_ppc_reset to cpu_reset for consistency
PPC: remove unneeded calls to device reset
target-ppc: move often used CPU fields at the top of the structure
target-ppc: simpler definitions for microcontrollers based on e300
No need to alias e300 core for each CPU package.Differences between microcontrollers have to be implemented in a higher layerthan translate_init.c
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>...
target-ppc: add declarations of microcontrollers based on e300
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E.
target-ppc: better support of e300 CPU core
Declare HID2 register.
Use high BATs for e300 (8 instead of 4).
Fix index of high BATs registers.Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: François Armand <francois.armand@os4i.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-ppc: log instructions start in TCG code
static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Unexport ticks_per_sec variable. Create get_ticks_per_sec() function
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'argument isn't self-explanatory. Simplify it by making it alwayssynchronize the kernel state into qemu, and automatically flush theregisters back to the kernel if they've been synchronized on this...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Replace REGX with PRIx64
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: add cpu_set_tls
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
target-ppc: add exceptions for conditional stores
target-ppc: fix cpu_clone_regs
We only need to make sure that the clone syscall looks like itsucceeded, not clobber 60% of the register set.