root / hw / arm / highbank.c @ 997aba8e
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/*
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* Calxeda Highbank SoC emulation
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*
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* Copyright (c) 2010-2012 Calxeda
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "hw/sysbus.h" |
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#include "hw/arm/arm.h" |
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#include "hw/devices.h" |
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#include "hw/loader.h" |
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#include "net/net.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/boards.h" |
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#include "sysemu/blockdev.h" |
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#include "exec/address-spaces.h" |
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#define SMP_BOOT_ADDR 0x100 |
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#define SMP_BOOT_REG 0x40 |
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#define GIC_BASE_ADDR 0xfff10000 |
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#define NIRQ_GIC 160 |
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/* Board init. */
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static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) |
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{ |
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int n;
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uint32_t smpboot[] = { |
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0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ |
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0xe210000f, /* ands r0, r0, #0x0f */ |
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0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ |
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0xe0830200, /* add r0, r3, r0, lsl #4 */ |
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0xe59f2024, /* ldr r2, privbase */ |
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0xe3a01001, /* mov r1, #1 */ |
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0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ |
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0xe3a010ff, /* mov r1, #0xff */ |
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0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ |
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0xf57ff04f, /* dsb */ |
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0xe320f003, /* wfi */ |
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0xe5901000, /* ldr r1, [r0] */ |
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0xe1110001, /* tst r1, r1 */ |
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0x0afffffb, /* beq <wfi> */ |
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0xe12fff11, /* bx r1 */ |
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GIC_BASE_ADDR /* privbase: gic address. */
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}; |
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
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smpboot[n] = tswap32(smpboot[n]); |
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} |
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); |
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} |
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static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) |
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{ |
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CPUARMState *env = &cpu->env; |
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switch (info->nb_cpus) {
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case 4: |
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stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0); |
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case 3: |
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stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0); |
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case 2: |
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stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0); |
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env->regs[15] = SMP_BOOT_ADDR;
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break;
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default:
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break;
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} |
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} |
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#define NUM_REGS 0x200 |
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static void hb_regs_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
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{ |
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uint32_t *regs = opaque; |
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if (offset == 0xf00) { |
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if (value == 1 || value == 2) { |
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qemu_system_reset_request(); |
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} else if (value == 3) { |
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qemu_system_shutdown_request(); |
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} |
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} |
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regs[offset/4] = value;
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} |
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static uint64_t hb_regs_read(void *opaque, hwaddr offset, |
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unsigned size)
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{ |
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uint32_t *regs = opaque; |
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uint32_t value = regs[offset/4];
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if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { |
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value |= 0x30000000;
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} |
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return value;
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} |
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static const MemoryRegionOps hb_mem_ops = { |
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.read = hb_regs_read, |
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.write = hb_regs_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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typedef struct { |
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SysBusDevice busdev; |
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MemoryRegion *iomem; |
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uint32_t regs[NUM_REGS]; |
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} HighbankRegsState; |
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static VMStateDescription vmstate_highbank_regs = {
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.name = "highbank-regs",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), |
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VMSTATE_END_OF_LIST(), |
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}, |
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}; |
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static void highbank_regs_reset(DeviceState *dev) |
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{ |
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SysBusDevice *sys_dev = SYS_BUS_DEVICE(dev); |
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HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev); |
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s->regs[0x40] = 0x05F20121; |
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s->regs[0x41] = 0x2; |
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s->regs[0x42] = 0x05F30121; |
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s->regs[0x43] = 0x05F40121; |
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} |
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static int highbank_regs_init(SysBusDevice *dev) |
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{ |
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HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev); |
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s->iomem = g_new(MemoryRegion, 1);
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memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
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0x1000);
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sysbus_init_mmio(dev, s->iomem); |
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return 0; |
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} |
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static void highbank_regs_class_init(ObjectClass *klass, void *data) |
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{ |
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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sbc->init = highbank_regs_init; |
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dc->desc = "Calxeda Highbank registers";
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dc->vmsd = &vmstate_highbank_regs; |
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dc->reset = highbank_regs_reset; |
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} |
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static const TypeInfo highbank_regs_info = { |
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.name = "highbank-regs",
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(HighbankRegsState),
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.class_init = highbank_regs_class_init, |
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}; |
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static void highbank_regs_register_types(void) |
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{ |
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type_register_static(&highbank_regs_info); |
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} |
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type_init(highbank_regs_register_types) |
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static struct arm_boot_info highbank_binfo; |
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/* ram_size must be set to match the upper bound of memory in the
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* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
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* normally 0xff900000 or -m 4089. When running this board on a
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* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
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* device tree and pass -m 2047 to QEMU.
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*/
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static void highbank_init(QEMUMachineInitArgs *args) |
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{ |
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ram_addr_t ram_size = args->ram_size; |
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const char *cpu_model = args->cpu_model; |
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const char *kernel_filename = args->kernel_filename; |
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const char *kernel_cmdline = args->kernel_cmdline; |
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const char *initrd_filename = args->initrd_filename; |
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DeviceState *dev; |
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SysBusDevice *busdev; |
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qemu_irq *irqp; |
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qemu_irq pic[128];
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int n;
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qemu_irq cpu_irq[4];
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MemoryRegion *sysram; |
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MemoryRegion *dram; |
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MemoryRegion *sysmem; |
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char *sysboot_filename;
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if (!cpu_model) {
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cpu_model = "cortex-a9";
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} |
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for (n = 0; n < smp_cpus; n++) { |
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ARMCPU *cpu; |
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cpu = cpu_arm_init(cpu_model); |
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if (cpu == NULL) { |
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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} |
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/* This will become a QOM property eventually */
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cpu->reset_cbar = GIC_BASE_ADDR; |
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irqp = arm_pic_init_cpu(cpu); |
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cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
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} |
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sysmem = get_system_memory(); |
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dram = g_new(MemoryRegion, 1);
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memory_region_init_ram(dram, "highbank.dram", ram_size);
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/* SDRAM at address zero. */
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memory_region_add_subregion(sysmem, 0, dram);
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sysram = g_new(MemoryRegion, 1);
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memory_region_init_ram(sysram, "highbank.sysram", 0x8000); |
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memory_region_add_subregion(sysmem, 0xfff88000, sysram);
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if (bios_name != NULL) { |
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sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
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if (sysboot_filename != NULL) { |
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uint32_t filesize = get_image_size(sysboot_filename); |
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if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) { |
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hw_error("Unable to load %s\n", bios_name);
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} |
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} else {
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hw_error("Unable to find %s\n", bios_name);
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} |
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} |
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dev = qdev_create(NULL, "a9mpcore_priv"); |
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
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qdev_init_nofail(dev); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
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for (n = 0; n < smp_cpus; n++) { |
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sysbus_connect_irq(busdev, n, cpu_irq[n]); |
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} |
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for (n = 0; n < 128; n++) { |
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pic[n] = qdev_get_gpio_in(dev, n); |
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} |
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dev = qdev_create(NULL, "l2x0"); |
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qdev_init_nofail(dev); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_mmio_map(busdev, 0, 0xfff12000); |
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dev = qdev_create(NULL, "sp804"); |
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qdev_prop_set_uint32(dev, "freq0", 150000000); |
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qdev_prop_set_uint32(dev, "freq1", 150000000); |
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qdev_init_nofail(dev); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_mmio_map(busdev, 0, 0xfff34000); |
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sysbus_connect_irq(busdev, 0, pic[18]); |
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sysbus_create_simple("pl011", 0xfff36000, pic[20]); |
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dev = qdev_create(NULL, "highbank-regs"); |
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qdev_init_nofail(dev); |
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busdev = SYS_BUS_DEVICE(dev); |
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sysbus_mmio_map(busdev, 0, 0xfff3c000); |
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sysbus_create_simple("pl061", 0xfff30000, pic[14]); |
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sysbus_create_simple("pl061", 0xfff31000, pic[15]); |
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sysbus_create_simple("pl061", 0xfff32000, pic[16]); |
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sysbus_create_simple("pl061", 0xfff33000, pic[17]); |
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sysbus_create_simple("pl031", 0xfff35000, pic[19]); |
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sysbus_create_simple("pl022", 0xfff39000, pic[23]); |
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sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]); |
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if (nd_table[0].used) { |
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qemu_check_nic_model(&nd_table[0], "xgmac"); |
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dev = qdev_create(NULL, "xgmac"); |
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qdev_set_nic_properties(dev, &nd_table[0]);
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qdev_init_nofail(dev); |
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); |
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qemu_check_nic_model(&nd_table[1], "xgmac"); |
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dev = qdev_create(NULL, "xgmac"); |
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qdev_set_nic_properties(dev, &nd_table[1]);
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qdev_init_nofail(dev); |
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); |
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); |
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} |
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highbank_binfo.ram_size = ram_size; |
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highbank_binfo.kernel_filename = kernel_filename; |
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highbank_binfo.kernel_cmdline = kernel_cmdline; |
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highbank_binfo.initrd_filename = initrd_filename; |
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/* highbank requires a dtb in order to boot, and the dtb will override
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* the board ID. The following value is ignored, so set it to -1 to be
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* clear that the value is meaningless.
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*/
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highbank_binfo.board_id = -1;
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highbank_binfo.nb_cpus = smp_cpus; |
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highbank_binfo.loader_start = 0;
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highbank_binfo.write_secondary_boot = hb_write_secondary; |
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highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; |
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arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo); |
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} |
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static QEMUMachine highbank_machine = {
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.name = "highbank",
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.desc = "Calxeda Highbank (ECX-1000)",
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.init = highbank_init, |
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.block_default_type = IF_SCSI, |
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.max_cpus = 4,
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DEFAULT_MACHINE_OPTIONS, |
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}; |
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static void highbank_machine_init(void) |
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{ |
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qemu_register_machine(&highbank_machine); |
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} |
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machine_init(highbank_machine_init); |