Archipelago » qemu

TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

static int nb_tbs;

/* any access to the tbs or the page table must use this lock */

#if defined(__arm__) || defined(__sparc_v9__)

/* The prologue must be reachable with a direct jump. ARM and Sparc64

typedef struct RAMBlock {

    uint8_t *host;

    struct RAMBlock *next;

} RAMBlock;

/* TODO: When we implement (and use) ram deallocation (e.g. for hotplug)

   then we can no longer assume contiguous ram offsets, and external uses

   of this variable will break.  */

#endif

CPUState *first_cpu;

typedef struct PhysPageDesc {

    /* offset in host memory of the page + io_index in the low bits */

} PhysPageDesc;

#define L2_BITS 10

static int tb_phys_invalidate_count;

#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)

    CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4];

    CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4];

    void *opaque[TARGET_PAGE_SIZE][2][4];

#ifdef _WIN32

static void map_exec(void *addr, long size)

    return p + (index & (L2_SIZE - 1));

}

{

    void **lp, **p;

    PhysPageDesc *pd;

    return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));

}

{

    return phys_page_find_alloc(index, 0);

}

#if !defined(CONFIG_USER_ONLY)

                                    target_ulong vaddr);

#define mmap_lock() do { } while(0)

#define mmap_unlock() do { } while(0)

    CPUState *env;

    PageDesc *p;

    unsigned int h, n1;

    TranslationBlock *tb1, *tb2;

    /* remove the TB from the hash list */

   the same physical page. 'is_cpu_write_access' should be true if called

   from a real cpu write access: the virtual CPU will exit the current

   TB if code is modified inside this TB. */

                                   int is_cpu_write_access)

{

    TranslationBlock *tb, *tb_next, *saved_tb;

}

/* len must be <= 8 and start must be a multiple of len */

{

    PageDesc *p;

    int offset, b;

}

#if !defined(CONFIG_SOFTMMU)

                                    unsigned long pc, void *puc)

{

    TranslationBlock *tb;

#if defined(TARGET_HAS_ICE)

static void breakpoint_invalidate(CPUState *env, target_ulong pc)

{

    target_ulong pd;

    PhysPageDesc *p;

    addr = cpu_get_phys_page_debug(env, pc);

       signals are used primarily to interrupt blocking syscalls.  */

#else

    TranslationBlock *tb;

    tb = env->current_tb;

    /* if the cpu is currently executing code, we must unlink it and

/* update the TLBs so that writes to code in the virtual page 'addr'

   can be detected */

{

    cpu_physical_memory_reset_dirty(ram_addr,

                                    ram_addr + TARGET_PAGE_SIZE,

/* update the TLB so that writes in physical page 'phys_addr' are no longer

   tested for self modifying code */

                                    target_ulong vaddr)

{

    phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;

}

/* Note: start and end must be within the same ram block.  */

                                     int dirty_flags)

{

    CPUState *env;

    return in_migration;

}

{

    int ret = 0;

static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)

{

    void *p;

    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {

   (can only happen in non SOFTMMU mode for I/O pages or pages

   conflicting with the host address space). */

int tlb_set_page_exec(CPUState *env, target_ulong vaddr,

                      int mmu_idx, int is_softmmu)

{

    PhysPageDesc *p;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    int ret;

    CPUTLBEntry *te;

    CPUWatchpoint *wp;

    p = phys_page_find(paddr >> TARGET_PAGE_BITS);

    if (!p) {

}

int tlb_set_page_exec(CPUState *env, target_ulong vaddr,

                      int mmu_idx, int is_softmmu)

{

    return 0;

#if !defined(CONFIG_USER_ONLY)

#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \

                      need_subpage)                                     \

    do {                                                                \

   start_addr and region_offset are rounded down to a page boundary

   before calculating this offset.  This should not be a problem unless

   the low bits of start_addr and region_offset differ.  */

{

    PhysPageDesc *p;

    CPUState *env;

    void *subpage;

    if (kvm_enabled())

    }

    region_offset &= TARGET_PAGE_MASK;

    size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;

    for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {

        p = phys_page_find(addr >> TARGET_PAGE_BITS);

        if (p && p->phys_offset != IO_MEM_UNASSIGNED) {

            int need_subpage = 0;

            CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,

                (phys_offset & IO_MEM_ROMD)) {

                phys_offset += TARGET_PAGE_SIZE;

            } else {

                int need_subpage = 0;

                CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,

}

/* XXX: temporary until new memory mapping API */

{

    PhysPageDesc *p;

    return p->phys_offset;

}

{

    if (kvm_enabled())

        kvm_coalesce_mmio_region(addr, size);

}

{

    if (kvm_enabled())

        kvm_uncoalesce_mmio_region(addr, size);

}

{

    RAMBlock *new_block;

    return new_block->offset;

}

{

    /* TODO: implement this.  */

}

   It should not be used for general purpose DMA.

   Use cpu_physical_memory_map/cpu_physical_memory_rw instead.

 */

{

    RAMBlock *prev;

    RAMBlock **prevp;

/* Some of the softmmu routines need to translate from a host pointer

   (typically a TLB entry) back to a ram offset.  */

{

    RAMBlock *prev;

    RAMBlock **prevp;

    return block->offset + (host - block->host);

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);

    return 0;

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);

    return 0;

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);

    return 0;

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);

#endif

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);

#endif

}

{

#ifdef DEBUG_UNASSIGNED

    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);

    unassigned_mem_writel,

};

                                uint32_t val)

{

    int dirty_flags;

        tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);

}

                                uint32_t val)

{

    int dirty_flags;

        tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);

}

                                uint32_t val)

{

    int dirty_flags;

/* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,

   so these check for a hit then pass through to the normal out-of-line

   phys routines.  */

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);

    return ldub_phys(addr);

}

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);

    return lduw_phys(addr);

}

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);

    return ldl_phys(addr);

}

                             uint32_t val)

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);

    stb_phys(addr, val);

}

                             uint32_t val)

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);

    stw_phys(addr, val);

}

                             uint32_t val)

{

    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);

    watch_mem_writel,

};

                                 unsigned int len)

{

    uint32_t ret;

    return ret;

}

                              uint32_t value, unsigned int len)

{

    unsigned int idx;

                                  value);

}

{

#if defined(DEBUG_SUBPAGE)

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

    return subpage_readlen(opaque, addr, 0);

}

                            uint32_t value)

{

#if defined(DEBUG_SUBPAGE)

    subpage_writelen(opaque, addr, value, 0);

}

{

#if defined(DEBUG_SUBPAGE)

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

    return subpage_readlen(opaque, addr, 1);

}

                            uint32_t value)

{

#if defined(DEBUG_SUBPAGE)

    subpage_writelen(opaque, addr, value, 1);

}

{

#if defined(DEBUG_SUBPAGE)

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

}

static void subpage_writel (void *opaque,

{

#if defined(DEBUG_SUBPAGE)

    printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);

    &subpage_writel,

};

{

    int idx, eidx;

    unsigned int i;

    return 0;

}

{

    int subpage_memory;

    mmio->base = base;

    subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);

/* physical memory access (slow version, mainly for debug) */

#if defined(CONFIG_USER_ONLY)

                            int len, int is_write)

{

    int l, flags;

}

#else

                            int len, int is_write)

{

    int l, io_index;

    uint8_t *ptr;

    uint32_t val;

    unsigned long pd;

    PhysPageDesc *p;

        if (is_write) {

            if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {

                io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);

                if (p)

                    addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;

        } else {

            if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&

                !(pd & IO_MEM_ROMD)) {

                /* I/O case */

                io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);

                if (p)

}

/* used for ROM loading : can write in RAM and ROM */

                                   const uint8_t *buf, int len)

{

    int l;

    uint8_t *ptr;

    unsigned long pd;

    PhysPageDesc *p;

typedef struct {

    void *buffer;

} BounceBuffer;

static BounceBuffer bounce;

 * Use cpu_register_map_client() to know when retrying the map operation is

 * likely to succeed.

 */

                              int is_write)

{

    int l;

    uint8_t *ret = NULL;

    uint8_t *ptr;

    unsigned long pd;

    PhysPageDesc *p;

    unsigned long addr1;

 * Will also mark the memory as dirty if is_write == 1.  access_len gives

 * the amount of memory that was actually read or written by the caller.

 */

{

    if (buffer != bounce.buffer) {

        if (is_write) {

            while (access_len) {

                unsigned l;

                l = TARGET_PAGE_SIZE;

}

/* warning: addr must be aligned */

{

    int io_index;

    uint8_t *ptr;

}

/* warning: addr must be aligned */

{

    int io_index;

    uint8_t *ptr;

}

/* XXX: optimize */

{

    uint8_t val;

    cpu_physical_memory_read(addr, &val, 1);

}

/* XXX: optimize */

{

    uint16_t val;

    cpu_physical_memory_read(addr, (uint8_t *)&val, 2);

/* warning: addr must be aligned. The ram page is not masked as dirty

   and the code inside is not invalidated. It is useful if the dirty

   bits are used to track modified PTEs */

{

    int io_index;

    uint8_t *ptr;

    }

}

{

    int io_index;

    uint8_t *ptr;

}

/* warning: addr must be aligned */

{

    int io_index;

    uint8_t *ptr;

}

/* XXX: optimize */

{

    uint8_t v = val;

    cpu_physical_memory_write(addr, &v, 1);

}

/* XXX: optimize */

{

    uint16_t v = tswap16(val);

    cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);

}

/* XXX: optimize */

{

    val = tswap64(val);

    cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);

                        uint8_t *buf, int len, int is_write)

{

    int l;

    target_ulong page;

    while (len > 0) {