Revision 99a0949b hw/arm_timer.c
| b/hw/arm_timer.c | ||
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} |
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} |
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static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset)
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{
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arm_timer_state *s = (arm_timer_state *)opaque; |
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ptimer_set_limit(s->timer, limit, reload); |
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} |
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static void arm_timer_write(void *opaque, target_phys_addr_t offset,
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static void arm_timer_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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arm_timer_state *s = (arm_timer_state *)opaque; |
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qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
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} |
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static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
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static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
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{
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sp804_state *s = (sp804_state *)opaque; |
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} |
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} |
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static void sp804_write(void *opaque, target_phys_addr_t offset,
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static void sp804_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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sp804_state *s = (sp804_state *)opaque; |
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arm_timer_state *timer[3]; |
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} icp_pit_state; |
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static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
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static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
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{
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icp_pit_state *s = (icp_pit_state *)opaque; |
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int n; |
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return arm_timer_read(s->timer[n], offset & 0xff); |
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} |
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static void icp_pit_write(void *opaque, target_phys_addr_t offset,
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static void icp_pit_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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icp_pit_state *s = (icp_pit_state *)opaque; |
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