Revision 99a0949b hw/e1000.c
b/hw/e1000.c | ||
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} |
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static uint32_t |
481 |
txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
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txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
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{ |
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uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); |
484 | 484 |
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... | ... | |
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static void |
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start_xmit(E1000State *s) |
497 | 497 |
{ |
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target_phys_addr_t base;
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a_target_phys_addr base;
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499 | 499 |
struct e1000_tx_desc desc; |
500 | 500 |
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; |
501 | 501 |
|
... | ... | |
613 | 613 |
{ |
614 | 614 |
E1000State *s = vc->opaque; |
615 | 615 |
struct e1000_rx_desc desc; |
616 |
target_phys_addr_t base;
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a_target_phys_addr base;
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617 | 617 |
unsigned int n, rdt; |
618 | 618 |
uint32_t rdh_start; |
619 | 619 |
uint16_t vlan_special = 0; |
... | ... | |
814 | 814 |
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) }; |
815 | 815 |
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816 | 816 |
static void |
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e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
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818 | 818 |
{ |
819 | 819 |
E1000State *s = opaque; |
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unsigned int index = (addr & 0x1ffff) >> 2; |
... | ... | |
832 | 832 |
} |
833 | 833 |
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static void |
835 |
e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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835 |
e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
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836 | 836 |
{ |
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// emulate hw without byte enables: no RMW |
838 | 838 |
e1000_mmio_writel(opaque, addr & ~3, |
... | ... | |
840 | 840 |
} |
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842 | 842 |
static void |
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e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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844 | 844 |
{ |
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// emulate hw without byte enables: no RMW |
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e1000_mmio_writel(opaque, addr & ~3, |
... | ... | |
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} |
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850 | 850 |
static uint32_t |
851 |
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
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851 |
e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
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852 | 852 |
{ |
853 | 853 |
E1000State *s = opaque; |
854 | 854 |
unsigned int index = (addr & 0x1ffff) >> 2; |
... | ... | |
866 | 866 |
} |
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868 | 868 |
static uint32_t |
869 |
e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
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e1000_mmio_readb(void *opaque, a_target_phys_addr addr)
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870 | 870 |
{ |
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return ((e1000_mmio_readl(opaque, addr & ~3)) >> |
872 | 872 |
(8 * (addr & 3))) & 0xff; |
873 | 873 |
} |
874 | 874 |
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875 | 875 |
static uint32_t |
876 |
e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
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e1000_mmio_readw(void *opaque, a_target_phys_addr addr)
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877 | 877 |
{ |
878 | 878 |
return ((e1000_mmio_readl(opaque, addr & ~3)) >> |
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(8 * (addr & 3))) & 0xffff; |
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