Revision 99a0949b hw/flash.h

b/hw/flash.h
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/* NOR flash devices */
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typedef struct pflash_t pflash_t;
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typedef struct pflash a_pflash;
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/* pflash_cfi01.c */


  		





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pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,


  		





  
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a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,


  		





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                                BlockDriverState *bs,


  		





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                                uint32_t sector_len, int nb_blocs, int width,


  		





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                                uint16_t id0, uint16_t id1,


  		





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                                uint16_t id2, uint16_t id3);


  		





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/* pflash_cfi02.c */


  		





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pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,


  		





  
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a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,


  		





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                                BlockDriverState *bs, uint32_t sector_len,


  		





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                                int nb_blocs, int nb_mappings, int width,


  		





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                                uint16_t id0, uint16_t id1,


  		





  ......




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#define NAND_MFR_MICRON		0x2c


  		





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/* onenand.c */


  		





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void onenand_base_update(void *opaque, target_phys_addr_t new);


  		





  
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void onenand_base_update(void *opaque, a_target_phys_addr new);


  		





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void onenand_base_unmap(void *opaque);


  		





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void *onenand_init(uint32_t id, int regshift, qemu_irq irq);


  		





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void *onenand_raw_otp(void *opaque);


  		












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