Revision 99a0949b hw/g364fb.c
| b/hw/g364fb.c | ||
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| 36 | 36 |
typedef struct G364State {
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| 37 | 37 |
/* hardware */ |
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uint8_t *vram; |
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ram_addr_t vram_offset;
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a_ram_addr vram_offset;
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int vram_size; |
| 41 | 41 |
qemu_irq irq; |
| 42 | 42 |
/* registers */ |
| ... | ... | |
| 68 | 68 |
#define CTLA_FORCE_BLANK 0x00000400 |
| 69 | 69 |
#define CTLA_NO_CURSOR 0x00800000 |
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static inline int check_dirty(ram_addr_t page)
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static inline int check_dirty(a_ram_addr page)
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{
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return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
| 74 | 74 |
} |
| 75 | 75 |
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static inline void reset_dirty(G364State *s, |
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ram_addr_t page_min, ram_addr_t page_max)
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a_ram_addr page_min, a_ram_addr page_max)
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{
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1, |
| 80 | 80 |
VGA_DIRTY_FLAG); |
| ... | ... | |
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int i, w; |
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uint8_t *vram; |
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uint8_t *data_display, *dd; |
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ram_addr_t page, page_min, page_max;
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a_ram_addr page, page_min, page_max;
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int x, y; |
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int xmin, xmax; |
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int ymin, ymax; |
| ... | ... | |
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} |
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page = s->vram_offset; |
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page_min = (ram_addr_t)-1;
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page_min = (a_ram_addr)-1;
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page_max = 0; |
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x = y = 0; |
| ... | ... | |
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if (check_dirty(page)) {
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if (y < ymin) |
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ymin = ymax = y; |
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if (page_min == (ram_addr_t)-1)
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if (page_min == (a_ram_addr)-1)
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page_min = page; |
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page_max = page; |
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if (x < xmin) |
| ... | ... | |
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ymax = y; |
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} else {
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int dy; |
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if (page_min != (ram_addr_t)-1) {
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if (page_min != (a_ram_addr)-1) {
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reset_dirty(s, page_min, page_max); |
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page_min = (ram_addr_t)-1;
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page_min = (a_ram_addr)-1;
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page_max = 0; |
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
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xmin = s->width; |
| ... | ... | |
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} |
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done: |
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if (page_min != (ram_addr_t)-1) {
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if (page_min != (a_ram_addr)-1) {
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
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reset_dirty(s, page_min, page_max); |
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} |
| ... | ... | |
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} |
| 337 | 337 |
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/* called for accesses to io ports */ |
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static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
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static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
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{
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G364State *s = opaque; |
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uint32_t val; |
| ... | ... | |
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return val; |
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} |
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static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
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{
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uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3); |
| 385 | 385 |
if (addr & 0x2) |
| ... | ... | |
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return v & 0xffff; |
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} |
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static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t g364fb_ctrl_readb(void *opaque, a_target_phys_addr addr)
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{
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uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3); |
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return (v >> (8 * (addr & 0x3))) & 0xff; |
| ... | ... | |
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} |
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} |
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static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
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{
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G364State *s = opaque; |
| 421 | 421 |
|
| ... | ... | |
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qemu_irq_lower(s->irq); |
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} |
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static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
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{
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uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3); |
| 496 | 496 |
|
| ... | ... | |
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g364fb_ctrl_writel(opaque, addr & ~0x3, val); |
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} |
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static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void g364fb_ctrl_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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{
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uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3); |
| 507 | 507 |
|
| ... | ... | |
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qemu_put_be32(f, s->height); |
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} |
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int g364fb_mm_init(target_phys_addr_t vram_base,
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target_phys_addr_t ctrl_base, int it_shift,
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int g364fb_mm_init(a_target_phys_addr vram_base,
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a_target_phys_addr ctrl_base, int it_shift,
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qemu_irq irq) |
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{
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G364State *s; |
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