Revision 99a0949b hw/integratorcp.c
| b/hw/integratorcp.c | ||
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
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static uint32_t integratorcm_read(void *opaque, a_target_phys_addr offset)
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
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if (offset >= 0x100 && offset < 0x200) {
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| ... | ... | |
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hw_error("Core module interrupt\n");
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} |
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static void integratorcm_write(void *opaque, target_phys_addr_t offset,
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static void integratorcm_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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integratorcm_state *s = (integratorcm_state *)opaque; |
| ... | ... | |
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icp_pic_update(s); |
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} |
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static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
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static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
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| ... | ... | |
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} |
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} |
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static void icp_pic_write(void *opaque, target_phys_addr_t offset,
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static void icp_pic_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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icp_pic_state *s = (icp_pic_state *)opaque; |
| ... | ... | |
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} |
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/* CP control registers. */ |
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static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
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static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
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{
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switch (offset >> 2) {
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case 0: /* CP_IDFIELD */ |
| ... | ... | |
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} |
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} |
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static void icp_control_write(void *opaque, target_phys_addr_t offset,
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static void icp_control_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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switch (offset >> 2) {
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| ... | ... | |
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.board_id = 0x113, |
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}; |
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static void integratorcp_init(ram_addr_t ram_size,
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static void integratorcp_init(a_ram_addr ram_size,
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const char *boot_device, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
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{
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CPUState *env; |
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ram_addr_t ram_offset;
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a_ram_addr ram_offset;
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qemu_irq pic[32]; |
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qemu_irq *cpu_pic; |
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DeviceState *dev; |
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