Revision 99a0949b hw/m48t59.c
| b/hw/m48t59.c | ||
|---|---|---|
| 41 | 41 |
* alarm and a watchdog timer and related control registers. In the |
| 42 | 42 |
* PPC platform there is also a nvram lock function. |
| 43 | 43 |
*/ |
| 44 |
struct m48t59_t {
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struct m48t59 {
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| 45 | 45 |
/* Model parameters */ |
| 46 | 46 |
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 |
| 47 | 47 |
/* Hardware parameters */ |
| ... | ... | |
| 63 | 63 |
|
| 64 | 64 |
typedef struct M48t59ISAState {
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| 65 | 65 |
ISADevice busdev; |
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m48t59_t state;
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a_m48t59 state;
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| 67 | 67 |
} M48t59ISAState; |
| 68 | 68 |
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| 69 | 69 |
typedef struct M48t59SysBusState {
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| 70 | 70 |
SysBusDevice busdev; |
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m48t59_t state;
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a_m48t59 state;
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| 72 | 72 |
} M48t59SysBusState; |
| 73 | 73 |
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/* Fake timer functions */ |
| ... | ... | |
| 88 | 88 |
{
|
| 89 | 89 |
struct tm tm; |
| 90 | 90 |
uint64_t next_time; |
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 92 | 92 |
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| 93 | 93 |
qemu_set_irq(NVRAM->IRQ, 1); |
| 94 | 94 |
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
| ... | ... | |
| 130 | 130 |
qemu_set_irq(NVRAM->IRQ, 0); |
| 131 | 131 |
} |
| 132 | 132 |
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static void set_alarm (m48t59_t *NVRAM)
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static void set_alarm (a_m48t59 *NVRAM)
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| 134 | 134 |
{
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int diff; |
| 136 | 136 |
if (NVRAM->alrm_timer != NULL) {
|
| ... | ... | |
| 142 | 142 |
} |
| 143 | 143 |
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| 144 | 144 |
/* RTC management helpers */ |
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static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
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static inline void get_time (a_m48t59 *NVRAM, struct tm *tm)
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{
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qemu_get_timedate(tm, NVRAM->time_offset); |
| 148 | 148 |
} |
| 149 | 149 |
|
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static void set_time (m48t59_t *NVRAM, struct tm *tm)
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static void set_time (a_m48t59 *NVRAM, struct tm *tm)
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{
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NVRAM->time_offset = qemu_timedate_diff(tm); |
| 153 | 153 |
set_alarm(NVRAM); |
| ... | ... | |
| 156 | 156 |
/* Watchdog management */ |
| 157 | 157 |
static void watchdog_cb (void *opaque) |
| 158 | 158 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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NVRAM->buffer[0x1FF0] |= 0x80; |
| 162 | 162 |
if (NVRAM->buffer[0x1FF7] & 0x80) {
|
| ... | ... | |
| 170 | 170 |
} |
| 171 | 171 |
} |
| 172 | 172 |
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
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static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
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{
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uint64_t interval; /* in 1/16 seconds */ |
| 176 | 176 |
|
| ... | ... | |
| 188 | 188 |
/* Direct access to NVRAM */ |
| 189 | 189 |
void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
| 190 | 190 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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struct tm tm; |
| 193 | 193 |
int tmp; |
| 194 | 194 |
|
| ... | ... | |
| 356 | 356 |
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| 357 | 357 |
uint32_t m48t59_read (void *opaque, uint32_t addr) |
| 358 | 358 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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struct tm tm; |
| 361 | 361 |
uint32_t retval = 0xFF; |
| 362 | 362 |
|
| ... | ... | |
| 463 | 463 |
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| 464 | 464 |
void m48t59_set_addr (void *opaque, uint32_t addr) |
| 465 | 465 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 467 | 467 |
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NVRAM->addr = addr; |
| 469 | 469 |
} |
| 470 | 470 |
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void m48t59_toggle_lock (void *opaque, int lock) |
| 472 | 472 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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NVRAM->lock ^= 1 << lock; |
| 476 | 476 |
} |
| ... | ... | |
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/* IO access to NVRAM */ |
| 479 | 479 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 480 | 480 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 482 | 482 |
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addr -= NVRAM->io_base; |
| 484 | 484 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
| ... | ... | |
| 502 | 502 |
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static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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uint32_t retval; |
| 507 | 507 |
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addr -= NVRAM->io_base; |
| ... | ... | |
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return retval; |
| 520 | 520 |
} |
| 521 | 521 |
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value)
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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m48t59_write(NVRAM, addr, value & 0xff); |
| 527 | 527 |
} |
| 528 | 528 |
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static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
| 534 | 534 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
| 535 | 535 |
} |
| 536 | 536 |
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static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 540 | 540 |
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m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
| 542 | 542 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
| ... | ... | |
| 544 | 544 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
| 545 | 545 |
} |
| 546 | 546 |
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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uint32_t retval; |
| 551 | 551 |
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retval = m48t59_read(NVRAM, addr); |
| 553 | 553 |
return retval; |
| 554 | 554 |
} |
| 555 | 555 |
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static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
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static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
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{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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uint32_t retval; |
| 560 | 560 |
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retval = m48t59_read(NVRAM, addr) << 8; |
| ... | ... | |
| 563 | 563 |
return retval; |
| 564 | 564 |
} |
| 565 | 565 |
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static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
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static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
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| 567 | 567 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 569 | 569 |
uint32_t retval; |
| 570 | 570 |
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retval = m48t59_read(NVRAM, addr) << 24; |
| ... | ... | |
| 589 | 589 |
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| 590 | 590 |
static void m48t59_save(QEMUFile *f, void *opaque) |
| 591 | 591 |
{
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m48t59_t *s = opaque;
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a_m48t59 *s = opaque;
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| 593 | 593 |
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qemu_put_8s(f, &s->lock); |
| 595 | 595 |
qemu_put_be16s(f, &s->addr); |
| ... | ... | |
| 598 | 598 |
|
| 599 | 599 |
static int m48t59_load(QEMUFile *f, void *opaque, int version_id) |
| 600 | 600 |
{
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m48t59_t *s = opaque;
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a_m48t59 *s = opaque;
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| 602 | 602 |
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| 603 | 603 |
if (version_id != 1) |
| 604 | 604 |
return -EINVAL; |
| ... | ... | |
| 612 | 612 |
|
| 613 | 613 |
static void m48t59_reset(void *opaque) |
| 614 | 614 |
{
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m48t59_t *NVRAM = opaque;
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a_m48t59 *NVRAM = opaque;
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| 616 | 616 |
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| 617 | 617 |
NVRAM->addr = 0; |
| 618 | 618 |
NVRAM->lock = 0; |
| ... | ... | |
| 624 | 624 |
} |
| 625 | 625 |
|
| 626 | 626 |
/* Initialisation routine */ |
| 627 |
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
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a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
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| 628 | 628 |
uint32_t io_base, uint16_t size, |
| 629 | 629 |
int type) |
| 630 | 630 |
{
|
| ... | ... | |
| 652 | 652 |
return &d->state; |
| 653 | 653 |
} |
| 654 | 654 |
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m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
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a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
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| 656 | 656 |
{
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| 657 | 657 |
M48t59ISAState *d; |
| 658 | 658 |
ISADevice *dev; |
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m48t59_t *s;
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a_m48t59 *s;
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| 660 | 660 |
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| 661 | 661 |
dev = isa_create("m48t59_isa");
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| 662 | 662 |
qdev_prop_set_uint32(&dev->qdev, "type", type); |
| ... | ... | |
| 674 | 674 |
return s; |
| 675 | 675 |
} |
| 676 | 676 |
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static void m48t59_init_common(m48t59_t *s)
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| 677 |
static void m48t59_init_common(a_m48t59 *s)
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| 678 | 678 |
{
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| 679 | 679 |
s->buffer = qemu_mallocz(s->size); |
| 680 | 680 |
if (s->type == 59) {
|
| ... | ... | |
| 690 | 690 |
static int m48t59_init_isa1(ISADevice *dev) |
| 691 | 691 |
{
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| 692 | 692 |
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
| 693 |
m48t59_t *s = &d->state;
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a_m48t59 *s = &d->state;
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| 694 | 694 |
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| 695 | 695 |
isa_init_irq(dev, &s->IRQ, 8); |
| 696 | 696 |
m48t59_init_common(s); |
| ... | ... | |
| 701 | 701 |
static int m48t59_init1(SysBusDevice *dev) |
| 702 | 702 |
{
|
| 703 | 703 |
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
| 704 |
m48t59_t *s = &d->state;
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| 704 |
a_m48t59 *s = &d->state;
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| 705 | 705 |
int mem_index; |
| 706 | 706 |
|
| 707 | 707 |
sysbus_init_irq(dev, &s->IRQ); |
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