Revision 99a0949b hw/mcf5208.c
b/hw/mcf5208.c | ||
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qemu_irq_lower(s->irq); |
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} |
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static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
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static void m5208_timer_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{ |
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m5208_timer_state *s = (m5208_timer_state *)opaque; |
... | ... | |
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m5208_timer_update(s); |
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} |
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static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
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static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr)
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{ |
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m5208_timer_state *s = (m5208_timer_state *)opaque; |
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switch (addr) { |
... | ... | |
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m5208_timer_write |
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}; |
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static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
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static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
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{ |
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switch (addr) { |
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case 0x110: /* SDCS0 */ |
... | ... | |
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} |
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} |
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static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
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static void m5208_sys_write(void *opaque, a_target_phys_addr addr,
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uint32_t value) |
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{ |
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hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); |
... | ... | |
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} |
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} |
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static void mcf5208evb_init(ram_addr_t ram_size,
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static void mcf5208evb_init(a_ram_addr ram_size,
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const char *boot_device, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
... | ... | |
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CPUState *env; |
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int kernel_size; |
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uint64_t elf_entry; |
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target_phys_addr_t entry;
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a_target_phys_addr entry;
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qemu_irq *pic; |
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if (!cpu_model) |
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