Revision 99a0949b hw/mips_jazz.c
| b/hw/mips_jazz.c | ||
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cpu_reset(env); |
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} |
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static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t rtc_readb(void *opaque, a_target_phys_addr addr)
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{
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return cpu_inw(0x71); |
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} |
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static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void rtc_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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{
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cpu_outw(0x71, val & 0xff); |
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} |
| ... | ... | |
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rtc_writeb, |
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}; |
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static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void dma_dummy_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
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{
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/* Nothing to do. That is only to ensure that |
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* the current DMA acknowledge cycle is completed. */ |
| ... | ... | |
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#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) |
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static |
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void mips_jazz_init (ram_addr_t ram_size,
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void mips_jazz_init (a_ram_addr ram_size,
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const char *cpu_model, |
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enum jazz_model_e jazz_model) |
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{
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| ... | ... | |
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PITState *pit; |
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BlockDriverState *fds[MAX_FD]; |
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qemu_irq esp_reset; |
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ram_addr_t ram_offset;
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ram_addr_t bios_offset;
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a_ram_addr ram_offset;
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a_ram_addr bios_offset;
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/* init CPUs */ |
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if (cpu_model == NULL) {
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| ... | ... | |
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} |
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static |
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void mips_magnum_init (ram_addr_t ram_size,
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void mips_magnum_init (a_ram_addr ram_size,
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const char *boot_device, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
| ... | ... | |
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} |
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static |
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void mips_pica61_init (ram_addr_t ram_size,
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void mips_pica61_init (a_ram_addr ram_size,
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const char *boot_device, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
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