Archipelago » qemu

/* omap[123].c */

struct omap_l4_s;

struct omap_target_agent_s;

struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);

                int iotype);

# define l4_register_io_memory	cpu_register_io_memory

struct omap_intr_handler_s;

                unsigned long size, unsigned char nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);

                int size, int nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq,

                omap_clk fclk, omap_clk iclk);

                omap_clk iclk, struct omap_mpu_state_s *mpu);

struct omap_sdrc_s;

struct omap_gpmc_s;

void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,

                void (*unmap)(void *opaque), void *opaque);

/*

};

struct soc_dma_s;

                qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,

                enum omap_dma_model model);

                struct omap_mpu_state_s *mpu, int fifo,

                int chans, omap_clk iclk, omap_clk fclk);

void omap_dma_reset(struct soc_dma_s *s);

    post_incremented,

    single_index,

    double_index,

/* Only used in OMAP DMA 3.x gigacells */

struct omap_dma_lcd_channel_s {

    enum omap_dma_port src;

    /* Used in OMAP DMA 3.2 gigacell */

    unsigned char brust_f1;

    uint16_t frames_f1;

    uint16_t elements_f2;

    uint16_t frames_f2;

    /* Destination port is fixed.  */

    int interrupts;

    int dual;

    int current_frame;

    qemu_irq irq;

    struct omap_mpu_state_s *mpu;

} *omap_dma_get_lcdch(struct soc_dma_s *s);

/* omap[123].c */

struct omap_mpu_timer_s;

                qemu_irq irq, omap_clk clk);

struct omap_gp_timer_s;

                qemu_irq irq, omap_clk fclk, omap_clk iclk);

struct omap_watchdog_timer_s;

                qemu_irq irq, omap_clk clk);

struct omap_32khz_timer_s;

                qemu_irq irq, omap_clk clk);

void omap_synctimer_init(struct omap_target_agent_s *ta,

                struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);

struct omap_tipb_bridge_s;

                qemu_irq abort_irq, omap_clk clk);

struct omap_uart_s;

                qemu_irq irq, omap_clk fclk, omap_clk iclk,

                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);

struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,

void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);

struct omap_mpuio_s;

                qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,

                omap_clk clk);

qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);

void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);

struct omap_gpio_s;

                qemu_irq irq, omap_clk clk);

qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);

void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);

    void *opaque;

};

struct omap_uwire_s;

                qemu_irq *irq, qemu_irq dma, omap_clk clk);

void omap_uwire_attach(struct omap_uwire_s *s,

                uWireSlave *slave, int chipselect);

                int chipselect);

struct omap_rtc_s;

                qemu_irq *irq, omap_clk clk);

struct I2SCodec {

    } in, out;

};

struct omap_mcbsp_s;

                qemu_irq *irq, qemu_irq *dma, omap_clk clk);

void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);

struct omap_lpg_s;

void omap_tap_init(struct omap_target_agent_s *ta,

                struct omap_mpu_state_s *mpu);

/* omap_lcdc.c */

struct omap_lcd_panel_s;

void omap_lcdc_reset(struct omap_lcd_panel_s *s);

                struct omap_dma_lcd_channel_s *dma,

/* omap_dss.c */

struct rfbi_chip_s {

struct omap_dss_s;

void omap_dss_reset(struct omap_dss_s *s);

struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,

                qemu_irq irq, qemu_irq drq,

                omap_clk fck1, omap_clk fck2, omap_clk ck54m,

                omap_clk ick1, omap_clk ick2);

/* omap_mmc.c */

struct omap_mmc_s;

                BlockDriverState *bd,

                qemu_irq irq, qemu_irq dma[], omap_clk clk);

struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,

/* omap_i2c.c */

struct omap_i2c_s;

                qemu_irq irq, qemu_irq *dma, omap_clk clk);

struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,

                qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);

    struct omap_dma_port_if_s {

        uint32_t (*read[3])(struct omap_mpu_state_s *s,

        void (*write[3])(struct omap_mpu_state_s *s,

        int (*addr_valid)(struct omap_mpu_state_s *s,

    } port[__omap_dma_port_last];

    unsigned long sdram_size;

#  error TARGET_PHYS_ADDR_BITS undefined

# endif

                uint32_t value);

                uint32_t value);

                uint32_t value);

void omap_mpu_wakeup(void *opaque, int irq, int req);

    int in;

};

{

    struct io_fn *s = opaque;

    uint32_t ret;

        fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);

    return ret;

}

{

    struct io_fn *s = opaque;

    uint32_t ret;

        fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);

    return ret;

}

{

    struct io_fn *s = opaque;

    uint32_t ret;

        fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);

    return ret;

}

{

    struct io_fn *s = opaque;

    s->mem_write[0](s->opaque, addr, value);

    s->in --;

}

{

    struct io_fn *s = opaque;

    s->mem_write[1](s->opaque, addr, value);

    s->in --;

}

{

    struct io_fn *s = opaque;