Archipelago » qemu

#include "pc.h"

/* Should signal the TCMI/GPMC */

{

    uint8_t ret;

    return ret;

}

                uint32_t value)

{

    uint8_t val8 = value;

    cpu_physical_memory_write(addr, (void *) &val8, 1);

}

{

    uint16_t ret;

    return ret;

}

                uint32_t value)

{

    uint16_t val16 = value;

    cpu_physical_memory_write(addr, (void *) &val16, 2);

}

{

    uint32_t ret;

    return ret;

}

                uint32_t value)

{

    OMAP_32B_REG(addr);

        bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;

}

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int i, offset = addr;

    return 0;

}

                uint32_t value)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    qemu_set_irq(s->parent_intr[1], 0);

}

                unsigned long size, unsigned char nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)

{

    return s;

}

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int offset = addr;

    return 0;

}

                uint32_t value)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    omap2_inth_write,

};

                int size, int nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq,

                omap_clk fclk, omap_clk iclk)

    timer->rate = omap_clk_getrate(timer->clk);

}

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;

    s->it_ena = 1;

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    int reset;

};

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;

    omap_timer_update(&s->timer);

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    struct omap_mpu_timer_s timer;

};

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;

    s->timer.ar = 1;

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

}

/* Ultra Low-Power Device Module */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    uint16_t ret;

        omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));

}

                struct omap_mpu_state_s *mpu)

{

    int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,

}

/* OMAP Pin Configuration */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

         omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));

}

                struct omap_mpu_state_s *mpu)

{

    int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,

}

/* Device Identification, Die Identification */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    return 0;

}

                uint32_t value)

{

    OMAP_BAD_REG(addr);

}

/* MPUI Control (Dummy) */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    s->mpui_ctrl = 0x0003ff1b;

}

                struct omap_mpu_state_s *mpu)

{

    int iomemtype = cpu_register_io_memory(omap_mpui_readfn,

    uint16_t enh_control;

};

{

    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;

    s->enh_control = 0x000f;

}

                qemu_irq abort_irq, omap_clk clk)

{

    int iomemtype;

}

/* Dummy Traffic Controller's Memory Interface */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    uint32_t ret;

    return 0;

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    mpu->tcmi_regs[0x40 >> 2] = 0x00000000;

}

                struct omap_mpu_state_s *mpu)

{

    int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,

}

/* Digital phase-locked loops control */

{

    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;

    omap_clk_setrate(s->dpll, 1, 1);

}

                omap_clk clk)

{

    int iomemtype = cpu_register_io_memory(omap_dpll_readfn,

/* UARTs */

struct omap_uart_s {

    SerialState *serial; /* TODO */

    struct omap_target_agent_s *ta;

    omap_clk fclk;

    s->clksel = 0;

}

                qemu_irq irq, omap_clk fclk, omap_clk iclk,

                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)

{

    return s;

}

{

    struct omap_uart_s *s = (struct omap_uart_s *) opaque;

    return 0;

}

                uint32_t value)

{

    struct omap_uart_s *s = (struct omap_uart_s *) opaque;

                qemu_irq irq, omap_clk fclk, omap_clk iclk,

                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)

{

    struct omap_uart_s *s = omap_uart_init(base, irq,

                    fclk, iclk, txdma, rxdma, chr);

    int iomemtype = cpu_register_io_memory(omap_uart_readfn,

}

/* MPU Clock/Reset/Power Mode Control */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    }

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    omap_badwidth_write16,

};

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    SET_ONOFF("dspxor_ck", 1);				/* EN_XORPCK */

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    s->clkm.dsp_rstct2 = 0x0000;

}

{

    int iomemtype[2] = {

        cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),

    s->row_latch = ~rows;

}

{

    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;

        omap_mpuio_kbd_update(s);

}

                qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,

                omap_clk clk)

{

    }

}

{

    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;

    s->pins = ~0;

}

                qemu_irq irq, omap_clk clk)

{

    int iomemtype;

    }

}

{

    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;

    s->setup[4] = 0;

}

                qemu_irq *irq, qemu_irq dma, omap_clk clk)

{

    int iomemtype;

    }

}

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    omap_pwl_update(s);

}

                omap_clk clk)

{

    int iomemtype;

}

/* Pulse-Width Tone module */

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;

    s->pwt.gcr = 0;

}

                omap_clk clk)

{

    int iomemtype;

    return (num & 15) + 10 * (num >> 4);

}

{

    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;

    omap_rtc_tick(s);

}

                qemu_irq *irq, omap_clk clk)

{

    int iomemtype;

        omap_mcbsp_rx_stop(s);

}

{

    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

    OMAP_BAD_REG(addr);

}

                uint32_t value)

{

    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

    qemu_del_timer(s->sink_timer);

}

                qemu_irq *irq, qemu_irq *dma, omap_clk clk)

{

    int iomemtype;

    omap_lpg_update(s);

}

{

    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    return 0;

}

                uint32_t value)

{

    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;

    omap_lpg_update(s);

}

{

    int iomemtype;

    struct omap_lpg_s *s = (struct omap_lpg_s *)

}

/* MPUI Peripheral Bridge configuration */

{

    if (addr == OMAP_MPUI_BASE)	/* CMR */

        return 0xfe4d;

}

static const struct omap_map_s {

    uint32_t size;

    const char *name;

} omap15xx_dsp_mm[] = {

/* DMA ports for OMAP1 */

static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,

{

    return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;

}

static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,

{

    return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;

}

static int omap_validate_imif_addr(struct omap_mpu_state_s *s,

{

    return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;

}

static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,

{

    return addr >= 0xfffb0000 && addr < 0xffff0000;

}

static int omap_validate_local_addr(struct omap_mpu_state_s *s,

{

    return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;

}

static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,

{

    return addr >= 0xe1010000 && addr < 0xe1020004;

}

    int i;

    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)

            qemu_mallocz(sizeof(struct omap_mpu_state_s));

    qemu_irq *cpu_irq;

    qemu_irq dma_irqs[6];

    DriveInfo *dinfo;