Revision 99a0949b hw/omap2.c
b/hw/omap2.c | ||
---|---|---|
263 | 263 |
omap_gp_timer_update(s); |
264 | 264 |
} |
265 | 265 |
|
266 |
static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
|
|
266 |
static uint32_t omap_gp_timer_readw(void *opaque, a_target_phys_addr addr)
|
|
267 | 267 |
{ |
268 | 268 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
269 | 269 |
|
... | ... | |
329 | 329 |
return 0; |
330 | 330 |
} |
331 | 331 |
|
332 |
static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
|
|
332 |
static uint32_t omap_gp_timer_readh(void *opaque, a_target_phys_addr addr)
|
|
333 | 333 |
{ |
334 | 334 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
335 | 335 |
uint32_t ret; |
... | ... | |
349 | 349 |
omap_gp_timer_readw, |
350 | 350 |
}; |
351 | 351 |
|
352 |
static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
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|
352 |
static void omap_gp_timer_write(void *opaque, a_target_phys_addr addr,
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|
353 | 353 |
uint32_t value) |
354 | 354 |
{ |
355 | 355 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
... | ... | |
449 | 449 |
} |
450 | 450 |
} |
451 | 451 |
|
452 |
static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
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|
452 |
static void omap_gp_timer_writeh(void *opaque, a_target_phys_addr addr,
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|
453 | 453 |
uint32_t value) |
454 | 454 |
{ |
455 | 455 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
... | ... | |
499 | 499 |
s->val = omap_synctimer_read(s); |
500 | 500 |
} |
501 | 501 |
|
502 |
static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
|
|
502 |
static uint32_t omap_synctimer_readw(void *opaque, a_target_phys_addr addr)
|
|
503 | 503 |
{ |
504 | 504 |
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
505 | 505 |
|
... | ... | |
515 | 515 |
return 0; |
516 | 516 |
} |
517 | 517 |
|
518 |
static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
|
|
518 |
static uint32_t omap_synctimer_readh(void *opaque, a_target_phys_addr addr)
|
|
519 | 519 |
{ |
520 | 520 |
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
521 | 521 |
uint32_t ret; |
... | ... | |
535 | 535 |
omap_synctimer_readw, |
536 | 536 |
}; |
537 | 537 |
|
538 |
static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
|
|
538 |
static void omap_synctimer_write(void *opaque, a_target_phys_addr addr,
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|
539 | 539 |
uint32_t value) |
540 | 540 |
{ |
541 | 541 |
OMAP_BAD_REG(addr); |
... | ... | |
658 | 658 |
s->delay = 0; |
659 | 659 |
} |
660 | 660 |
|
661 |
static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
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|
661 |
static uint32_t omap_gpio_module_read(void *opaque, a_target_phys_addr addr)
|
|
662 | 662 |
{ |
663 | 663 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
664 | 664 |
|
... | ... | |
730 | 730 |
return 0; |
731 | 731 |
} |
732 | 732 |
|
733 |
static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
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|
733 |
static void omap_gpio_module_write(void *opaque, a_target_phys_addr addr,
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|
734 | 734 |
uint32_t value) |
735 | 735 |
{ |
736 | 736 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
... | ... | |
872 | 872 |
} |
873 | 873 |
} |
874 | 874 |
|
875 |
static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
|
|
875 |
static uint32_t omap_gpio_module_readp(void *opaque, a_target_phys_addr addr)
|
|
876 | 876 |
{ |
877 | 877 |
return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); |
878 | 878 |
} |
879 | 879 |
|
880 |
static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
|
|
880 |
static void omap_gpio_module_writep(void *opaque, a_target_phys_addr addr,
|
|
881 | 881 |
uint32_t value) |
882 | 882 |
{ |
883 | 883 |
uint32_t cur = 0; |
... | ... | |
975 | 975 |
s->gpo = 0; |
976 | 976 |
} |
977 | 977 |
|
978 |
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
|
|
978 |
static uint32_t omap_gpif_top_read(void *opaque, a_target_phys_addr addr)
|
|
979 | 979 |
{ |
980 | 980 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
981 | 981 |
|
... | ... | |
1003 | 1003 |
return 0; |
1004 | 1004 |
} |
1005 | 1005 |
|
1006 |
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
|
|
1006 |
static void omap_gpif_top_write(void *opaque, a_target_phys_addr addr,
|
|
1007 | 1007 |
uint32_t value) |
1008 | 1008 |
{ |
1009 | 1009 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
... | ... | |
1187 | 1187 |
omap_mcspi_interrupt_update(s); |
1188 | 1188 |
} |
1189 | 1189 |
|
1190 |
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
|
|
1190 |
static uint32_t omap_mcspi_read(void *opaque, a_target_phys_addr addr)
|
|
1191 | 1191 |
{ |
1192 | 1192 |
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
1193 | 1193 |
int ch = 0; |
... | ... | |
1256 | 1256 |
return 0; |
1257 | 1257 |
} |
1258 | 1258 |
|
1259 |
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
|
|
1259 |
static void omap_mcspi_write(void *opaque, a_target_phys_addr addr,
|
|
1260 | 1260 |
uint32_t value) |
1261 | 1261 |
{ |
1262 | 1262 |
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
... | ... | |
1696 | 1696 |
omap_eac_interrupt_update(s); |
1697 | 1697 |
} |
1698 | 1698 |
|
1699 |
static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
|
|
1699 |
static uint32_t omap_eac_read(void *opaque, a_target_phys_addr addr)
|
|
1700 | 1700 |
{ |
1701 | 1701 |
struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
1702 | 1702 |
uint32_t ret; |
... | ... | |
1807 | 1807 |
return 0; |
1808 | 1808 |
} |
1809 | 1809 |
|
1810 |
static void omap_eac_write(void *opaque, target_phys_addr_t addr,
|
|
1810 |
static void omap_eac_write(void *opaque, a_target_phys_addr addr,
|
|
1811 | 1811 |
uint32_t value) |
1812 | 1812 |
{ |
1813 | 1813 |
struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
... | ... | |
2014 | 2014 |
omap_sti_interrupt_update(s); |
2015 | 2015 |
} |
2016 | 2016 |
|
2017 |
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
|
|
2017 |
static uint32_t omap_sti_read(void *opaque, a_target_phys_addr addr)
|
|
2018 | 2018 |
{ |
2019 | 2019 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
2020 | 2020 |
|
... | ... | |
2050 | 2050 |
return 0; |
2051 | 2051 |
} |
2052 | 2052 |
|
2053 |
static void omap_sti_write(void *opaque, target_phys_addr_t addr,
|
|
2053 |
static void omap_sti_write(void *opaque, a_target_phys_addr addr,
|
|
2054 | 2054 |
uint32_t value) |
2055 | 2055 |
{ |
2056 | 2056 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
... | ... | |
2108 | 2108 |
omap_sti_write, |
2109 | 2109 |
}; |
2110 | 2110 |
|
2111 |
static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
|
|
2111 |
static uint32_t omap_sti_fifo_read(void *opaque, a_target_phys_addr addr)
|
|
2112 | 2112 |
{ |
2113 | 2113 |
OMAP_BAD_REG(addr); |
2114 | 2114 |
return 0; |
2115 | 2115 |
} |
2116 | 2116 |
|
2117 |
static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
|
|
2117 |
static void omap_sti_fifo_write(void *opaque, a_target_phys_addr addr,
|
|
2118 | 2118 |
uint32_t value) |
2119 | 2119 |
{ |
2120 | 2120 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
... | ... | |
2147 | 2147 |
}; |
2148 | 2148 |
|
2149 | 2149 |
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, |
2150 |
target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
|
|
2150 |
a_target_phys_addr channel_base, qemu_irq irq, omap_clk clk,
|
|
2151 | 2151 |
CharDriverState *chr) |
2152 | 2152 |
{ |
2153 | 2153 |
int iomemtype; |
... | ... | |
2175 | 2175 |
struct omap_l4_s *bus; |
2176 | 2176 |
int regions; |
2177 | 2177 |
struct omap_l4_region_s *start; |
2178 |
target_phys_addr_t base;
|
|
2178 |
a_target_phys_addr base;
|
|
2179 | 2179 |
uint32_t component; |
2180 | 2180 |
uint32_t control; |
2181 | 2181 |
uint32_t status; |
2182 | 2182 |
}; |
2183 | 2183 |
|
2184 | 2184 |
struct omap_l4_s { |
2185 |
target_phys_addr_t base;
|
|
2185 |
a_target_phys_addr base;
|
|
2186 | 2186 |
int ta_num; |
2187 | 2187 |
struct omap_target_agent_s ta[0]; |
2188 | 2188 |
}; |
... | ... | |
2213 | 2213 |
return omap_l4_io_entries ++; |
2214 | 2214 |
} |
2215 | 2215 |
|
2216 |
static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
|
|
2216 |
static uint32_t omap_l4_io_readb(void *opaque, a_target_phys_addr addr)
|
|
2217 | 2217 |
{ |
2218 | 2218 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
2219 | 2219 |
|
2220 | 2220 |
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr); |
2221 | 2221 |
} |
2222 | 2222 |
|
2223 |
static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
|
|
2223 |
static uint32_t omap_l4_io_readh(void *opaque, a_target_phys_addr addr)
|
|
2224 | 2224 |
{ |
2225 | 2225 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
2226 | 2226 |
|
2227 | 2227 |
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr); |
2228 | 2228 |
} |
2229 | 2229 |
|
2230 |
static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
|
|
2230 |
static uint32_t omap_l4_io_readw(void *opaque, a_target_phys_addr addr)
|
|
2231 | 2231 |
{ |
2232 | 2232 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
2233 | 2233 |
|
2234 | 2234 |
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr); |
2235 | 2235 |
} |
2236 | 2236 |
|
2237 |
static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
|
|
2237 |
static void omap_l4_io_writeb(void *opaque, a_target_phys_addr addr,
|
|
2238 | 2238 |
uint32_t value) |
2239 | 2239 |
{ |
2240 | 2240 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
... | ... | |
2242 | 2242 |
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value); |
2243 | 2243 |
} |
2244 | 2244 |
|
2245 |
static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
|
|
2245 |
static void omap_l4_io_writeh(void *opaque, a_target_phys_addr addr,
|
|
2246 | 2246 |
uint32_t value) |
2247 | 2247 |
{ |
2248 | 2248 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
... | ... | |
2250 | 2250 |
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value); |
2251 | 2251 |
} |
2252 | 2252 |
|
2253 |
static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
|
|
2253 |
static void omap_l4_io_writew(void *opaque, a_target_phys_addr addr,
|
|
2254 | 2254 |
uint32_t value) |
2255 | 2255 |
{ |
2256 | 2256 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
... | ... | |
2271 | 2271 |
}; |
2272 | 2272 |
#endif |
2273 | 2273 |
|
2274 |
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
|
|
2274 |
struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num)
|
|
2275 | 2275 |
{ |
2276 | 2276 |
struct omap_l4_s *bus = qemu_mallocz( |
2277 | 2277 |
sizeof(*bus) + ta_num * sizeof(*bus->ta)); |
... | ... | |
2299 | 2299 |
return bus; |
2300 | 2300 |
} |
2301 | 2301 |
|
2302 |
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
|
|
2302 |
static uint32_t omap_l4ta_read(void *opaque, a_target_phys_addr addr)
|
|
2303 | 2303 |
{ |
2304 | 2304 |
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
2305 | 2305 |
|
... | ... | |
2318 | 2318 |
return 0; |
2319 | 2319 |
} |
2320 | 2320 |
|
2321 |
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
|
|
2321 |
static void omap_l4ta_write(void *opaque, a_target_phys_addr addr,
|
|
2322 | 2322 |
uint32_t value) |
2323 | 2323 |
{ |
2324 | 2324 |
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
... | ... | |
2356 | 2356 |
#define L4TAO(n) ((n) + 39) |
2357 | 2357 |
|
2358 | 2358 |
static struct omap_l4_region_s { |
2359 |
target_phys_addr_t offset;
|
|
2359 |
a_target_phys_addr offset;
|
|
2360 | 2360 |
size_t size; |
2361 | 2361 |
int access; |
2362 | 2362 |
} omap_l4_region[125] = { |
... | ... | |
2584 | 2584 |
return ta; |
2585 | 2585 |
} |
2586 | 2586 |
|
2587 |
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
|
|
2587 |
a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
|
|
2588 | 2588 |
int iotype) |
2589 | 2589 |
{ |
2590 |
target_phys_addr_t base;
|
|
2590 |
a_target_phys_addr base;
|
|
2591 | 2591 |
ssize_t size; |
2592 | 2592 |
#ifdef L4_MUX_HACK |
2593 | 2593 |
int i; |
... | ... | |
2622 | 2622 |
} |
2623 | 2623 |
|
2624 | 2624 |
/* TEST-Chip-level TAP */ |
2625 |
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
|
|
2625 |
static uint32_t omap_tap_read(void *opaque, a_target_phys_addr addr)
|
|
2626 | 2626 |
{ |
2627 | 2627 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2628 | 2628 |
|
... | ... | |
2686 | 2686 |
return 0; |
2687 | 2687 |
} |
2688 | 2688 |
|
2689 |
static void omap_tap_write(void *opaque, target_phys_addr_t addr,
|
|
2689 |
static void omap_tap_write(void *opaque, a_target_phys_addr addr,
|
|
2690 | 2690 |
uint32_t value) |
2691 | 2691 |
{ |
2692 | 2692 |
OMAP_BAD_REG(addr); |
... | ... | |
2753 | 2753 |
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ |
2754 | 2754 |
} |
2755 | 2755 |
|
2756 |
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
|
|
2756 |
static uint32_t omap_prcm_read(void *opaque, a_target_phys_addr addr)
|
|
2757 | 2757 |
{ |
2758 | 2758 |
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
2759 | 2759 |
uint32_t ret; |
... | ... | |
3060 | 3060 |
} |
3061 | 3061 |
} |
3062 | 3062 |
|
3063 |
static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
|
|
3063 |
static void omap_prcm_write(void *opaque, a_target_phys_addr addr,
|
|
3064 | 3064 |
uint32_t value) |
3065 | 3065 |
{ |
3066 | 3066 |
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
... | ... | |
3540 | 3540 |
uint32_t msuspendmux[5]; |
3541 | 3541 |
}; |
3542 | 3542 |
|
3543 |
static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
|
|
3543 |
static uint32_t omap_sysctl_read8(void *opaque, a_target_phys_addr addr)
|
|
3544 | 3544 |
{ |
3545 | 3545 |
|
3546 | 3546 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
... | ... | |
3565 | 3565 |
return 0; |
3566 | 3566 |
} |
3567 | 3567 |
|
3568 |
static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
|
|
3568 |
static uint32_t omap_sysctl_read(void *opaque, a_target_phys_addr addr)
|
|
3569 | 3569 |
{ |
3570 | 3570 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
3571 | 3571 |
|
... | ... | |
3665 | 3665 |
return 0; |
3666 | 3666 |
} |
3667 | 3667 |
|
3668 |
static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
|
|
3668 |
static void omap_sysctl_write8(void *opaque, a_target_phys_addr addr,
|
|
3669 | 3669 |
uint32_t value) |
3670 | 3670 |
{ |
3671 | 3671 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
... | ... | |
3689 | 3689 |
} |
3690 | 3690 |
} |
3691 | 3691 |
|
3692 |
static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
|
|
3692 |
static void omap_sysctl_write(void *opaque, a_target_phys_addr addr,
|
|
3693 | 3693 |
uint32_t value) |
3694 | 3694 |
{ |
3695 | 3695 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
... | ... | |
3907 | 3907 |
s->config = 0x10; |
3908 | 3908 |
} |
3909 | 3909 |
|
3910 |
static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
|
|
3910 |
static uint32_t omap_sdrc_read(void *opaque, a_target_phys_addr addr)
|
|
3911 | 3911 |
{ |
3912 | 3912 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
3913 | 3913 |
|
... | ... | |
3957 | 3957 |
return 0; |
3958 | 3958 |
} |
3959 | 3959 |
|
3960 |
static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
|
|
3960 |
static void omap_sdrc_write(void *opaque, a_target_phys_addr addr,
|
|
3961 | 3961 |
uint32_t value) |
3962 | 3962 |
{ |
3963 | 3963 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
... | ... | |
4026 | 4026 |
omap_sdrc_write, |
4027 | 4027 |
}; |
4028 | 4028 |
|
4029 |
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
|
|
4029 |
struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base)
|
|
4030 | 4030 |
{ |
4031 | 4031 |
int iomemtype; |
4032 | 4032 |
struct omap_sdrc_s *s = (struct omap_sdrc_s *) |
... | ... | |
4056 | 4056 |
int prefcount; |
4057 | 4057 |
struct omap_gpmc_cs_file_s { |
4058 | 4058 |
uint32_t config[7]; |
4059 |
target_phys_addr_t base;
|
|
4059 |
a_target_phys_addr base;
|
|
4060 | 4060 |
size_t size; |
4061 | 4061 |
int iomemtype; |
4062 |
void (*base_update)(void *opaque, target_phys_addr_t new);
|
|
4062 |
void (*base_update)(void *opaque, a_target_phys_addr new);
|
|
4063 | 4063 |
void (*unmap)(void *opaque); |
4064 | 4064 |
void *opaque; |
4065 | 4065 |
} cs_file[8]; |
... | ... | |
4151 | 4151 |
ecc_reset(&s->ecc[i]); |
4152 | 4152 |
} |
4153 | 4153 |
|
4154 |
static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
|
|
4154 |
static uint32_t omap_gpmc_read(void *opaque, a_target_phys_addr addr)
|
|
4155 | 4155 |
{ |
4156 | 4156 |
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
4157 | 4157 |
int cs; |
... | ... | |
4248 | 4248 |
return 0; |
4249 | 4249 |
} |
4250 | 4250 |
|
4251 |
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
|
|
4251 |
static void omap_gpmc_write(void *opaque, a_target_phys_addr addr,
|
|
4252 | 4252 |
uint32_t value) |
4253 | 4253 |
{ |
4254 | 4254 |
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
... | ... | |
4400 | 4400 |
omap_gpmc_write, |
4401 | 4401 |
}; |
4402 | 4402 |
|
4403 |
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
|
|
4403 |
struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq)
|
|
4404 | 4404 |
{ |
4405 | 4405 |
int iomemtype; |
4406 | 4406 |
struct omap_gpmc_s *s = (struct omap_gpmc_s *) |
... | ... | |
4416 | 4416 |
} |
4417 | 4417 |
|
4418 | 4418 |
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
4419 |
void (*base_upd)(void *opaque, target_phys_addr_t new),
|
|
4419 |
void (*base_upd)(void *opaque, a_target_phys_addr new),
|
|
4420 | 4420 |
void (*unmap)(void *opaque), void *opaque) |
4421 | 4421 |
{ |
4422 | 4422 |
struct omap_gpmc_cs_file_s *f; |
... | ... | |
4475 | 4475 |
} |
4476 | 4476 |
|
4477 | 4477 |
static int omap2_validate_addr(struct omap_mpu_state_s *s, |
4478 |
target_phys_addr_t addr)
|
|
4478 |
a_target_phys_addr addr)
|
|
4479 | 4479 |
{ |
4480 | 4480 |
return 1; |
4481 | 4481 |
} |
... | ... | |
4492 | 4492 |
{ |
4493 | 4493 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
4494 | 4494 |
qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
4495 |
ram_addr_t sram_base, q2_base;
|
|
4495 |
a_ram_addr sram_base, q2_base;
|
|
4496 | 4496 |
qemu_irq *cpu_irq; |
4497 | 4497 |
qemu_irq dma_irqs[4]; |
4498 | 4498 |
omap_clk gpio_clks[4]; |
Also available in: Unified diff