Revision 99a0949b hw/omap_dss.c
| b/hw/omap_dss.c | ||
|---|---|---|
| 59 | 59 |
int nx; |
| 60 | 60 |
int ny; |
| 61 | 61 |
|
| 62 |
target_phys_addr_t addr[3];
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| 62 |
a_target_phys_addr addr[3];
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| 63 | 63 |
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| 64 | 64 |
uint32_t attr; |
| 65 | 65 |
uint32_t tresh; |
| ... | ... | |
| 167 | 167 |
omap_dispc_interrupt_update(s); |
| 168 | 168 |
} |
| 169 | 169 |
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| 170 |
static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
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static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
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| 171 | 171 |
{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 173 | 173 |
|
| ... | ... | |
| 200 | 200 |
return 0; |
| 201 | 201 |
} |
| 202 | 202 |
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static void omap_diss_write(void *opaque, target_phys_addr_t addr,
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static void omap_diss_write(void *opaque, a_target_phys_addr addr,
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| 204 | 204 |
uint32_t value) |
| 205 | 205 |
{
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| 206 | 206 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| ... | ... | |
| 242 | 242 |
omap_diss_write, |
| 243 | 243 |
}; |
| 244 | 244 |
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static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
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static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
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| 246 | 246 |
{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 248 | 248 |
|
| ... | ... | |
| 362 | 362 |
return 0; |
| 363 | 363 |
} |
| 364 | 364 |
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| 365 |
static void omap_disc_write(void *opaque, target_phys_addr_t addr,
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static void omap_disc_write(void *opaque, a_target_phys_addr addr,
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| 366 | 366 |
uint32_t value) |
| 367 | 367 |
{
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| 368 | 368 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| ... | ... | |
| 488 | 488 |
s->dispc.invalidate = 1; |
| 489 | 489 |
break; |
| 490 | 490 |
case 0x080: /* DISPC_GFX_BA0 */ |
| 491 |
s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[0] = (a_target_phys_addr) value;
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| 492 | 492 |
s->dispc.invalidate = 1; |
| 493 | 493 |
break; |
| 494 | 494 |
case 0x084: /* DISPC_GFX_BA1 */ |
| 495 |
s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[1] = (a_target_phys_addr) value;
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| 496 | 496 |
s->dispc.invalidate = 1; |
| 497 | 497 |
break; |
| 498 | 498 |
case 0x088: /* DISPC_GFX_POSITION */ |
| ... | ... | |
| 529 | 529 |
s->dispc.l[0].wininc = value; |
| 530 | 530 |
break; |
| 531 | 531 |
case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
| 532 |
s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[2] = (a_target_phys_addr) value;
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| 533 | 533 |
s->dispc.invalidate = 1; |
| 534 | 534 |
break; |
| 535 | 535 |
|
| ... | ... | |
| 594 | 594 |
static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
| 595 | 595 |
{
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| 596 | 596 |
void *data; |
| 597 |
target_phys_addr_t len;
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target_phys_addr_t data_addr;
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a_target_phys_addr len;
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a_target_phys_addr data_addr;
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| 599 | 599 |
int pitch; |
| 600 | 600 |
static void *bounce_buffer; |
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static target_phys_addr_t bounce_len;
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static a_target_phys_addr bounce_len;
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| 602 | 602 |
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| 603 | 603 |
if (!s->rfbi.enable || s->rfbi.busy) |
| 604 | 604 |
return; |
| ... | ... | |
| 655 | 655 |
omap_dispc_interrupt_update(s); |
| 656 | 656 |
} |
| 657 | 657 |
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| 658 |
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
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static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
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| 659 | 659 |
{
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| 660 | 660 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 661 | 661 |
|
| ... | ... | |
| 717 | 717 |
return 0; |
| 718 | 718 |
} |
| 719 | 719 |
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static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
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static void omap_rfbi_write(void *opaque, a_target_phys_addr addr,
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| 721 | 721 |
uint32_t value) |
| 722 | 722 |
{
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| 723 | 723 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| ... | ... | |
| 853 | 853 |
omap_rfbi_write, |
| 854 | 854 |
}; |
| 855 | 855 |
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static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
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static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
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| 857 | 857 |
{
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| 858 | 858 |
switch (addr) {
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| 859 | 859 |
case 0x00: /* REV_ID */ |
| ... | ... | |
| 908 | 908 |
return 0; |
| 909 | 909 |
} |
| 910 | 910 |
|
| 911 |
static void omap_venc_write(void *opaque, target_phys_addr_t addr,
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static void omap_venc_write(void *opaque, a_target_phys_addr addr,
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| 912 | 912 |
uint32_t value) |
| 913 | 913 |
{
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| 914 | 914 |
switch (addr) {
|
| ... | ... | |
| 972 | 972 |
omap_venc_write, |
| 973 | 973 |
}; |
| 974 | 974 |
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| 975 |
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
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| 975 |
static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
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| 976 | 976 |
{
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| 977 | 977 |
switch (addr) {
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| 978 | 978 |
case 0x0a8: /* SBIMERRLOGA */ |
| ... | ... | |
| 993 | 993 |
return 0; |
| 994 | 994 |
} |
| 995 | 995 |
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| 996 |
static void omap_im3_write(void *opaque, target_phys_addr_t addr,
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| 996 |
static void omap_im3_write(void *opaque, a_target_phys_addr addr,
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| 997 | 997 |
uint32_t value) |
| 998 | 998 |
{
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| 999 | 999 |
switch (addr) {
|
| ... | ... | |
| 1023 | 1023 |
}; |
| 1024 | 1024 |
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| 1025 | 1025 |
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
| 1026 |
target_phys_addr_t l3_base,
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| 1026 |
a_target_phys_addr l3_base,
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| 1027 | 1027 |
qemu_irq irq, qemu_irq drq, |
| 1028 | 1028 |
omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
| 1029 | 1029 |
omap_clk ick1, omap_clk ick2) |
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