Revision 99a0949b hw/onenand.c
| b/hw/onenand.c | ||
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| 33 | 33 |
typedef struct {
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uint32_t id; |
| 35 | 35 |
int shift; |
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target_phys_addr_t base;
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a_target_phys_addr base;
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qemu_irq intr; |
| 38 | 38 |
qemu_irq rdy; |
| 39 | 39 |
BlockDriverState *bdrv; |
| ... | ... | |
| 41 | 41 |
uint8_t *image; |
| 42 | 42 |
uint8_t *otp; |
| 43 | 43 |
uint8_t *current; |
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ram_addr_t ram;
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a_ram_addr ram;
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uint8_t *boot[2]; |
| 46 | 46 |
uint8_t *data[2][2]; |
| 47 | 47 |
int iomemtype; |
| ... | ... | |
| 96 | 96 |
ONEN_LOCK_UNLOCKED = 1 << 2, |
| 97 | 97 |
}; |
| 98 | 98 |
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void onenand_base_update(void *opaque, target_phys_addr_t new)
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void onenand_base_update(void *opaque, a_target_phys_addr new)
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{
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OneNANDState *s = (OneNANDState *) opaque; |
| 102 | 102 |
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| ... | ... | |
| 443 | 443 |
onenand_intr_update(s); |
| 444 | 444 |
} |
| 445 | 445 |
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static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
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static uint32_t onenand_read(void *opaque, a_target_phys_addr addr)
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{
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OneNANDState *s = (OneNANDState *) opaque; |
| 449 | 449 |
int offset = addr >> s->shift; |
| ... | ... | |
| 507 | 507 |
return 0; |
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} |
| 509 | 509 |
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static void onenand_write(void *opaque, target_phys_addr_t addr,
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static void onenand_write(void *opaque, a_target_phys_addr addr,
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uint32_t value) |
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{
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OneNANDState *s = (OneNANDState *) opaque; |
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