Revision 99a0949b hw/openpic.c
| b/hw/openpic.c | ||
|---|---|---|
| 166 | 166 |
IRQ_SPECIAL = 0x08, |
| 167 | 167 |
}; |
| 168 | 168 |
|
| 169 |
typedef struct IRQ_queue_t {
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| 169 |
typedef struct IRQ_queue {
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|
| 170 | 170 |
uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
| 171 | 171 |
int next; |
| 172 | 172 |
int priority; |
| 173 |
} IRQ_queue_t;
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|
| 173 |
} a_IRQ_queue;
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|
| 174 | 174 |
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| 175 |
typedef struct IRQ_src_t {
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| 175 |
typedef struct IRQ_src {
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| 176 | 176 |
uint32_t ipvp; /* IRQ vector/priority register */ |
| 177 | 177 |
uint32_t ide; /* IRQ destination register */ |
| 178 | 178 |
int type; |
| 179 | 179 |
int last_cpu; |
| 180 | 180 |
int pending; /* TRUE if IRQ is pending */ |
| 181 |
} IRQ_src_t;
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|
| 181 |
} a_IRQ_src;
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|
| 182 | 182 |
|
| 183 | 183 |
enum IPVP_bits {
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| 184 | 184 |
IPVP_MASK = 31, |
| ... | ... | |
| 192 | 192 |
#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
| 193 | 193 |
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) |
| 194 | 194 |
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| 195 |
typedef struct IRQ_dst_t {
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| 195 |
typedef struct IRQ_dst {
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| 196 | 196 |
uint32_t tfrr; |
| 197 | 197 |
uint32_t pctp; /* CPU current task priority */ |
| 198 | 198 |
uint32_t pcsr; /* CPU sensitivity register */ |
| 199 |
IRQ_queue_t raised;
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| 200 |
IRQ_queue_t servicing;
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| 199 |
a_IRQ_queue raised;
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| 200 |
a_IRQ_queue servicing;
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| 201 | 201 |
qemu_irq *irqs; |
| 202 |
} IRQ_dst_t;
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| 202 |
} a_IRQ_dst;
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| 203 | 203 |
|
| 204 |
typedef struct openpic_t {
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| 204 |
typedef struct openpic {
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| 205 | 205 |
PCIDevice pci_dev; |
| 206 | 206 |
int mem_index; |
| 207 | 207 |
/* Global registers */ |
| ... | ... | |
| 213 | 213 |
uint32_t spve; /* Spurious vector register */ |
| 214 | 214 |
uint32_t tifr; /* Timer frequency reporting register */ |
| 215 | 215 |
/* Source registers */ |
| 216 |
IRQ_src_t src[MAX_IRQ];
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| 216 |
a_IRQ_src src[MAX_IRQ];
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|
| 217 | 217 |
/* Local registers per output pin */ |
| 218 |
IRQ_dst_t dst[MAX_CPU];
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| 218 |
a_IRQ_dst dst[MAX_CPU];
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|
| 219 | 219 |
int nb_cpus; |
| 220 | 220 |
/* Timer registers */ |
| 221 | 221 |
struct {
|
| ... | ... | |
| 242 | 242 |
int irq_tim0; |
| 243 | 243 |
int need_swap; |
| 244 | 244 |
void (*reset) (void *); |
| 245 |
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
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|
| 246 |
} openpic_t;
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| 245 |
void (*irq_raise) (struct openpic *, int, a_IRQ_src *);
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| 246 |
} a_openpic;
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| 247 | 247 |
|
| 248 |
static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
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| 248 |
static inline uint32_t openpic_swap32(a_openpic *opp, uint32_t val)
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| 249 | 249 |
{
|
| 250 | 250 |
if (opp->need_swap) |
| 251 | 251 |
return bswap32(val); |
| ... | ... | |
| 253 | 253 |
return val; |
| 254 | 254 |
} |
| 255 | 255 |
|
| 256 |
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
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| 256 |
static inline void IRQ_setbit (a_IRQ_queue *q, int n_IRQ)
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|
| 257 | 257 |
{
|
| 258 | 258 |
set_bit(q->queue, n_IRQ); |
| 259 | 259 |
} |
| 260 | 260 |
|
| 261 |
static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
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| 261 |
static inline void IRQ_resetbit (a_IRQ_queue *q, int n_IRQ)
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|
| 262 | 262 |
{
|
| 263 | 263 |
reset_bit(q->queue, n_IRQ); |
| 264 | 264 |
} |
| 265 | 265 |
|
| 266 |
static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
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| 266 |
static inline int IRQ_testbit (a_IRQ_queue *q, int n_IRQ)
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|
| 267 | 267 |
{
|
| 268 | 268 |
return test_bit(q->queue, n_IRQ); |
| 269 | 269 |
} |
| 270 | 270 |
|
| 271 |
static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
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|
| 271 |
static void IRQ_check (a_openpic *opp, a_IRQ_queue *q)
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|
| 272 | 272 |
{
|
| 273 | 273 |
int next, i; |
| 274 | 274 |
int priority; |
| ... | ... | |
| 289 | 289 |
q->priority = priority; |
| 290 | 290 |
} |
| 291 | 291 |
|
| 292 |
static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
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| 292 |
static int IRQ_get_next (a_openpic *opp, a_IRQ_queue *q)
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| 293 | 293 |
{
|
| 294 | 294 |
if (q->next == -1) {
|
| 295 | 295 |
/* XXX: optimize */ |
| ... | ... | |
| 299 | 299 |
return q->next; |
| 300 | 300 |
} |
| 301 | 301 |
|
| 302 |
static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
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| 302 |
static void IRQ_local_pipe (a_openpic *opp, int n_CPU, int n_IRQ)
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| 303 | 303 |
{
|
| 304 |
IRQ_dst_t *dst;
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| 305 |
IRQ_src_t *src;
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| 304 |
a_IRQ_dst *dst;
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| 305 |
a_IRQ_src *src;
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| 306 | 306 |
int priority; |
| 307 | 307 |
|
| 308 | 308 |
dst = &opp->dst[n_CPU]; |
| ... | ... | |
| 341 | 341 |
} |
| 342 | 342 |
|
| 343 | 343 |
/* update pic state because registers for n_IRQ have changed value */ |
| 344 |
static void openpic_update_irq(openpic_t *opp, int n_IRQ)
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| 344 |
static void openpic_update_irq(a_openpic *opp, int n_IRQ)
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| 345 | 345 |
{
|
| 346 |
IRQ_src_t *src;
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| 346 |
a_IRQ_src *src;
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| 347 | 347 |
int i; |
| 348 | 348 |
|
| 349 | 349 |
src = &opp->src[n_IRQ]; |
| ... | ... | |
| 399 | 399 |
|
| 400 | 400 |
static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
| 401 | 401 |
{
|
| 402 |
openpic_t *opp = opaque;
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| 403 |
IRQ_src_t *src;
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| 402 |
a_openpic *opp = opaque;
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| 403 |
a_IRQ_src *src;
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| 404 | 404 |
|
| 405 | 405 |
src = &opp->src[n_IRQ]; |
| 406 | 406 |
DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
|
| ... | ... | |
| 420 | 420 |
|
| 421 | 421 |
static void openpic_reset (void *opaque) |
| 422 | 422 |
{
|
| 423 |
openpic_t *opp = (openpic_t *)opaque;
|
|
| 423 |
a_openpic *opp = (a_openpic *)opaque;
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|
| 424 | 424 |
int i; |
| 425 | 425 |
|
| 426 | 426 |
opp->glbc = 0x80000000; |
| ... | ... | |
| 441 | 441 |
for (i = 0; i < MAX_CPU; i++) {
|
| 442 | 442 |
opp->dst[i].pctp = 0x0000000F; |
| 443 | 443 |
opp->dst[i].pcsr = 0x00000000; |
| 444 |
memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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|
| 445 |
memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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|
| 444 |
memset(&opp->dst[i].raised, 0, sizeof(a_IRQ_queue));
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| 445 |
memset(&opp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
|
|
| 446 | 446 |
} |
| 447 | 447 |
/* Initialise timers */ |
| 448 | 448 |
for (i = 0; i < MAX_TMR; i++) {
|
| ... | ... | |
| 466 | 466 |
opp->glbc = 0x00000000; |
| 467 | 467 |
} |
| 468 | 468 |
|
| 469 |
static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
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|
| 469 |
static inline uint32_t read_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg)
|
|
| 470 | 470 |
{
|
| 471 | 471 |
uint32_t retval; |
| 472 | 472 |
|
| ... | ... | |
| 482 | 482 |
return retval; |
| 483 | 483 |
} |
| 484 | 484 |
|
| 485 |
static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
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|
| 485 |
static inline void write_IRQreg (a_openpic *opp, int n_IRQ,
|
|
| 486 | 486 |
uint32_t reg, uint32_t val) |
| 487 | 487 |
{
|
| 488 | 488 |
uint32_t tmp; |
| ... | ... | |
| 510 | 510 |
|
| 511 | 511 |
#if 0 // Code provision for Intel model |
| 512 | 512 |
#if MAX_DBL > 0 |
| 513 |
static uint32_t read_doorbell_register (openpic_t *opp,
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| 513 |
static uint32_t read_doorbell_register (a_openpic *opp,
|
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| 514 | 514 |
int n_dbl, uint32_t offset) |
| 515 | 515 |
{
|
| 516 | 516 |
uint32_t retval; |
| ... | ... | |
| 548 | 548 |
#endif |
| 549 | 549 |
|
| 550 | 550 |
#if MAX_MBX > 0 |
| 551 |
static uint32_t read_mailbox_register (openpic_t *opp,
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| 551 |
static uint32_t read_mailbox_register (a_openpic *opp,
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|
| 552 | 552 |
int n_mbx, uint32_t offset) |
| 553 | 553 |
{
|
| 554 | 554 |
uint32_t retval; |
| ... | ... | |
| 568 | 568 |
return retval; |
| 569 | 569 |
} |
| 570 | 570 |
|
| 571 |
static void write_mailbox_register (openpic_t *opp, int n_mbx,
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| 571 |
static void write_mailbox_register (a_openpic *opp, int n_mbx,
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|
| 572 | 572 |
uint32_t address, uint32_t value) |
| 573 | 573 |
{
|
| 574 | 574 |
switch (offset) {
|
| ... | ... | |
| 586 | 586 |
#endif |
| 587 | 587 |
#endif /* 0 : Code provision for Intel model */ |
| 588 | 588 |
|
| 589 |
static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 589 |
static void openpic_gbl_write (void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 590 | 590 |
{
|
| 591 |
openpic_t *opp = opaque;
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| 592 |
IRQ_dst_t *dst;
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|
| 591 |
a_openpic *opp = opaque;
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| 592 |
a_IRQ_dst *dst;
|
|
| 593 | 593 |
int idx; |
| 594 | 594 |
|
| 595 | 595 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 646 | 646 |
} |
| 647 | 647 |
} |
| 648 | 648 |
|
| 649 |
static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
|
|
| 649 |
static uint32_t openpic_gbl_read (void *opaque, a_target_phys_addr addr)
|
|
| 650 | 650 |
{
|
| 651 |
openpic_t *opp = opaque;
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|
| 651 |
a_openpic *opp = opaque;
|
|
| 652 | 652 |
uint32_t retval; |
| 653 | 653 |
|
| 654 | 654 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
| ... | ... | |
| 700 | 700 |
|
| 701 | 701 |
static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
| 702 | 702 |
{
|
| 703 |
openpic_t *opp = opaque;
|
|
| 703 |
a_openpic *opp = opaque;
|
|
| 704 | 704 |
int idx; |
| 705 | 705 |
|
| 706 | 706 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 734 | 734 |
|
| 735 | 735 |
static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
| 736 | 736 |
{
|
| 737 |
openpic_t *opp = opaque;
|
|
| 737 |
a_openpic *opp = opaque;
|
|
| 738 | 738 |
uint32_t retval; |
| 739 | 739 |
int idx; |
| 740 | 740 |
|
| ... | ... | |
| 770 | 770 |
|
| 771 | 771 |
static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
| 772 | 772 |
{
|
| 773 |
openpic_t *opp = opaque;
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|
| 773 |
a_openpic *opp = opaque;
|
|
| 774 | 774 |
int idx; |
| 775 | 775 |
|
| 776 | 776 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 792 | 792 |
|
| 793 | 793 |
static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
| 794 | 794 |
{
|
| 795 |
openpic_t *opp = opaque;
|
|
| 795 |
a_openpic *opp = opaque;
|
|
| 796 | 796 |
uint32_t retval; |
| 797 | 797 |
int idx; |
| 798 | 798 |
|
| ... | ... | |
| 817 | 817 |
return retval; |
| 818 | 818 |
} |
| 819 | 819 |
|
| 820 |
static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 820 |
static void openpic_cpu_write (void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 821 | 821 |
{
|
| 822 |
openpic_t *opp = opaque;
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| 823 |
IRQ_src_t *src;
|
|
| 824 |
IRQ_dst_t *dst;
|
|
| 822 |
a_openpic *opp = opaque;
|
|
| 823 |
a_IRQ_src *src;
|
|
| 824 |
a_IRQ_dst *dst;
|
|
| 825 | 825 |
int idx, s_IRQ, n_IRQ; |
| 826 | 826 |
|
| 827 | 827 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 878 | 878 |
} |
| 879 | 879 |
} |
| 880 | 880 |
|
| 881 |
static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
|
|
| 881 |
static uint32_t openpic_cpu_read (void *opaque, a_target_phys_addr addr)
|
|
| 882 | 882 |
{
|
| 883 |
openpic_t *opp = opaque;
|
|
| 884 |
IRQ_src_t *src;
|
|
| 885 |
IRQ_dst_t *dst;
|
|
| 883 |
a_openpic *opp = opaque;
|
|
| 884 |
a_IRQ_src *src;
|
|
| 885 |
a_IRQ_dst *dst;
|
|
| 886 | 886 |
uint32_t retval; |
| 887 | 887 |
int idx, n_IRQ; |
| 888 | 888 |
|
| ... | ... | |
| 955 | 955 |
} |
| 956 | 956 |
|
| 957 | 957 |
static void openpic_buggy_write (void *opaque, |
| 958 |
target_phys_addr_t addr, uint32_t val)
|
|
| 958 |
a_target_phys_addr addr, uint32_t val)
|
|
| 959 | 959 |
{
|
| 960 | 960 |
printf("Invalid OPENPIC write access !\n");
|
| 961 | 961 |
} |
| 962 | 962 |
|
| 963 |
static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
|
|
| 963 |
static uint32_t openpic_buggy_read (void *opaque, a_target_phys_addr addr)
|
|
| 964 | 964 |
{
|
| 965 | 965 |
printf("Invalid OPENPIC read access !\n");
|
| 966 | 966 |
|
| ... | ... | |
| 968 | 968 |
} |
| 969 | 969 |
|
| 970 | 970 |
static void openpic_writel (void *opaque, |
| 971 |
target_phys_addr_t addr, uint32_t val)
|
|
| 971 |
a_target_phys_addr addr, uint32_t val)
|
|
| 972 | 972 |
{
|
| 973 |
openpic_t *opp = opaque;
|
|
| 973 |
a_openpic *opp = opaque;
|
|
| 974 | 974 |
|
| 975 | 975 |
addr &= 0x3FFFF; |
| 976 | 976 |
DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
|
| ... | ... | |
| 989 | 989 |
} |
| 990 | 990 |
} |
| 991 | 991 |
|
| 992 |
static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
|
|
| 992 |
static uint32_t openpic_readl (void *opaque,a_target_phys_addr addr)
|
|
| 993 | 993 |
{
|
| 994 |
openpic_t *opp = opaque;
|
|
| 994 |
a_openpic *opp = opaque;
|
|
| 995 | 995 |
uint32_t retval; |
| 996 | 996 |
|
| 997 | 997 |
addr &= 0x3FFFF; |
| ... | ... | |
| 1028 | 1028 |
static void openpic_map(PCIDevice *pci_dev, int region_num, |
| 1029 | 1029 |
uint32_t addr, uint32_t size, int type) |
| 1030 | 1030 |
{
|
| 1031 |
openpic_t *opp;
|
|
| 1031 |
a_openpic *opp;
|
|
| 1032 | 1032 |
|
| 1033 | 1033 |
DPRINTF("Map OpenPIC\n");
|
| 1034 |
opp = (openpic_t *)pci_dev;
|
|
| 1034 |
opp = (a_openpic *)pci_dev;
|
|
| 1035 | 1035 |
/* Global registers */ |
| 1036 | 1036 |
DPRINTF("Register OPENPIC gbl %08x => %08x\n",
|
| 1037 | 1037 |
addr + 0x1000, addr + 0x1000 + 0x100); |
| ... | ... | |
| 1053 | 1053 |
#endif |
| 1054 | 1054 |
} |
| 1055 | 1055 |
|
| 1056 |
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
|
|
| 1056 |
static void openpic_save_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
|
|
| 1057 | 1057 |
{
|
| 1058 | 1058 |
unsigned int i; |
| 1059 | 1059 |
|
| ... | ... | |
| 1066 | 1066 |
|
| 1067 | 1067 |
static void openpic_save(QEMUFile* f, void *opaque) |
| 1068 | 1068 |
{
|
| 1069 |
openpic_t *opp = (openpic_t *)opaque;
|
|
| 1069 |
a_openpic *opp = (a_openpic *)opaque;
|
|
| 1070 | 1070 |
unsigned int i; |
| 1071 | 1071 |
|
| 1072 | 1072 |
qemu_put_be32s(f, &opp->frep); |
| ... | ... | |
| 1117 | 1117 |
pci_device_save(&opp->pci_dev, f); |
| 1118 | 1118 |
} |
| 1119 | 1119 |
|
| 1120 |
static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
|
|
| 1120 |
static void openpic_load_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
|
|
| 1121 | 1121 |
{
|
| 1122 | 1122 |
unsigned int i; |
| 1123 | 1123 |
|
| ... | ... | |
| 1130 | 1130 |
|
| 1131 | 1131 |
static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
| 1132 | 1132 |
{
|
| 1133 |
openpic_t *opp = (openpic_t *)opaque;
|
|
| 1133 |
a_openpic *opp = (a_openpic *)opaque;
|
|
| 1134 | 1134 |
unsigned int i; |
| 1135 | 1135 |
|
| 1136 | 1136 |
if (version_id != 1) |
| ... | ... | |
| 1184 | 1184 |
return pci_device_load(&opp->pci_dev, f); |
| 1185 | 1185 |
} |
| 1186 | 1186 |
|
| 1187 |
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
|
|
| 1187 |
static void openpic_irq_raise(a_openpic *opp, int n_CPU, a_IRQ_src *src)
|
|
| 1188 | 1188 |
{
|
| 1189 | 1189 |
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
| 1190 | 1190 |
} |
| ... | ... | |
| 1192 | 1192 |
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
| 1193 | 1193 |
qemu_irq **irqs, qemu_irq irq_out) |
| 1194 | 1194 |
{
|
| 1195 |
openpic_t *opp;
|
|
| 1195 |
a_openpic *opp;
|
|
| 1196 | 1196 |
uint8_t *pci_conf; |
| 1197 | 1197 |
int i, m; |
| 1198 | 1198 |
|
| ... | ... | |
| 1200 | 1200 |
if (nb_cpus != 1) |
| 1201 | 1201 |
return NULL; |
| 1202 | 1202 |
if (bus) {
|
| 1203 |
opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
|
|
| 1203 |
opp = (a_openpic *)pci_register_device(bus, "OpenPIC", sizeof(a_openpic),
|
|
| 1204 | 1204 |
-1, NULL, NULL); |
| 1205 | 1205 |
if (opp == NULL) |
| 1206 | 1206 |
return NULL; |
| ... | ... | |
| 1215 | 1215 |
pci_register_bar((PCIDevice *)opp, 0, 0x40000, |
| 1216 | 1216 |
PCI_ADDRESS_SPACE_MEM, &openpic_map); |
| 1217 | 1217 |
} else {
|
| 1218 |
opp = qemu_mallocz(sizeof(openpic_t));
|
|
| 1218 |
opp = qemu_mallocz(sizeof(a_openpic));
|
|
| 1219 | 1219 |
} |
| 1220 | 1220 |
opp->mem_index = cpu_register_io_memory(openpic_read, |
| 1221 | 1221 |
openpic_write, opp); |
| ... | ... | |
| 1261 | 1261 |
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); |
| 1262 | 1262 |
} |
| 1263 | 1263 |
|
| 1264 |
static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
|
|
| 1264 |
static void mpic_irq_raise(a_openpic *mpp, int n_CPU, a_IRQ_src *src)
|
|
| 1265 | 1265 |
{
|
| 1266 | 1266 |
int n_ci = IDR_CI0 - n_CPU; |
| 1267 | 1267 |
|
| ... | ... | |
| 1275 | 1275 |
|
| 1276 | 1276 |
static void mpic_reset (void *opaque) |
| 1277 | 1277 |
{
|
| 1278 |
openpic_t *mpp = (openpic_t *)opaque;
|
|
| 1278 |
a_openpic *mpp = (a_openpic *)opaque;
|
|
| 1279 | 1279 |
int i; |
| 1280 | 1280 |
|
| 1281 | 1281 |
mpp->glbc = 0x80000000; |
| ... | ... | |
| 1293 | 1293 |
for (i = 0; i < MAX_CPU; i++) {
|
| 1294 | 1294 |
mpp->dst[i].pctp = 0x0000000F; |
| 1295 | 1295 |
mpp->dst[i].tfrr = 0x00000000; |
| 1296 |
memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
|
|
| 1296 |
memset(&mpp->dst[i].raised, 0, sizeof(a_IRQ_queue));
|
|
| 1297 | 1297 |
mpp->dst[i].raised.next = -1; |
| 1298 |
memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
|
|
| 1298 |
memset(&mpp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
|
|
| 1299 | 1299 |
mpp->dst[i].servicing.next = -1; |
| 1300 | 1300 |
} |
| 1301 | 1301 |
/* Initialise timers */ |
| ... | ... | |
| 1307 | 1307 |
mpp->glbc = 0x00000000; |
| 1308 | 1308 |
} |
| 1309 | 1309 |
|
| 1310 |
static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
| 1310 |
static void mpic_timer_write (void *opaque, a_target_phys_addr addr, uint32_t val)
|
|
| 1311 | 1311 |
{
|
| 1312 |
openpic_t *mpp = opaque;
|
|
| 1312 |
a_openpic *mpp = opaque;
|
|
| 1313 | 1313 |
int idx, cpu; |
| 1314 | 1314 |
|
| 1315 | 1315 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 1340 | 1340 |
} |
| 1341 | 1341 |
} |
| 1342 | 1342 |
|
| 1343 |
static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
|
|
| 1343 |
static uint32_t mpic_timer_read (void *opaque, a_target_phys_addr addr)
|
|
| 1344 | 1344 |
{
|
| 1345 |
openpic_t *mpp = opaque;
|
|
| 1345 |
a_openpic *mpp = opaque;
|
|
| 1346 | 1346 |
uint32_t retval; |
| 1347 | 1347 |
int idx, cpu; |
| 1348 | 1348 |
|
| ... | ... | |
| 1375 | 1375 |
return retval; |
| 1376 | 1376 |
} |
| 1377 | 1377 |
|
| 1378 |
static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
|
|
| 1378 |
static void mpic_src_ext_write (void *opaque, a_target_phys_addr addr,
|
|
| 1379 | 1379 |
uint32_t val) |
| 1380 | 1380 |
{
|
| 1381 |
openpic_t *mpp = opaque;
|
|
| 1381 |
a_openpic *mpp = opaque;
|
|
| 1382 | 1382 |
int idx = MPIC_EXT_IRQ; |
| 1383 | 1383 |
|
| 1384 | 1384 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 1398 | 1398 |
} |
| 1399 | 1399 |
} |
| 1400 | 1400 |
|
| 1401 |
static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
|
|
| 1401 |
static uint32_t mpic_src_ext_read (void *opaque, a_target_phys_addr addr)
|
|
| 1402 | 1402 |
{
|
| 1403 |
openpic_t *mpp = opaque;
|
|
| 1403 |
a_openpic *mpp = opaque;
|
|
| 1404 | 1404 |
uint32_t retval; |
| 1405 | 1405 |
int idx = MPIC_EXT_IRQ; |
| 1406 | 1406 |
|
| ... | ... | |
| 1425 | 1425 |
return retval; |
| 1426 | 1426 |
} |
| 1427 | 1427 |
|
| 1428 |
static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
|
|
| 1428 |
static void mpic_src_int_write (void *opaque, a_target_phys_addr addr,
|
|
| 1429 | 1429 |
uint32_t val) |
| 1430 | 1430 |
{
|
| 1431 |
openpic_t *mpp = opaque;
|
|
| 1431 |
a_openpic *mpp = opaque;
|
|
| 1432 | 1432 |
int idx = MPIC_INT_IRQ; |
| 1433 | 1433 |
|
| 1434 | 1434 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 1448 | 1448 |
} |
| 1449 | 1449 |
} |
| 1450 | 1450 |
|
| 1451 |
static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
|
|
| 1451 |
static uint32_t mpic_src_int_read (void *opaque, a_target_phys_addr addr)
|
|
| 1452 | 1452 |
{
|
| 1453 |
openpic_t *mpp = opaque;
|
|
| 1453 |
a_openpic *mpp = opaque;
|
|
| 1454 | 1454 |
uint32_t retval; |
| 1455 | 1455 |
int idx = MPIC_INT_IRQ; |
| 1456 | 1456 |
|
| ... | ... | |
| 1475 | 1475 |
return retval; |
| 1476 | 1476 |
} |
| 1477 | 1477 |
|
| 1478 |
static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
|
|
| 1478 |
static void mpic_src_msg_write (void *opaque, a_target_phys_addr addr,
|
|
| 1479 | 1479 |
uint32_t val) |
| 1480 | 1480 |
{
|
| 1481 |
openpic_t *mpp = opaque;
|
|
| 1481 |
a_openpic *mpp = opaque;
|
|
| 1482 | 1482 |
int idx = MPIC_MSG_IRQ; |
| 1483 | 1483 |
|
| 1484 | 1484 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 1498 | 1498 |
} |
| 1499 | 1499 |
} |
| 1500 | 1500 |
|
| 1501 |
static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
|
|
| 1501 |
static uint32_t mpic_src_msg_read (void *opaque, a_target_phys_addr addr)
|
|
| 1502 | 1502 |
{
|
| 1503 |
openpic_t *mpp = opaque;
|
|
| 1503 |
a_openpic *mpp = opaque;
|
|
| 1504 | 1504 |
uint32_t retval; |
| 1505 | 1505 |
int idx = MPIC_MSG_IRQ; |
| 1506 | 1506 |
|
| ... | ... | |
| 1525 | 1525 |
return retval; |
| 1526 | 1526 |
} |
| 1527 | 1527 |
|
| 1528 |
static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
|
|
| 1528 |
static void mpic_src_msi_write (void *opaque, a_target_phys_addr addr,
|
|
| 1529 | 1529 |
uint32_t val) |
| 1530 | 1530 |
{
|
| 1531 |
openpic_t *mpp = opaque;
|
|
| 1531 |
a_openpic *mpp = opaque;
|
|
| 1532 | 1532 |
int idx = MPIC_MSI_IRQ; |
| 1533 | 1533 |
|
| 1534 | 1534 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
| ... | ... | |
| 1547 | 1547 |
} |
| 1548 | 1548 |
} |
| 1549 | 1549 |
} |
| 1550 |
static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
|
|
| 1550 |
static uint32_t mpic_src_msi_read (void *opaque, a_target_phys_addr addr)
|
|
| 1551 | 1551 |
{
|
| 1552 |
openpic_t *mpp = opaque;
|
|
| 1552 |
a_openpic *mpp = opaque;
|
|
| 1553 | 1553 |
uint32_t retval; |
| 1554 | 1554 |
int idx = MPIC_MSI_IRQ; |
| 1555 | 1555 |
|
| ... | ... | |
| 1657 | 1657 |
&mpic_src_msi_read, |
| 1658 | 1658 |
}; |
| 1659 | 1659 |
|
| 1660 |
qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
|
|
| 1660 |
qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus,
|
|
| 1661 | 1661 |
qemu_irq **irqs, qemu_irq irq_out) |
| 1662 | 1662 |
{
|
| 1663 |
openpic_t *mpp;
|
|
| 1663 |
a_openpic *mpp;
|
|
| 1664 | 1664 |
int i; |
| 1665 | 1665 |
struct {
|
| 1666 | 1666 |
CPUReadMemoryFunc * const *read; |
| 1667 | 1667 |
CPUWriteMemoryFunc * const *write; |
| 1668 |
target_phys_addr_t start_addr;
|
|
| 1669 |
ram_addr_t size;
|
|
| 1668 |
a_target_phys_addr start_addr;
|
|
| 1669 |
a_ram_addr size;
|
|
| 1670 | 1670 |
} const list[] = {
|
| 1671 | 1671 |
{mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
|
| 1672 | 1672 |
{mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
|
| ... | ... | |
| 1681 | 1681 |
if (nb_cpus != 1) |
| 1682 | 1682 |
return NULL; |
| 1683 | 1683 |
|
| 1684 |
mpp = qemu_mallocz(sizeof(openpic_t));
|
|
| 1684 |
mpp = qemu_mallocz(sizeof(a_openpic));
|
|
| 1685 | 1685 |
|
| 1686 | 1686 |
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
|
| 1687 | 1687 |
int mem_index; |
Also available in: Unified diff