Revision 99a0949b hw/ppc440.c

b/hw/ppc440.c
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    256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
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};
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CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,


  		





  
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CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip,


  		





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                        const unsigned int pci_irq_nrs[4], int do_init,


  		





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                        const char *cpu_model)


  		





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{


  		





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    target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];


  		





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    target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];


  		





  
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    a_target_phys_addr ram_bases[PPC440EP_SDRAM_NR_BANKS];


  		





  
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    a_target_phys_addr ram_sizes[PPC440EP_SDRAM_NR_BANKS];


  		





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    CPUState *env;


  		





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    qemu_irq *pic;


  		





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    qemu_irq *irqs;


  		












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