Revision 99a0949b hw/ppc4xx.h
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/* PowerPC 4xx core initialization */ |
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CPUState *ppc4xx_init (const char *cpu_model, |
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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a_clk_setup *cpu_clk, a_clk_setup *tb_clk,
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uint32_t sysclk); |
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/* PowerPC 4xx universal interrupt controller */ |
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qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
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uint32_t dcr_base, int has_ssr, int has_vr); |
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ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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target_phys_addr_t ram_bases[],
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target_phys_addr_t ram_sizes[],
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a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks,
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a_target_phys_addr ram_bases[],
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a_target_phys_addr ram_sizes[],
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const unsigned int sdram_bank_sizes[]); |
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void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
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target_phys_addr_t *ram_bases,
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target_phys_addr_t *ram_sizes,
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a_target_phys_addr *ram_bases,
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a_target_phys_addr *ram_sizes,
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int do_init); |
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PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], |
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers);
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a_target_phys_addr config_space,
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a_target_phys_addr int_ack,
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a_target_phys_addr special_cycle,
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a_target_phys_addr registers);
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#endif /* !defined(PPC_4XX_H) */ |
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