Revision 99a0949b hw/pxa2xx_pcmcia.c
b/hw/pxa2xx_pcmcia.c | ||
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}; |
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static uint32_t pxa2xx_pcmcia_common_read(void *opaque, |
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target_phys_addr_t offset)
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a_target_phys_addr offset)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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} |
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static void pxa2xx_pcmcia_common_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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a_target_phys_addr offset, uint32_t value)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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... | ... | |
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} |
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static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, |
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target_phys_addr_t offset)
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a_target_phys_addr offset)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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... | ... | |
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} |
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static void pxa2xx_pcmcia_attr_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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a_target_phys_addr offset, uint32_t value)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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... | ... | |
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} |
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static uint32_t pxa2xx_pcmcia_io_read(void *opaque, |
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target_phys_addr_t offset)
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a_target_phys_addr offset)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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... | ... | |
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} |
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static void pxa2xx_pcmcia_io_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value)
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a_target_phys_addr offset, uint32_t value)
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{ |
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PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; |
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qemu_set_irq(s->irq, level); |
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} |
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(a_target_phys_addr base)
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{ |
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int iomemtype; |
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PXA2xxPCMCIAState *s; |
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