/hw/sh_pci.c - Diff - qemu - Greek Research and Technology Network's projects

Revision 99a0949b hw/sh_pci.c

b/hw/sh_pci.c
34	34	uint32_t iobr;
35	35	} SHPCIC;
36	36
37		static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
	37	static void sh_pci_reg_write (void *p, a_target_phys_addr addr, uint32_t val)
38	38	{
39	39	SHPCIC *pcic = p;
40	40	switch(addr) {
...	...
56	56	}
57	57	}
58	58
59		static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
	59	static uint32_t sh_pci_reg_read (void *p, a_target_phys_addr addr)
60	60	{
61	61	SHPCIC *pcic = p;
62	62	switch(addr) {
...	...
70	70	return 0;
71	71	}
72	72
73		static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
	73	static void sh_pci_data_write (SHPCIC *pcic, a_target_phys_addr addr,
74	74	uint32_t val, int size)
75	75	{
76	76	pci_data_write(pcic->bus, addr + pcic->mbr, val, size);
77	77	}
78	78
79		static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
	79	static uint32_t sh_pci_mem_read (SHPCIC *pcic, a_target_phys_addr addr,
80	80	int size)
81	81	{
82	82	return pci_data_read(pcic->bus, addr + pcic->mbr, size);
83	83	}
84	84
85		static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
	85	static void sh_pci_writeb (void *p, a_target_phys_addr addr, uint32_t val)
86	86	{
87	87	sh_pci_data_write(p, addr, val, 1);
88	88	}
89	89
90		static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)
	90	static void sh_pci_writew (void *p, a_target_phys_addr addr, uint32_t val)
91	91	{
92	92	sh_pci_data_write(p, addr, val, 2);
93	93	}
94	94
95		static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)
	95	static void sh_pci_writel (void *p, a_target_phys_addr addr, uint32_t val)
96	96	{
97	97	sh_pci_data_write(p, addr, val, 4);
98	98	}
99	99
100		static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)
	100	static uint32_t sh_pci_readb (void *p, a_target_phys_addr addr)
101	101	{
102	102	return sh_pci_mem_read(p, addr, 1);
103	103	}
104	104
105		static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)
	105	static uint32_t sh_pci_readw (void *p, a_target_phys_addr addr)
106	106	{
107	107	return sh_pci_mem_read(p, addr, 2);
108	108	}
109	109
110		static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
	110	static uint32_t sh_pci_readl (void *p, a_target_phys_addr addr)
111	111	{
112	112	return sh_pci_mem_read(p, addr, 4);
113	113	}
114	114
115		static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
	115	static int sh_pci_addr2port(SHPCIC *pcic, a_target_phys_addr addr)
116	116	{
117	117	return addr + pcic->iobr;
118	118	}
119	119
120		static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
	120	static void sh_pci_outb (void *p, a_target_phys_addr addr, uint32_t val)
121	121	{
122	122	cpu_outb(sh_pci_addr2port(p, addr), val);
123	123	}
124	124
125		static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)
	125	static void sh_pci_outw (void *p, a_target_phys_addr addr, uint32_t val)
126	126	{
127	127	cpu_outw(sh_pci_addr2port(p, addr), val);
128	128	}
129	129
130		static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)
	130	static void sh_pci_outl (void *p, a_target_phys_addr addr, uint32_t val)
131	131	{
132	132	cpu_outl(sh_pci_addr2port(p, addr), val);
133	133	}
134	134
135		static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)
	135	static uint32_t sh_pci_inb (void *p, a_target_phys_addr addr)
136	136	{
137	137	return cpu_inb(sh_pci_addr2port(p, addr));
138	138	}
139	139
140		static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)
	140	static uint32_t sh_pci_inw (void *p, a_target_phys_addr addr)
141	141	{
142	142	return cpu_inw(sh_pci_addr2port(p, addr));
143	143	}
144	144
145		static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
	145	static uint32_t sh_pci_inl (void *p, a_target_phys_addr addr)
146	146	{
147	147	return cpu_inl(sh_pci_addr2port(p, addr));
148	148	}

Also available in: Unified diff

Archipelago » qemu

Revision 99a0949b hw/sh_pci.c