Revision 99a0949b hw/sh_timer.c
| b/hw/sh_timer.c | ||
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| 57 | 57 |
s->int_level = new_level; |
| 58 | 58 |
} |
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static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
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static uint32_t sh_timer_read(void *opaque, a_target_phys_addr offset)
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{
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sh_timer_state *s = (sh_timer_state *)opaque; |
| 63 | 63 |
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| ... | ... | |
| 77 | 77 |
} |
| 78 | 78 |
} |
| 79 | 79 |
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static void sh_timer_write(void *opaque, target_phys_addr_t offset,
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static void sh_timer_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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sh_timer_state *s = (sh_timer_state *)opaque; |
| ... | ... | |
| 217 | 217 |
int feat; |
| 218 | 218 |
} tmu012_state; |
| 219 | 219 |
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static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
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static uint32_t tmu012_read(void *opaque, a_target_phys_addr offset)
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{
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tmu012_state *s = (tmu012_state *)opaque; |
| 223 | 223 |
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| ... | ... | |
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return 0; |
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} |
| 249 | 249 |
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static void tmu012_write(void *opaque, target_phys_addr_t offset,
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static void tmu012_write(void *opaque, a_target_phys_addr offset,
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uint32_t value) |
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{
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tmu012_state *s = (tmu012_state *)opaque; |
| ... | ... | |
| 303 | 303 |
tmu012_write |
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}; |
| 305 | 305 |
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void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
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void tmu012_init(a_target_phys_addr base, int feat, uint32_t freq,
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| 307 | 307 |
qemu_irq ch0_irq, qemu_irq ch1_irq, |
| 308 | 308 |
qemu_irq ch2_irq0, qemu_irq ch2_irq1) |
| 309 | 309 |
{
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