Revision 99a0949b hw/sm501.c
| b/hw/sm501.c | ||
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| 451 | 451 |
DisplayState *ds; |
| 452 | 452 |
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| 453 | 453 |
/* status & internal resources */ |
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target_phys_addr_t base;
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a_target_phys_addr base;
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| 455 | 455 |
uint32_t local_mem_size_index; |
| 456 | 456 |
uint8_t * local_mem; |
| 457 |
ram_addr_t local_mem_offset;
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a_ram_addr local_mem_offset;
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| 458 | 458 |
uint32_t last_width; |
| 459 | 459 |
uint32_t last_height; |
| 460 | 460 |
|
| ... | ... | |
| 526 | 526 |
return index; |
| 527 | 527 |
} |
| 528 | 528 |
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static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
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static uint32_t sm501_system_config_read(void *opaque, a_target_phys_addr addr)
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{
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SM501State * s = (SM501State *)opaque; |
| 532 | 532 |
uint32_t ret = 0; |
| ... | ... | |
| 579 | 579 |
} |
| 580 | 580 |
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| 581 | 581 |
static void sm501_system_config_write(void *opaque, |
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target_phys_addr_t addr, uint32_t value)
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a_target_phys_addr addr, uint32_t value)
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{
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SM501State * s = (SM501State *)opaque; |
| 585 | 585 |
SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
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| ... | ... | |
| 638 | 638 |
&sm501_system_config_write, |
| 639 | 639 |
}; |
| 640 | 640 |
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static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
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static uint32_t sm501_palette_read(void *opaque, a_target_phys_addr addr)
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{
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| 643 | 643 |
SM501State * s = (SM501State *)opaque; |
| 644 | 644 |
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
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| ... | ... | |
| 651 | 651 |
} |
| 652 | 652 |
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| 653 | 653 |
static void sm501_palette_write(void *opaque, |
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target_phys_addr_t addr, uint32_t value)
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a_target_phys_addr addr, uint32_t value)
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| 655 | 655 |
{
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| 656 | 656 |
SM501State * s = (SM501State *)opaque; |
| 657 | 657 |
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
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| ... | ... | |
| 664 | 664 |
*(uint32_t*)&s->dc_palette[addr] = value; |
| 665 | 665 |
} |
| 666 | 666 |
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static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
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static uint32_t sm501_disp_ctrl_read(void *opaque, a_target_phys_addr addr)
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| 668 | 668 |
{
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| 669 | 669 |
SM501State * s = (SM501State *)opaque; |
| 670 | 670 |
uint32_t ret = 0; |
| ... | ... | |
| 759 | 759 |
} |
| 760 | 760 |
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| 761 | 761 |
static void sm501_disp_ctrl_write(void *opaque, |
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target_phys_addr_t addr,
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a_target_phys_addr addr,
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uint32_t value) |
| 764 | 764 |
{
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| 765 | 765 |
SM501State * s = (SM501State *)opaque; |
| ... | ... | |
| 972 | 972 |
int y_start = -1; |
| 973 | 973 |
int page_min = 0x7fffffff; |
| 974 | 974 |
int page_max = -1; |
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ram_addr_t offset = s->local_mem_offset;
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a_ram_addr offset = s->local_mem_offset;
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| 976 | 976 |
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| 977 | 977 |
/* choose draw_line function */ |
| 978 | 978 |
switch (s->dc_crt_control & 3) {
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| ... | ... | |
| 1006 | 1006 |
/* draw each line according to conditions */ |
| 1007 | 1007 |
for (y = 0; y < height; y++) {
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| 1008 | 1008 |
int update = full_update; |
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ram_addr_t page0 = offset & TARGET_PAGE_MASK;
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ram_addr_t page1 = (offset + width * src_bpp - 1) & TARGET_PAGE_MASK;
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ram_addr_t page;
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a_ram_addr page0 = offset & TARGET_PAGE_MASK;
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a_ram_addr page1 = (offset + width * src_bpp - 1) & TARGET_PAGE_MASK;
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a_ram_addr page;
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| 1012 | 1012 |
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| 1013 | 1013 |
/* check dirty flags for each line */ |
| 1014 | 1014 |
for (page = page0; page <= page1; page += TARGET_PAGE_SIZE) |
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